WO1994011952A1

WO1994011952A1 - Pseudo clock extractor

Info

Publication number: WO1994011952A1
Application number: PCT/US1993/010516
Authority: WO
Inventors: Keith L. Klinger
Original assignee: Ampex Systems Corp
Current assignee: Ampex Systems Corp
Priority date: 1992-11-13
Filing date: 1993-11-03
Publication date: 1994-05-26
Anticipated expiration: 1995-05-13

Abstract

In a digital audio or digital video recording channel, a pseudo clock extractor receives a reference clock (212, 306) having a periodicity n times (n ≥ 4) or preferably 2n times (n ≥ 2) the frequency of an audio data clock signal, the reference clock triggering in and synchronizing to a biphase-mark encoded data stream (222, 302). Data transitions in the data stream are detected and each transition resets a modulo-counter (240) to a pre-specified value so that in combination with the reference signal, the audio data clock signal (242, 326) is synchronous to the triggered-in data stream, the audio data clock rising transition edges being near half-bit cell centers of the triggered-in data stream.

Description

PSEIJDO CLOCK EXTRACTOR

P ACKGROϋNP OF THE INVENTION

FIELD OF THE INYENTION

The present invention generally relates to digitally encoded information processing and, more particularly, to the extraction of a data clock signal from a digitally encoded data stream.

PESCRTPTTON OF THE RELATED ART

Digital information processing offers numerous advantages over its analog counterpart. One advantage is the very little or no loss of digitized information content under digital processing environment This environment includes digital processing of analog signals such as audio and video information. When audio and video information are recorded on a physical medium, playback degradation effects due to medium deterioration can be circumvented by copying digitized data sample values from the deteriorated medium to a new medium. As a result, digital processing of audio and video information produces little loss of information which is especially important in audio and video editing activities.

Typically, the above digital processing begins with a data processing apparatus receiving from a transmission channel an incoming data stream containing audio and video information. For transmission purposes, the digitized audio and video information are encoded according to a set of channel code rules. Some of these channel codes, such as Manchester codes, represent digitized logic information, l's or 0's, by the presence or the absence of data transitions in the encoded data stream. A general property of these channel codes is that data clock information is also embedded in the encoded data stream.

Therefore, instead of generating a data clock signal independent of the incoming data stream, it can be extracted from the incoming data stream for ensuing data processing activities.

Biphase-mark code is a Manchester code. Under biphase-mark coding, each source data bit, either a logical 0 or a logical 1 in a data stream, is represented by two half -bit cells which is also called a two-cell doublet. A half-bit cell spans half of the source data bit time duration. Each coding doublet begins, and therefore also ends, with a data transition. More specifically, a source-data bit 0 generates a doublet with no further transition until the end of the doublet. A source-data bit 1 generates a transition between the cells of the doublet. Thus, a series of source-data bit 0 will be represented as a series of alternating doublets having logic values 00 and doublets having logic values 11, while source data bits l's will be represented either as the doublets having logic values 10's or doublets having logic values 01's.

A biphase-mark encoded data stream will therefore have no transition lengths, or intervals between adjacent transitions in the data stream, greater than one data bit period, or two half-bit cells. Similarly, such encoded data stream will have no transition lengths shorter than one half of a coding data bit period, or one half-bit cell. In other words, within each doublet, there may be either none or one transition. These characteristics enable a receiver of a data stream to extract the data clock information from the data stream.

A known art commonly referred to as "ringer circuits" are typically used to extract embedded clock information. It bases its operation on an oscillating circuit having a pre¬ determined resonating frequency. An appropriately defined input pulse will "ring" the circuit and a series of the defined pulses will produce a series of "rings". This series of "rings" represents the extracted clock.

Phase-locked loop is another circuit embodiment well known in the art. It also can be used to extract embedded clock information. Like the "ringer circuit", it contains an oscillator. It is a device that varies the frequency of a voltage-controlled oscillator to match an input signal frequency.

In addition of being relatively complex, both known art require a number of digital and analog components such as oscillators which are not amenable to advanced miniaturization. Analog and discrete components in both known art occupy valuable space and can be difficult to calibrate, and are nearly impossible to manufacture as a part of digital ASIC. Moreover, the overall expense in interfacing analog and digital elements in a typical clock extraction circuit is far more costly than if the operation was completely digital.

A simple and calibration-free digital circuit capable of being a part of a digital ASIC that does not require any analog and discrete components presents a much better approach. In addition, this clock extraction apparatus can be digitally implemented at a considerable cost and space savings over the ringer and phase-locked-loop implementations.

SUMMARY OF THE INVENTION In digital audio or digital video operations which include but not limited to data recording, data are processed while synchronized to an associated data clock signal. In processing audio or video data in a data recording channel, as long as rising data transition edges of the data clock occur near centers of half-bit cells of the data stream, it is not necessary to have the data clock signal oscillating precisely at its pre-determined or desired frequency.

The present invention provides a digital pseudo clock extraction apparatus and method for receiving and extracting a clock signal from an encoded data stream. The word, pseudo, refers to that the resulting data clock signal, on the average, oscillates at the pre-determined frequency, but may not oscillate at that frequency in any given clock cycle. This apparatus and method of invention generates a data clock at a pre-determined frequency synchronous to the data stream data bits. The data clock signal has exactly one rising transition edge for each half-bit cell of channel code encoded data. Theses channel codes represent digitized logic information using data transitions. These channel codes include but not limited to biphase-mark channel code.

A pseudo clock extractor receives a reference clock which has a frequency n times a pre-determined data clock frequency, n being an integer greater than or equal to 4. However, for the ease of digital implementation, the preferred reference clock has a frequency 2ⁿ times a pre-determined data clock frequency, n being an integer greater than or equal to 2. This reference clock in combination with a synchronizer triggers in a channel code encoded data stream and synchronizes the data stream to the reference clock. The reference clock signal also generates the desired data clock running at the pre¬ determined frequency from a modulo-2ⁿ (divide by 2ⁿ) counter. Synchronization between the triggered-in data stream and the data clock produced by the modulo-2ⁿ counter is accomplished by a transition edge detector.

This transition edge detector responds to data transitions in the data stream generating a defined pulse for each data transition it detects. The modulo-2ⁿ counter is arranged so that every time the defined pulse occurs, the counter is reset and that the resulting data clock always has its rising transition edges near the centers of half-bit cells of the data stream for minimum noise interference.

More specifically, a number of standards has been developed to establish guidelines for digital audio engineering; one of which is Audio Engineering Society (AES) Recommended Practice AES3-1992 ANSI S4.40-1992. In this Recommended Practice for digital audio engineering, digitized audio data are encoded in a biphase-mark code. AES Recommended Practice AES3-1992 ANSI S4.40-1992 allows an audio sampling frequency of 48kHz. Within each sampling period, there are two 32-bit audio sample segments. This results in a 6.144MHz clock signal for a biphase-mark encoded audio data stream. A 24.576 MHz reference clock has 2^ times the frequency of the 6.144 MHz data clock. The corresponding counter for this embodiment is a modulo-4 counter. Since a biphase-mark encoded data stream may have a transition in the middle of a data bit, it is therefore necessary to have at least one data clock period per one half-bit cell for adequate data processing.

Normally, the reference clock-triggered counter will count four times for every half-bit cell of the audio data stream and the entire data bit in the data stream spans 8 reference clock periods. The audio data clock can be caused to have rising transition edges near centers of the half-bit cells by being responsive to the data transitions and the reference clock count

A better understanding of the present invention will become apparent to those skilled in the art by considering the following detailed description taken together with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWING

FIGURE 1 is a circuit diagram illustrating principal elements of a prior art ringer-type clock extractor.

FIGURE 2 is a functional block diagram of an embodiment in accordance to the present invention.

FIGURE 3 A is a functional logic diagram of an embodiment in accordance to the present invention.

FIGURE 3B is a partial timing diagram for the embodiment of FIGURE 3 A.

FIGURE 3C is a partial truth table of the counter employed in the embodiment depicted in FIGURE 3A.

FIGURE 4A & 4B are timing diagrams illustrating two possible signal timing relationships for FIG. 3A when received data are jittery and asynchronous to a reference clock.

FIGURE 5 is a functional block diagram of another embodiment in accordance to the present invention. DETAILED DESCRIPTION OF THE INVENTION

In the following description of embodiments of the present invention, like elements will be designated by like reference numerals, and the description of similar elements may not be repeated with reference to subsequent drawing figures related to the various embodiments of the invention.

A ringer circuit is typically used to extract the clock information embedded in a data stream. A prior art ringer circuit is shown in FIG. 1. The operation of the ringer circuit operation is explained as follows. The CLOCK EXTRACTION - RINGER CIRCUIT has three sequential logic elements, EDGE DETECT, RINGER OSCILLATOR AND TTL RESTORE. In general, a RINGER CIRCUIT has an input that is coupled to receive a data stream DATA, and is responsive to the received data stream to generate at its output a DATA CLOCK signal. More specifically, EDGE DETECT has an input coupled to receive the input data stream and responsively produces SIGNAL A having a defined pulse for each transition in the received data stream. SIGNAL A is coupled to cause RINGER OSCILLATOR to resonate at a pre-determined frequency and thereby generate at its output an oscillatory waveform, SIGNAL B. RINGER OSCILLATOR is constructed to generate an output of a resonance frequency selected to provide a continuous oscillatory waveform as long as the data stream is received at the input of the RINGER CIRCUIT. If receipt of the data stream is interrupted for an interval determinable by RINGER CIRCUIT component values, the RINGER OSCILLATOR returns to its quiescent state and SIGNAL B ceases. TTL RESTORE is coupled to receive SIGNAL B at its input and converts it to provide at its output DATA CLOCK having TTL voltage levels.

Referring now to the remaining drawings, and more particularly, to FIG. 2, there is shown a functional block diagram of an embodiment of the pseudo clock extractor generally designated 200. This pseudo clock extractor 200 includes a synchronizer 220, a edge detect logic 230 and a modulo-counter logic 240.

A REFERENCE signal over paths 212 and 214 couples to a clock input of the synchronizer 220. REFERENCE clocks an incoming channel code encoded data stream AES DATA into the synchronizer 220 via a path 222 coupled to a data input of the synchronizer 220. A signal DATA synchronous to REFERENCE is provided at the output end of the synchronizer 220 and contains the same information as that of AES DATA. DATA is fed into the edge detect logic 230 via paths 224 and 226. In response to each data transition edge in DATA, a defined pulse appears in a signal EDGE on a path 232 coupled to the reset input of the modulo-counter logic 240. The defined pulse serves to reset the modulo-counter logic 240, which is clocked by REFERENCE via path 212 coupled to the clock input of the modulo-counter logic 240. Because the periodicity of REFERENCE is n times (n > 4) or preferably 2ⁿ times (n > 2) that of the desired data clock, the modulo-counter logic 240 is designed so that it outputs a 'low' or a logic 0 level for up to half of the full count and provides a 'high' or a logic 1 for the remaining half of the full count. A resulting signal DATA CLOCK appearing at the output end of the modulo-counter logic 240 on a path 242 is synchronous to DATA ready for further data processing such as serial to parallel conversion in a data processing logic 250.

Referring now to FIGS. 3 A, 3B and 3C, there is provided an embodiment in accordance with the present invention constituting a pseudo clock extractor generally designated 300 for receiving a biphase-mark encoded audio data stream and generating a 6.144 MHz audio data clock synchronized thereto. It includes a SYNCHRONIZER, a EDGE DETECT and a MOD 2² COUNTER LOGIC, similar to the elements referred to in FIG. 2. The clock extractor 300 receives over a path 302 AES DATA, the incoming audio data stream in accordance to AES Recommended Practice AES3- 1992 ANSI S4.40- 1992 and outputs signals DATA and DATA CLOCK for further audio data processing.

A reference clock signal, 24.576 MHz, via a path 304 is provided to all sequential logic elements in the pseudo clock extractor 300. More specifically, 24.576 MHz, being 2² times 6.144 MHz, serving as a triggering clock, is coupled to the clock inputs of flip flops FFA, FFB, FFl and FF2 via paths 306, 308, 310 and 312 respectively. Flip flop FFA in the SYNCHRONIZER receives AES DATA at its D terminal via path 302 and synchronizes AES DATA to the reference clock named 24.576 MHz. DATA appears at FFA's Q terminal coupled to the output of the pseudo clock extractor 300 via paths 314, 318. At the same time, DATA is coupled to flip flop FFB's D terminal via paths 314, 316 and to one input of an exclusive-NOR gate GO via paths 314, 318, and 320. Flip flop FFB's output terminal Q outputs DATA 1, a signal like DATA but one 24.576 MHz clock period delayed and DATA 1 is coupled to a second input of the exclusive-NOR GO over a path 322. The exclusive-NOR GO's output, EDGE, has negative-active defined pulses, each pulse spanning a reference 24.576 MHz period. These pulses indicate occurrences of data transition edges in AES DATA (See FIG. 3B).

MOD 2² COUNTER LOGIC includes a modulo-2² counter and an inverter G3, and receives EDGE over a path 324 and outputs DATA CLOCK to a path 326. The modulo-2² counter includes an AND gate Gl, a NAND gate G2, and flip flops FFl and FF2. EDGE is received into input terminals of Gl and G2 via paths 324, 328 and 324,330, respectively. Signal S 1 appears at the output terminal of Gl and is fed into FFl's D terminal over a path 332. Signal S2 appears at the output terminal of G2 and is fed into FF2's D terminal over a path 334. Flip flop FFl's output Q terminal provides a signal Qi which is fed into G2 via a path 336. Flip flop FF2's output Q terminal provides a signal Q2 which is fed into Gl and G3 via paths 338, 340 and 338, 342, respectively. DATA CLOCK, at a frequency of 6.144 MHz, appears at the output terminal of G3 on path 326, which is synchronous to DATA on path 318.

Operationally, the modulo-2² counter can be better understood by referring to FIG. 3C which illustrates the truth table relationship for the various signals within the counter. When EDGE is high (1) indicating no data transition edge in AES DATA is detected, the counter in response to the reference clock 24.576 MHz, follows the Gray code, namely, 00, 01, 11, 10, 00, 01, etc. Qi indicates the lower bit code level and Q2 indicates the higher bit code level. Furthermore, logic states of Ql and Q2 follow those of S l and S2, respectively, lagging by one 24.576 MHz clock cycle. DATA CLOCK, the desired audio clock at 6.144 MHz depending only on Q2 is generated by being high (1) during two of the Gray code counts and low (0) for the remaining two counts.

When EDGE is low (0), indicating the detection of a data transition edge in AES DATA, the next states Si and S2 will be 0 and 1 respectively, regardless of state conditions of Qi and Q2. It is 01 instead of 00 because the EDGE pulse itself takes up one count. Therefore, including the EDGE pulse count or the first count, DATA CLOCK goes high (1) at the beginning of the third count after reset which approximates the center of a half-bit cell in DATA.

A biphase-mark encoded data stream containing dual-segmented audio information of 64 bits sampled at a rate of 48kHz requires an audio data clock signal of 6.144MHz which implies that a transition length of a half-bit cell spans four 24.576 MHz reference clock periods. Typically, the biphase-mark encoding scheme allows transition lengths of either one half-bit cell (4 reference clock periods) or one full bit cell (8 reference clock periods). However, AES Recommended Practice AES3-1992 ANSI S4.40-1992 stipulates violations of the biphase-mark encoding rules by having a maximum no transition length of three half -bit cells or 1224.576 MHz reference clock periods in a specified data bit area, or preamble, of each audio sample segment for audio information positioning purposes. Therefore, AES DATA conforming to AES Recommended Practice AES3-1992 ANSI S4.40-1992 will have no transition lengths spanning 4 (data logic 1), 8 (data logic 0) and 12 (allowed biphase-mark violations) 24.576 MHz reference clock periods.

When noise and transmission line degradation effects are introduced, AES DATA may be caused to deliver no transition lengths spanning not only 4, 8 and 1224.576 MHz reference clock periods, but also 3, 5, 7, 9, 11 and 13 24.576 MHz reference clock periods. Referring now to FIGS.4A and 4B which illustrate how the pseudo clock extractor 300 compensates a ll and 13 reference clock period no transition length for a supposedly 12- reference clock no transition length (as a part of the audio sample segment preamble) signal. The principles here apply also to the 4 (indicating a data logic 1) and 8 (indicating a data logic 0) reference clock no transition lengths in AES DATA. FIG. 4 A shows a 11- reference clock no transition length in AES DATA and illustrates how DATA CLOCK reduces one of its logic high pulse (1) by one reference clock period in response to a missing reference clock period in AES DATA. Similarly, for a 13-reference clock no transition length in AES DATA, FIG. 4B shows how DATA CLOCK lengthened one of its logic low (0) pulse by one reference clock period in response to an extra reference clock period in AES DATA. The count-0's and count- l's in COUNT always force a low (0) in DATA CLOCK; the count-2's and count-3's in COUNT indicate a high (1) in DATA CLOCK. Furthermore, the COUNT signal occurring one reference clock immediately after the pulse in EDGE is set to be count- 1.

An alternative embodiment to FIG.3A outputs DATA 1 as the pseudo clock extractor's 300's output instead of DATA. Unlike DATA, which may be time delayed up to one reference clock period because of FFA; now, DATA1 allows a time delay of up to two reference clock periods because of both flip flops FFA and FFB. In this embodiment if Gray code representations and the above rules translating count values to DATA CLOCK logic values hold true, then in order that DATA CLOCK rising edges approximate centers of half -bit cells of DATA 1, then a configuration is to arranged the modulo-2² counter so that the row of the truth table in FIG. 3C with EDGE being 0 has Q1(S 1) and Q2(S2) both equaling 0 instead of Q1(S1) = 0 and Q2(S2) = 1. This will delay the DATA CLOCK rising edges by one additional reference clock period to compensate for the additional reference clock period in DATA 1 introduced by the flip flop FFB, so that the rising DATA CLOCK rising edges remain near half-bit cell centers of DATA 1.

FIG. 5 shows another embodiment in accordance to the present invention. FIG. 5 is similar to FIG. 2 in all aspects except SYNCHRONIZER is now replaced by two flip flops FF5A and FF5B. This flip flop configuration protects DATA from signal instability due to potential metastability problems caused by AES DATA and 24.576 MHz undergoing simultaneous transition changes. The metastable problems may arise especially in synchronization of asynchronous signals when data transitions of asynchronous signals occur too close together in time (such as within the setup-time interval preceding a clock pulse) causing long propagation delays if not logic state confusion for the circuit.

Incorporation of this flip flop configuration in FIG. 5 into FIG. 3A results in the DATA, EDGE, COUNT and DATA CLOCK wave form relationships looking the same as those found in FIGS. 4A and 4B, except all of them would be delayed with respect to AES DATA by one additional 24.576 MHz period.

The present invention and its disclosed embodiments are therefore considered in all respects to be illustrative and not restrictive. Embodiments may be implemented in various types of digital logic families or technology including ASIC technology. Logic reduction and transformation techniques may be employed to utilize other arrangements of gates or logic elements which are functionally equivalent to the ones described here. The scope of the invention is indicated by the following claims rather than the foregoing description, and all changes that come within the meaning and range of equivalents thereof are intended to be embraced therein.

Claims

WHAT IS CLAIMED IS:

1. An apparatus responsive to an incoming digital data stream and a reference signal, for generating a data clock signal having a predetermined frequency, the apparatus comprising:

synchronizing means for aligning data transitions of the data stream in timed relation with the reference signal, the reference signal having a periodicity at an integral multiple n of the predetermined frequency, n being an integer greater or equal to 4;

a transition edge detector for producing a transition edge signal including signal pulses responsive to the aligned data transitions, the signal pulses in timed relation with the aligned data transitions and the signal pulses having a signal pulse time length of a cycle period of the reference signal; and

modulo-counter means for generating the data clock signal synchronous to the aligned data stream, The counter means including a modulo-n counter having n being greater than or equal to 4, the counter means being responsive to the transition edge signal and the reference signal, the counter means wherein the signal pulses resetting the counter means to a pre-specified counter output value and the signal pulses in combination with the reference signal determining logic states of the data clock signal.

2. The apparatus of Claim 1 wherein the reference signal having a periodicity at an integral multiple of the predetermined frequency, the integral multiple satisfying the expression, 2ⁿ, and n being an integer greater than or equal to 2 and wherein the modulo- counter means including a modulo-2ⁿ counter, and n being an integer greater than or equal to 2.

3. A pseudo clock extracting apparatus receiving a biphase-mark encoded audio data stream in serial data form and receiving a reference signal, the apparatus providing an audio clock having a pre-determined frequency synchronous to the audio data in serial data form to be recorded on magnetic tape synchronously with a digital video signal, comprising:

digital flip flop means for aligning data transitions of the audio data stream in timed relation with the reference signal, the reference signal having a periodicity at an integral multiple 2ⁿ of the predetermined frequency, n being an integer greater or equal to 2;

modulo-counter means for generating the audio clock signal synchronous to the aligned audio data stream, the counter means including a modulo-2ⁿ counter, n being an integer greater than or equal to 2, the counter means being responsive to the transition edge signal and the reference signal, the counter means wherein the signal pulses resetting the counter means to a pre-specified counter output value and the signal pulses in combination with the reference signal determining logic values of the data clock signal.

4. The pseudo clock extracting apparatus of Claim 3 wherein the reference signal having a periodicity of 24.576 MHz, the reference signal being 4 times the predetermined frequency and wherein the modulo-counter means including a modulo-4 counter.

5. The pseudo clock extracting apparatus of Claim 3 wherein digital flip flop means includes at least two digital D-flip flop circuits in cascading configuration for eliminating metastable conditions, the D-flip flop circuits changing logic states in response to the reference signal.

6. The pseudo clock extracting apparatus of Claim 5 wherein the modulo-4 counter means includes a Gray code counter.

7. The pseudo clock extracting apparatus of Claim 3 wherein the pre-specified counter output value causes rising transition edges of the audio clock signal occurring near half-bit cell centers of the aligned audio data stream.

8. A pseudo clock extracting method for receiving a biphase-mark encoded audio data stream in serial data form and receiving a reference signal and for providing an audio clock having a pre-determined frequency synchronous to the audio data in serial data form to be recorded on magnetic tape synchronously with a digital video signal, comprising the steps of:

aligning data transitions of the audio data stream in timed relation with the reference signal, the reference signal having a periodicity at an integral multiple 2ⁿ of the predetermined frequency, n being an integer greater or equal to 2;

producing a transition edge signal including signal pulses responsive to the aligned data transitions, the signal pulses being synchronous to the aligned data transitions and the signal pulses having a signal pulse time length of a cycle period of the reference signal; and

outputting the audio clock signal synchronous to the aligned audio data stream.