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WO1993006545A1 - Economies de puissance realisees a l'aide d'une boucle d'inactivite du ms-dos - Google Patents

Economies de puissance realisees a l'aide d'une boucle d'inactivite du ms-dos Download PDF

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Publication number
WO1993006545A1
WO1993006545A1 PCT/US1992/004405 US9204405W WO9306545A1 WO 1993006545 A1 WO1993006545 A1 WO 1993006545A1 US 9204405 W US9204405 W US 9204405W WO 9306545 A1 WO9306545 A1 WO 9306545A1
Authority
WO
WIPO (PCT)
Prior art keywords
processor
interrupt
idle
software instructions
data processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US1992/004405
Other languages
English (en)
Inventor
David N. Barrett
Patricia A. Martin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wang Laboratories Inc
Original Assignee
Wang Laboratories Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wang Laboratories Inc filed Critical Wang Laboratories Inc
Priority to AU21455/92A priority Critical patent/AU665354B2/en
Priority to EP92912580A priority patent/EP0603185A1/fr
Priority to JP5505544A priority patent/JPH06510616A/ja
Publication of WO1993006545A1 publication Critical patent/WO1993006545A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode

Definitions

  • Portable computers allow users to take computing power wherever they go. As portable computers become smaller and lighter, their mobility increases. In addition, a portable computer's usefulness increases as processing power and battery life are increased.
  • a typical battery pack will power a notebook size computer for approximately two hours of continuous use.
  • a portable computer's usefulness is limited.
  • a spare battery pack By carrying a spare battery pack, a user can extend the portable computers usefulness another two hours.
  • the additional battery pack reduces the computer's portability.
  • the present invention extends battery life by decreasing the power drain while the portable computer is idle. Whenever the operating system waits for an event, it enters an idle sequence.
  • the present invention takes advantage of the idle sequence.
  • the invention comprises an idle state detector, which detects an idle sequence, and a sleeper, which provides an instruction to halt the processor when the idle state detector detects the idle sequence.
  • the idle sequence generates a unique interrupt.
  • the unique interrupt triggers a specific interrupt handler. By thus detecting the unique interrupt, the specific interrupt handler detects the idle state.
  • the sleeper is implemented as the specific interrupt handler program. Whenever the sleeper program executes, the processor is in the idle state.
  • the preferred sleeper interrupt handler reduces the system clock speed, turns down hardware devices having a power saving mode, and halts the processor.
  • the processor remains halted until an external interrupt occurs. After the processor services the external interrupt, processing continues until the processor returns to the idle sequence.
  • the Applicant's invention includes a limiter, which detects the identified situations and prevents the sleeper from executing.
  • the limiter sets a flag in shared data while an identified system service function is executing and maintains a cleared flag otherwise.
  • both the sleeper and the limiter are interrupt handler programs installed as device drivers.
  • Application program calls to MS-DOS system services trigger execution of the limiter program. Any program call to the MD-DOS idle sequence causes the sleeper program to execute.
  • Fig. 1 shows the logical system overview of a normal computer system operating under Microsoft DOS.
  • Fig. 2 shows the logical system overview of a computer system operating under Microsoft DOS and enhanced by the present invention.
  • Fig. 3 is a flowchart of the sleeper.
  • Fig. 4 is a flowchart of the limiter. Description of the Preferred Embodiment
  • the portable computer is notebook sized.
  • the central processing unit is an Intel model 80386SX microprocessor, normally operating at 16 MHz.
  • the system is operated under Microsoft DOS (MS-DOS).
  • Fig. 1 depicts the normal operation of MS-DOS.
  • the Intel family of processors support up to 256 interrupts, numbered 0 through 255.
  • the boot strap program creates a table 20 indexed by interrupt number for containing each interrupt's vector transfer address.
  • the boot strap program, MS-DOS 30 and application programs 10 load the vectors for defined interrupts 22,24 into the table 20.
  • the processor services interrupts by transferring control to the interrupt's vector address 22,24 which the processor looks up in the table 20.
  • At the vector address is a program called an interrupt handler. Users, however, can cause a new interrupt handler to execute when the processor services a particular interrupt.
  • MS- DOS provides standardized mechanisms. See e.g., R. Duncan, Advanced MS-DOS, pps. 207-257 (Microsoft Press 1986).
  • Application programs 10 communicate with MS-DOS 30 using software interrupts.
  • an application 10 requests a system service, it issues the system service interrupt 15.
  • the processor reads the vector address 22 for the system service interrupt 15 from the vector table 20 and transfers control to the MS-DOS System Service 35.
  • the system service interrupt 15 is interrupt number 33 (21 hex).
  • a code in the AH register identifies the particular system service function 37 requested by the application program 10.
  • the system service function 37 may need to wait for an event. If that is the case, the function 37 enters an idle loop 40.
  • the processor continuously executes the instructions in the idle loop 40 until the awaited event occurs. When the event occurs, control returns to the function 37, which then returns control to the application 10.
  • One instruction in the idle loop 40 is an instruction to issue an idle loop interrupt 45.
  • the idle loop interrupt 45 is interrupt number 40 (28 hex).
  • the processor Upon receiving the idle loop interrupt instruction 45, the processor transfers control to the idle loop interrupt handler 50 based on the vector address 24.
  • the idle loop interrupt handler 50 executes its software instructions and returns control to the idle loop 40.
  • the present invention installs an MS-DOS Device Driver 90 to modify the interrupt interface for the MS-DOS System Service calls 15 and the idle loop interrupt 45.
  • the device driver's initialization routine checks the BIOS version, stores the original vector addresses for the system service interrupt 22 and idle loop interrupt 24 in shared data 80, and modifies the vector addresses 22,24 to point to the limiter 60 and sleeper 70 programs.
  • the present invention realizes a reduced memory requirement because MS- DOS reclaims the memory used for the first-time initialization instructions.
  • the present invention is installed as a character device driver, with the initialization routine coded at the end of the driver.
  • the initialization routine relays its start address to MS-DOS as the first usable memory address. Therefore, MS-DOS is free to reuse the memory occupied by the initialization routine.
  • An application program 10 calls MS-DOS System Services 35 using the system service interrupt 15.
  • the present invention modifies the interrupt interface 20 to include a limiter interrupt handler program 60.
  • the instant invention supplies a sleeper interrupt handler program 70 for the idle loop interrupt 45.
  • the limiter program 60 communicates with the sleeper program 70 via shared data 80.
  • Fig. 3 shows the flowchart of the sleeper program 70, which contains the actual power saving instructions.
  • the sleeper program 70 checks 71 the flag in shared memory 80. If the flag is set then the limiter program 60 is restricting the functioning of the sleeper program 70 and the sleeper program 70 does not implement the power saving features. Instead, the sleeper program exits 78 by transferring control to the original idle loop interrupt handler 50 based on the original vector address. On the other hand, if the flag in shared memory 80 is not set then the limiter program 60 is not restricting the functioning of the sleeper program 70 and the sleeper program 70 implements the power saving features.
  • the system clock frequency is decreased to its minimum value.
  • Barrett et al. in U.S. Patent Serial Number 611 ,990, herein incorporated by reference, discloses the method for reducing the clock frequency.
  • the preferred embodiment requires there be no floppy disk accesses in progress. Reducing the system clock speed while a floppy disk access is in progress results in a Direct Memory Access (DMA) failure.
  • DMA Direct Memory Access
  • the sleeper program 70 checks 72 a flag maintained by the ROM Basic Input/Output System (BIOS) to see if a floppy disk access is in progress and, if not, the sleeper program 70 reduces 73 the clock speed. Otherwise, the sleeper program 70 does not reduce the clock speed. In either case, however, the next step is to enable interrupts 74 so the suspended processor detects external interrupts.
  • the sleeper program 70 next issues a halt instruction 75, which suspends processor activity. The processor stays suspended until the processor detects an external interrupt.
  • BIOS Basic Input/Output
  • Halting the processor results in two power saving benefits.
  • the portable computer uses pseudo-static memory. Pseudo-static memory chips enter a low-power, self- refresh mode while not accessed, and, once accessed, return to full-power mode.
  • pseudo-static memory In the preferred embodiment, the portable computer uses pseudo-static memory. Pseudo-static memory chips enter a low-power, self- refresh mode while not accessed, and, once accessed, return to full-power mode.
  • the pseudo-static memory because there is no bus activity, there are no memory accesses occurring. Because there are no memory accesses occurring, the pseudo-static memory automatically goes into the low-power, self-refresh mode. Therefore, memory decreases its power demands as a direct result of the halt instruction 75.
  • the external interrupt results from a user keystroke, cursor movement provided by a mouse, electromagnetic stylus or light pen device, or another hardware event.
  • the most common hardware event to occur and, thus, wake the processor is the periodic system timer, which triggers an external interrupt every 55 milliseconds. Thus, the computer does not remain in the suspended state indefinitely.
  • a hardware mechanism services 76 the external interrupt.
  • the resulting memory accesses cause the pseudo-static memory to power up.
  • a hardware mechanism automatically increases the system clock frequency during processing of the external interrupt.
  • control returns to the sleeper program 70 at the instruction after the halt instruction.
  • the sleeper program 70 corrects registers 77 reflecting the system speed.
  • the sleeper program 70 then exits 78 by transferring control to the original idle loop interrupt handler 50 based on the original vector address.
  • Fig. 4 shows the flowchart of the limiter program 60.
  • the AH register contains the system service function code identifying the particular system service function 37 called by the application 10. Halting the processor during the idle loop 40 degrades several identified system service functions.
  • the limiter program 60 compares 61 the code in the AH register with the codes corresponding to the identified functions.
  • the identified functions are the Character Output (code 2), Auxiliary Output (code 4), Printer Output (code 5), Direct Console Input/Output (code 6), Output Character String (code 9), and Get Input Status (code 11 ) functions.
  • the limiter program exits by transferring control 62 to the system service interrupt handler 35 based on the original vector address. As a result of the exit, the system service 35 retums directly to the application 10 upon completing the requested function.
  • the limiter program 60 signals the sleeper program 70 by setting
  • the system service 35 retums control to the limiter program 60 upon completion of the requested function. After control returns to the limiter program 60, it pushes 65 the results returned from the system service call onto the system stack.
  • the limiter program 60 clears 66 the flag in shared memory 80 and exits by returning 67 to the application program 10.
  • the applicants implemented the limiter program and sleeper program as device driver interrupt handlers.
  • the applicants recognize the interrupt handlers could also be implemented as MS-DOS Terminate-and-Stay-Resident programs.
  • the operating system code could be modified to include the limiter and sleeper program instructions in-line.
  • the invention could be used on any MS-DOS computer with only minor modifications.
  • another computer's DMA implementation might not be affected by a reduction in clock speed. In that case, there would be no need for the sleeper program to check for floppy disk accesses.
  • Another computer may have additional devices with a software selectable power-saving mode. Software instructions to place these devices into low-power mode could be added to the sleeper program.
  • the invention is not limited to computers using pseudo-static memory. Any computer memory with a low-power mode will benefit from the lack of memory accesses, in any case, any portable computers will benefit from halting the processor while it is idle.

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Abstract

Dans un ordinateur portable, un programme de gestion de périphériques permet au système d'économiser sa puissance lorsque le processeur est inactif. Ledit programme détecte l'inactivité du processeur à l'aide d'une interruption unique produite par la boucle d'inactivité du système d'exploitation. Après avoir détecté l'état d'inactivité, le programme économise la puissance en réduisant la vitesse de l'horloge de système et en arrêtant le processeur. Le système revient à son état de fonctionnement normal lorsque le processeur détecte une interruption externe. Bien qu'une action de l'opérateur engendre une interruption externe, le rythmeur périodique à 55 ms réveille typiquement le processeur. De plus, le programme bloque les mesures d'économie de puissance dans les cas où l'opérateur remarquerait une détérioration de la performance.
PCT/US1992/004405 1991-09-13 1992-05-26 Economies de puissance realisees a l'aide d'une boucle d'inactivite du ms-dos Ceased WO1993006545A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
AU21455/92A AU665354B2 (en) 1991-09-13 1992-05-26 Power savings with MS-DOS idle loop
EP92912580A EP0603185A1 (fr) 1991-09-13 1992-05-26 Système d'économie de puissance pour ordinateurs
JP5505544A JPH06510616A (ja) 1991-09-13 1992-05-26 Ｍｓ−ｄｏｓアイドルループを用いる電力節約

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US75902491A 1991-09-13 1991-09-13
US759,024 1991-09-13

Publications (1)

Publication Number Publication Date
WO1993006545A1 true WO1993006545A1 (fr) 1993-04-01

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1992/004405 Ceased WO1993006545A1 (fr) 1991-09-13 1992-05-26 Economies de puissance realisees a l'aide d'une boucle d'inactivite du ms-dos

Country Status (5)

Country Link
EP (1) EP0603185A1 (fr)
JP (1) JPH06510616A (fr)
AU (1) AU665354B2 (fr)
CA (1) CA2111680A1 (fr)
WO (1) WO1993006545A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0654726A1 (fr) * 1993-11-23 1995-05-24 Advanced Micro Devices, Inc. Systèmes de gestion d'alimentation d'ordinateur
EP0670539A1 (fr) * 1994-02-23 1995-09-06 Sun Microsystems, Inc. Méthode et dispositif de conservation d'énergie dans un système informatique utilisant un pseudomodule de gestion de périphérique dédié à la gestion d'énergie
US7596708B1 (en) 2000-01-18 2009-09-29 Sameer Halepete Adaptive power control

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08241145A (ja) * 1995-03-02 1996-09-17 Nec Corp データ処理装置の低消費電力化方式

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1991000566A1 (fr) * 1989-06-30 1991-01-10 Poqet Computer Corporation Systeme de gestion de l'alimentation d'un ordinateur
EP0426410A2 (fr) * 1989-10-30 1991-05-08 Texas Instruments Incorporated Conservation d'énergie en temps réel pour ordinateurs portables

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1991000566A1 (fr) * 1989-06-30 1991-01-10 Poqet Computer Corporation Systeme de gestion de l'alimentation d'un ordinateur
EP0426410A2 (fr) * 1989-10-30 1991-05-08 Texas Instruments Incorporated Conservation d'énergie en temps réel pour ordinateurs portables

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0654726A1 (fr) * 1993-11-23 1995-05-24 Advanced Micro Devices, Inc. Systèmes de gestion d'alimentation d'ordinateur
EP0670539A1 (fr) * 1994-02-23 1995-09-06 Sun Microsystems, Inc. Méthode et dispositif de conservation d'énergie dans un système informatique utilisant un pseudomodule de gestion de périphérique dédié à la gestion d'énergie
US7596708B1 (en) 2000-01-18 2009-09-29 Sameer Halepete Adaptive power control

Also Published As

Publication number Publication date
EP0603185A1 (fr) 1994-06-29
AU2145592A (en) 1993-04-27
AU665354B2 (en) 1996-01-04
CA2111680A1 (fr) 1993-04-01
JPH06510616A (ja) 1994-11-24

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