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WO1992019046A1 - SYSTEMES DE MEMOIRE MORTE PROGRAMMABLE EFFAÇABLE ELECTRIQUEMENT (EEPROM) POUR CODES 'n SUR m' - Google Patents

SYSTEMES DE MEMOIRE MORTE PROGRAMMABLE EFFAÇABLE ELECTRIQUEMENT (EEPROM) POUR CODES 'n SUR m' Download PDF

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Publication number
WO1992019046A1
WO1992019046A1 PCT/EP1991/000550 EP9100550W WO9219046A1 WO 1992019046 A1 WO1992019046 A1 WO 1992019046A1 EP 9100550 W EP9100550 W EP 9100550W WO 9219046 A1 WO9219046 A1 WO 9219046A1
Authority
WO
WIPO (PCT)
Prior art keywords
codes
eeprom
data
code
bits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP1991/000550
Other languages
English (en)
Inventor
Josef Horstkoetter
Pierre Lewandowski
Brian O'toole
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Germany GmbH
Original Assignee
Motorola GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola GmbH filed Critical Motorola GmbH
Priority to PCT/EP1991/000550 priority Critical patent/WO1992019046A1/fr
Publication of WO1992019046A1 publication Critical patent/WO1992019046A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/47—Error detection, forward error correction or error protection, not provided for in groups H03M13/01 - H03M13/37
    • H03M13/51—Constant weight codes; n-out-of-m codes; Berger codes
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/085—Error detection or correction by redundancy in data representation, e.g. by using checking codes using codes with inherent redundancy, e.g. n-out-of-m codes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells

Definitions

  • the present invention relates to memory systems and in particular to memory systems intended for data critical applications, that is applications in which a corruption of the data during storage and subsequent retrieval can have a potentially catastrophic effect on the overall system, a control system, for example, of which the memory system forms a part.
  • Data storage in control systems may be permanent ROM (control programs, for example), temporary RAM (e.g. intermediate process parameters), or long-term EEPROM (parameters to be carried forward to be retrieved at a later date, such as for example engine diagnostic parameters and performance parameters).
  • a memory cell of an EEPROM typically comprises a field effect memory transistor having a floating gate, which is selectively charged to change the logical state of the transistor.
  • EEPROM is commonly integrated with a microprocessor to form a single device, but the amount of the EEPROM storage is severely limited to 2-4 kbits.
  • Loss of energy stored in a programmed cell may occur through leakage at a very high temperature.
  • the most common form of data corruption is that not enough energy is loaded into the cell during programming the cell to "0".
  • the state of the cell after the operation will be indeterminate with consequent corruption of the data stored. For example it is common practice to hold the processor in a reset mode during power down so that potentially damaging spurious outputs cannot be generated by the power supply.
  • a reset which occurs before all memory cells have been erased or after memory cells have been erased but before the required cells have been programmed will cause data corruption.
  • the present invention provides in one aspect a memory system comprising a suction of electronically erasable programmable read only memory (EEPROM) , means for programming the EEPROM including means for transforming input data into specific codes of a code set, each code of the set having the same number of data bits and the same predetermined number of data bits of one logical state, means for writing the codes representing the input data into the EEPROM, and means for reading the codes stored in EEPROM including means for checking said codes for data corruption by determining whether said codes contain said predetermined number.
  • EEPROM electronically erasable programmable read only memory
  • the invention provides a method of writing data into a memory system comprising a section of electronically erasable programmable read only memory (EEPROM), the method comprising: transforming input data to be recorded into specific codes of a code set, each code of the set having the same number of data bits and the same predetermined number of data bits of one logical state; writing said specific codes into the EEPROM section, and verifying the write operation by reading the codes written into the EEPROM section, and determining in each read code whether the number of data bits of said one logical state is the same as said predetermined number.
  • EEPROM electronically erasable programmable read only memory
  • the coded data written or programmed in the cells of the EEPROM may easily be checked for data corruption by assessing the number of bits having said one logical state. Since the number of cells programmed by the code to a "0" condition is known, then a test which counts the programmed cells of a data byte of the EEPROM and compares the result with this known number, is a 100% effective failure detecting test. This test or check will usually occur immediately after writing, in accordance with usual write check methods, and at any time that data is to be read from the EEPROM. Thus the danger of wrongly programmed cells through power down during a write operation or other abnormal conditions can easily be detected.
  • the present invention is particularly adapted for automotive applications since normally there is only a limited number of data values that need to be stored, e.g. data values related to diagnostic routines.
  • EEPROM may be provided with a separate means for assessing whether the individual memory cells are functioning correctly.
  • the code set termed in general a "n out of m” code, will be a so-called “4 out of 8" code wherein the predetermined number of data bits is half the byte size. It is possible that in certain situations an additional code set may be provided with longer codes, e.g. 2 bytes long, and with a different predetermined number, e.g. 8.
  • FIG. 1 represents a microcomputer system including a memory system in accordance with the present invention.
  • Fig 2 represents a flow chart of a write cycle incorporating the present invention
  • Fig 3 represents a flow chart of a read cycle incorporating the present invention.
  • FIG. 1 a schematic block diagram is shown of the Motorola MC68HC05B6 microcomputer.
  • a central processing unit 2 an input port 4 which accepts 8 analog inputs on lines PD0-7, and 8 bit A/D converter 6, a static ram 8 of 176 bytes, an EPPROM 10 of 256 bytes, and a user ROM 12 of 6kbytes.
  • the user ROM 12 contains EPPROM read/write algorithms in a memory space 14 and a code conversion look up table in memory space 16.
  • An address/data bus 18 and a further code lookup table 19 are provided.
  • the codes of the code set in table 16 are chosen as "n out of m" codes so that they all contain the same number of 1 logical states.
  • a code which is 1 byte long, ie. 8 bits long, a code is chosen so that in each code of the code set a certain number of the bits are 1 and the rest are 0.
  • the largest number of allowable byte values occur when the number of Is is half the number of the available bits.
  • the number of allowable combinations in the situation where 4 of the bits are logical 1 is 70.
  • Such a code is known as "4 out of 8" code. Although the number of allowable byte values has been restricted compared with the 256 possible values this is not a limitation for example in automotive diagnostics, where perhaps considerably less than 70 different codes are used.
  • the analog inputs of PDO-7 to port 4 will be coupled to appropriate sensors.
  • a typical problem for which the present invention is particularly applicable is for detecting whether a sensor is inoperative.
  • the A/D converter 6 has a range of from 0 to 255 and a temperature sensor coupled to an input line may provide typically when it is operating correctly values of between 30 and 200. If the temperature sensor readings fall between 0 and 30 and 200 and 255, this indicates the possibility of an open circuit or a short circuit in the temperature sensor. If an outer limits reading occurs say 20 or 30 times within a pre-determined time span then this indicates that the temperature sensor has in fact failed and CPU 2 will generate an appropriate interrupt to ensure that the failure of the temperature sensor is registered. In accordance with the invention, a failure code is pre-allocated to this condition and is written into EPPROM 10.
  • the microcomputer contains monitoring and maintenance algorithms to ensure that its component parts are working correctly, and in particular that EPPROM 10 is working correctly. Typically this is done before data is written into EPPROM 10 by checking that its output is FF (hexadecimal code) , and at other times by checking the output "number" remains the same. It will be understood the processing of writing data to EPPROM
  • Data generated by CPU 2 to denote failure for example from a temperature sensor is output on address/data bus 18 (22) and the address created by CPU 2 is employed to access look up table 16 to access a code of a code set which has been pre-selected for temperature sensor failure (23). This code is then output on address data bus 18 and is written into EPPROM 10 (24). To check the writing operation, the code is immediately read (25) from EEPROM and the code is validated by counting the number of l's present and comparing the total with the predetermined number. If equal to the predetermined number of 4 no action is necessary (27); otherwise, the write operation is repeated.
  • the counting and comparison actions may be implemented in software routines in the CPU; alternatively, a special purpose hardware "discriminator" may be provided.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Quality & Reliability (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)

Abstract

Afin de surmonter les problèmes d'altération de données, notamment les cas de débranchement, dans les applications du domaine de l'automobile, qui se produisent en cours d'opération d'écriture, la présente invention prévoit une section de mémoire morte programmable effaçable électriquement (EEPROM), un dispositif de programmation de cette mémoire, notamment un dispositif de conversion des données d'entrée en codes spécifiques d'un ensemble de codes, chaque code de l'ensemble ayant le même nombre de bits d'information et le même nombre prédéterminé de bits d'information d'un état logique donné, des moyens d'écriture des codes représentant les données d'entrée dans la mémoire morte, et des moyens de lecture des codes stockés dans la mémoire morte incluant des moyens de dépistage d'altération de données permettant de vérifier lesdits codes en vérifiant s'ils contiennent ce nombre prédéterminé.
PCT/EP1991/000550 1991-04-15 1991-04-15 SYSTEMES DE MEMOIRE MORTE PROGRAMMABLE EFFAÇABLE ELECTRIQUEMENT (EEPROM) POUR CODES 'n SUR m' Ceased WO1992019046A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/EP1991/000550 WO1992019046A1 (fr) 1991-04-15 1991-04-15 SYSTEMES DE MEMOIRE MORTE PROGRAMMABLE EFFAÇABLE ELECTRIQUEMENT (EEPROM) POUR CODES 'n SUR m'

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP1991/000550 WO1992019046A1 (fr) 1991-04-15 1991-04-15 SYSTEMES DE MEMOIRE MORTE PROGRAMMABLE EFFAÇABLE ELECTRIQUEMENT (EEPROM) POUR CODES 'n SUR m'

Publications (1)

Publication Number Publication Date
WO1992019046A1 true WO1992019046A1 (fr) 1992-10-29

Family

ID=8165573

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP1991/000550 Ceased WO1992019046A1 (fr) 1991-04-15 1991-04-15 SYSTEMES DE MEMOIRE MORTE PROGRAMMABLE EFFAÇABLE ELECTRIQUEMENT (EEPROM) POUR CODES 'n SUR m'

Country Status (1)

Country Link
WO (1) WO1992019046A1 (fr)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0694840A3 (fr) * 1994-07-30 1996-05-15 Bosch Gmbh Robert Dispositif de contrÔle pour véhicule à moteur avec mémoire effaçable et programmable électriquement
WO1998033181A1 (fr) * 1997-01-23 1998-07-30 Ford Global Technologies, Inc. Systeme de remise a zero de memoire d'unite de commande de vehicule et procede afferent
EP0733974A3 (fr) * 1995-03-23 1999-07-28 Blaupunkt-Werke GmbH Dispositif de mémoire pour la représenation de signaux analogiques
WO2004114135A1 (fr) * 2003-06-18 2004-12-29 Robert Bosch Gmbh Procede et dispositif de detection d'erreurs pour une antememoire et antememoire correspondante
US7513590B2 (en) * 1998-11-26 2009-04-07 Seiko Epson Corporation Method of normality decision with regard to ink cartridge and printer actualizing the method
US20110160934A1 (en) * 2009-12-25 2011-06-30 Denso Corporation On-vehicle fault detecting device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2041029A1 (fr) * 1970-08-18 1972-03-09
GB2001789A (en) * 1977-07-14 1979-02-07 Indep Broadcasting Authority Transmission and/or recording of digital signals
EP0167271A2 (fr) * 1984-05-31 1986-01-08 Fujitsu Limited Dispositif de mémoire permanente à semi-conducteurs
EP0305987A2 (fr) * 1987-08-31 1989-03-08 Oki Electric Industry Company, Limited Dispositif de mémoire autocorrecteur à semi-conducteur et microcalculateur faisant usage d'un tel dispositif
FR2627004A1 (fr) * 1988-02-08 1989-08-11 Mitsubishi Electric Corp Dispositif a memoire ayant pour fonction de detecter et de corriger une erreur dans l'information stockee

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2041029A1 (fr) * 1970-08-18 1972-03-09
GB2001789A (en) * 1977-07-14 1979-02-07 Indep Broadcasting Authority Transmission and/or recording of digital signals
EP0167271A2 (fr) * 1984-05-31 1986-01-08 Fujitsu Limited Dispositif de mémoire permanente à semi-conducteurs
EP0305987A2 (fr) * 1987-08-31 1989-03-08 Oki Electric Industry Company, Limited Dispositif de mémoire autocorrecteur à semi-conducteur et microcalculateur faisant usage d'un tel dispositif
FR2627004A1 (fr) * 1988-02-08 1989-08-11 Mitsubishi Electric Corp Dispositif a memoire ayant pour fonction de detecter et de corriger une erreur dans l'information stockee

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0694840A3 (fr) * 1994-07-30 1996-05-15 Bosch Gmbh Robert Dispositif de contrÔle pour véhicule à moteur avec mémoire effaçable et programmable électriquement
EP0733974A3 (fr) * 1995-03-23 1999-07-28 Blaupunkt-Werke GmbH Dispositif de mémoire pour la représenation de signaux analogiques
WO1998033181A1 (fr) * 1997-01-23 1998-07-30 Ford Global Technologies, Inc. Systeme de remise a zero de memoire d'unite de commande de vehicule et procede afferent
US5884211A (en) * 1997-01-23 1999-03-16 Ford Global Technologies, Inc. System and method for memory reset of a vehicle controller
US7513590B2 (en) * 1998-11-26 2009-04-07 Seiko Epson Corporation Method of normality decision with regard to ink cartridge and printer actualizing the method
WO2004114135A1 (fr) * 2003-06-18 2004-12-29 Robert Bosch Gmbh Procede et dispositif de detection d'erreurs pour une antememoire et antememoire correspondante
JP2006527871A (ja) * 2003-06-18 2006-12-07 ローベルト ボッシュ ゲゼルシャフト ミット ベシュレンクテル ハフツング キャッシュメモリのためのエラーを認識する方法と装置，およびキャッシュメモリ
US7831889B2 (en) 2003-06-18 2010-11-09 Robert Bosch Gmbh Method and device for error detection for a cache memory and corresponding cache memory
JP4773343B2 (ja) * 2003-06-18 2011-09-14 ローベルト ボッシュ ゲゼルシャフト ミット ベシュレンクテル ハフツング キャッシュメモリのためのエラーを認識する方法と装置，およびキャッシュメモリ
US20110160934A1 (en) * 2009-12-25 2011-06-30 Denso Corporation On-vehicle fault detecting device
US8612089B2 (en) * 2009-12-25 2013-12-17 Denso Corporation On-vehicle fault detecting device

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