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WO1992005667A1 - Appareil de codage et de decodage d'image - Google Patents

Appareil de codage et de decodage d'image Download PDF

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Publication number
WO1992005667A1
WO1992005667A1 PCT/JP1988/000796 JP8800796W WO9205667A1 WO 1992005667 A1 WO1992005667 A1 WO 1992005667A1 JP 8800796 W JP8800796 W JP 8800796W WO 9205667 A1 WO9205667 A1 WO 9205667A1
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WIPO (PCT)
Prior art keywords
vector
frame
output
decoding
block
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PCT/JP1988/000796
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English (en)
Japanese (ja)
Inventor
Tokumichi Murakami
Kohtaro Asai
Koh Kamizawa
Masami Nishida
Eizoh YAMASAKI
Atsushi Itoh
Naoto Kinjoh
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Individual
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Individual
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Priority to US07/340,009 priority Critical patent/US5010401A/en
Priority to PCT/JP1988/000796 priority patent/WO1992005667A1/fr
Anticipated expiration legal-status Critical
Publication of WO1992005667A1 publication Critical patent/WO1992005667A1/fr
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T9/00—Image coding
    • G06T9/008—Vector quantisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
    • H04N19/146—Data rate or code amount at the encoder output
    • H04N19/152—Data rate or code amount at the encoder output by measuring the fullness of the transmission buffer
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
    • H04N19/503—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal prediction
    • H04N19/51—Motion estimation or motion compensation
    • H04N19/577—Motion compensation with bidirectional frame interpolation, i.e. using B-pictures
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
    • H04N19/587—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal sub-sampling or interpolation, e.g. decimation or subsequent interpolation of pictures in a video sequence
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/80—Details of filtering operations specially adapted for video compression, e.g. for pixel interpolation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/90—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
    • H04N19/94—Vector quantisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding

Definitions

  • the present invention relates to an image encoding / decoding device used for a television conference, a television telephone, and the like.
  • Fig. 1 is a block diagram showing the configuration of the encoding device of a conventional interframe block encoding / decoding device, which is a vector adapted to the block encoding method. This is an example using quantization.
  • (1) is an A-to-D converter
  • ( 2) is a switch for dropping frames of an input image signal sequence
  • ( 2) is a digital image signal of a raster type.
  • a raster / block scan conversion circuit that blocks a sequence for every m pixels X n lines (m and ⁇ are positive integers) and forms input block data.
  • ( 4) Is the difference signal between the input data and the block data in the frame memory at the same position on the screen, that is, the difference between the frames.
  • Average value separation normalization circuit (6) performs motion detection for each block using the average value, amplitude component, and threshold value A motion detection circuit for outputting motion information; and ( 7) a vector for vector-quantizing the normalized input vector and converting the normalized input vector into a normalized output vector index.
  • ( 8) is the motion information, The average value, the amplitude component, and the normalized output vector index are each variable-length coded, the coded data is stored for a fixed period of time, and the transmission data buffer is transmitted at a constant speed to the transmission path.
  • (9) is an encoding control circuit for dropping input frames according to the amount of information stored in the transmission data buffer and controlling a motion detection threshold, and ⁇ is the motion information,
  • a vector quantization decoder that decodes and reproduces the inter-frame difference block data from the average value, amplitude component, and normalized output vector index.
  • An adder for reproducing the input block data is a variable delay circuit,
  • FIG. 2 is a block diagram showing a configuration of a decoding unit of a conventional inter-frame block coding / decoding apparatus. As in the coding unit, FIG. This is an example in which the quantization is used.
  • FIG. is a received data buffer that receives coded data supplied from the transmission path, stores it for a fixed time while performing variable-length decoding, and outputs it at a speed corresponding to the decoding operation.
  • a block is a block-no-star scan conversion circuit for converting decoded block data into a raster format, and a DZA converter.
  • the input video signal (201) is an analog signal that is raster-scanned from left to right on the screen and downward from an upward force.
  • the analog signal is converted into a digital signal sequence (202) by an A / D converter (1).
  • the raster / block scan conversion circuit ( 3) a block is formed for every m pixels XII line (m and n are positive integers), and the input block is input.
  • the data S (203) is obtained.
  • the frame memory block data obtained by subtracting the block memory ( ⁇ (204) at the same block position in ⁇ ) from the frame memory ( ⁇ epsilon (205) is entered to the average value separation normalization circuit (5).
  • the average separated normalizing circuit (5), the full record over arm differencing blanking lock data a k-dimensional (k mxn :), then perform the following operation to calculate the average value in the block / ", the amplitude component (206), and the normalized input vector X (207 ).
  • the obtained average value // and the amplitude component ⁇ (206) are input to the motion detection circuit ( 6), and the Based on the comparison with the threshold value (208), motion detection is executed in block units under the following conditions. As a result of the motion detection, the motion information (209) is output from the motion detection circuit ( 6) .
  • the average separation normalization circuit obtains the normalized input vector X (207) obtained in (2) by the vector quantization encoder ( 7) . It is converted to the index i (210) of the normalized output vector yi that minimizes the distortion with X.
  • A) each is converted into encoded data using a variable-length code, etc., and stored for a fixed period of time.
  • the data storage amount (211) in the buffer is calculated and supplied to the coding control circuit ( 9 ), which increases or decreases the data storage amount (211).
  • the on / off signal (232) of the input frame drop switch and the motion detection threshold (208) are controlled on a frame-by-frame basis.
  • Fig. 3 shows an example of the control method.
  • each data input to the transmission data buffer ( 8) ie, motion information (209), average value / "and amplitude component (206), and normalized output vector
  • ⁇ ⁇ + q (q is the error that occurs in vector quantization coding and decoding)
  • variable-length decoded, speed-converted motion information (209), average value ⁇ and amplitude component (206), and normalized output received by the reception data buffer The vector index i (210) is decoded by the vector quantization decoder ⁇ in the same manner as described above, and the inter-frame differential decoding block data _ £ (212 ) Is played.
  • the inter-frame differential decoding block data s (212) is added to the frame memory block data ⁇ [204] output through the variable delay circuit 00, Decoding / reproducing block data S by processing similar to encoding
  • the decoded / reproduced block data (213) is converted into a raster-type data (214) in a block / laster-one-scan conversion circuit 3, and is converted into a D / A by a DZA converter. It is A-converted to obtain a playback output video signal (215).
  • the block-like deterioration due to the error becomes conspicuous and lowers the subjective quality, so that the motion detection threshold value cannot be made too large, and as a result, the motion When the sign is large
  • the amount of encoded information increases, and the number of dropped input frames increases. In other words, there are problems such as a decrease in the number of frames of the moving image to be transmitted, and a decrease in followability to the movement.
  • two transmission buffers and two reception buffers are provided to form a double buffer structure, and the switch W and the cell are provided. While writing the encoded information to one transmission buffer by the function 8 ), writing and reading are performed simultaneously so that the other transmission buffer reads and transmits the information. Similarly, the receiving buffer also switches and the selector ⁇ while one buffer is writing, while the other buffer reads. There is a configuration in which writing and reading are performed at the same time so that they are performed.
  • the delay time from when a certain video frame is written to when the same video frame is decoded and reproduced is approximately one video frame code. It is defined as the time required for two cycles in a simplified transmission cycle. Therefore, when the transmission speed is low or when the amount of generated information is large, it takes time to read the transmission buffer, which may increase the delay time. Frequent dropping increases the time interval between video frames to be coded, reducing the inter-frame correlation and increasing the efficiency of inter-frame coding. There was also a problem that it declined.
  • a spatial filter was used to smooth and reduce the granular noise caused by the vector quantization error.
  • interframe coding and decoding devices as shown in FIGS.
  • (21) is a spatial filter for smoothing and reducing the granular noise generated by the vector quantization error
  • ⁇ is a motion detection circuit ( 6). This is a selector that selects a signal that does not pass through the spatial filter for the block that was determined to be a stationary area in ( ) .
  • Figs. 8 and 9 are block diagrams showing the configuration of the motion detection vector quantization encoder and decoder, respectively.
  • ( 5) is the average value and the vector of the vector.
  • An average value separation normalization circuit that separates the amplitude, ⁇ is a distortion calculation circuit that calculates the distance between two vectors, and a distortion detection circuit that detects the minimum distortion from the output of the distortion calculation circuit 3 ⁇ 4
  • the minimum distortion detection circuit that outputs the signal, ⁇ is the codebook ROM of the output vector, and is the address that gives the address of this codeblock ROM ⁇ .
  • the counter adjusts the index corresponding to the address of the above-mentioned codebook ROM ⁇ so that the output of the minimum distortion detection circuit latches when the minimum distortion is detected. It is a latch. '
  • ⁇ is an amplitude multiplier that performs amplitude reproduction of the normalized output vector
  • ⁇ is an average value addition that adds the average value to the amplitude-reproduced output vector. Vessel.
  • the inter-frame difference reproduction vector decoded by the vector quantization decoder ⁇ according to the inverse coding process is
  • the previous frame vector stored in the frame memory is stored in the previous frame vector.
  • the space filter (the front frame vector passed through 2U is calculated with the force of any one of the frame vectors, and written to the frame memory ⁇ .
  • the motion detection circuit ( 6) the difference input vector between the frames is selected by the selector. Judge whether the block is valid (moving) or invalid, and the result is sent from the motion detection circuit (6) to the selector ⁇ as a valid / invalid identification code.
  • the selector sends the previous frame vector that passed through the spatial filter ⁇ if the inter-frame difference input vector was a valid block. If the block is invalid, select the previous frame vector that does not pass through the spatial filter ⁇ .
  • the conventional device is configured as described above, a spatial filter is always applied to the previous frame signal for obtaining the difference between frames. Therefore, a block containing a strong edge is smoothed by a spatial filter, and even if it is completely stationary, the output of the subtractor becomes zero.
  • the threshold value for motion detection was low, the block was sometimes judged to be valid (movable). As a result, in the playback image, the still edge of the still image does not stop, and the vector quantization is performed again. There was a problem that would be done.
  • FIG. 10 there is another conventional interframe coding / decoding device configured as shown in FIG. 10 and FIG. This figure 10
  • ⁇ denotes a vector of input block data supplied from the raster / block scan conversion circuit using a dynamic core and a block.
  • a dynamic vector quantization encoder for quantizing and ⁇ represents a dynamic output vector supplied from the dynamic vector quantization encoder.
  • a dynamic vector quantization decoder that decodes a trick index and reproduces an output vector where ⁇ is the above-described dynamic vector quantization decoding Is an adaptive spatial filter that performs smoothing processing on the dynamic vector quantized reproduced image signal sequence obtained by the quantizer, and ⁇ is a dynamic filter based on the block identification information.
  • a video signal sequence that has been quantized and that has been subjected to a smoothing process is selected.
  • the variable that converts the dynamic output vector index and the adaptive vector quantized coded output data into an appropriate code word. It is a long encoder.
  • a code string supplied at a speed synchronized to a transmission path through a transmission line is separated from a transmission line into codewords, and the codewords are sequentially inversely converted into coded data.
  • the variable-length decoder, ⁇ is a decoding circuit generator.
  • FIGS. 12 and 13 are block diagrams showing the configurations of the dynamic vector quantization encoder and the decoder, respectively.
  • ⁇ is a distortion calculation circuit that calculates the distance between two vectors in a multidimensional space, i.e., distortion, and ⁇ is the minimum distortion among distortions based on multiple output vectors.
  • a minimum distortion detection circuit that detects and outputs a strobe signal.
  • An output vector set consisting of a plurality of vectors read out from the frame memory;
  • (20 is an address counter that gives the address of the dynamic code book, and ⁇ is the address of the dynamic code book. This is an index latch that takes in the index corresponding to ⁇ ⁇ when the minimum distortion is detected.
  • Figs. 14 and 15 are block diagrams showing the configuration of the adaptive vector quantization encoder and decoder, respectively.
  • ( 5) shows three input vectors.
  • the line cormorant blanking lock identification circuit,) is small blanking lock-out based the Bro 'click identification fin dead-click scan, for example, in a two-dimensional array ( ⁇ X n 2,, n 2 is an integer) every A block to be coded.
  • the block information encoding circuit is the previous value prediction difference PCM encoding circuit
  • (41) is the block information decoding circuit that decodes the block identification index, and is the previous value prediction difference.
  • PCM decoding circuit ⁇ is an average value adding circuit, and is an amplitude multiplying circuit.
  • the AZD conversion Must be processed in real time synchronized with the video clock, from the transmitter to the transmitter buffer memory and from the decoder buffer to the DZA converter.
  • the device scale increases due to parallel processing for speeding up, etc., and the information input to the encoding control circuit is only the transmission buffer memory accumulation amount, It is difficult to control the block identification threshold value that follows. If the frame memory capacity in the encoding loop is only one video field, it is possible to encode all the input data of one video frame. There was a problem that the amount of information generated was large and the amount of transmission delay increased.
  • the conventional device encodes and transmits all pixels in some form based on a predetermined design even when the entire area of the input image is not required or when the number of pixels is not required immediately.
  • the amount of information is large, so dropping is easy to occur, and it is easy to see at what frame rate the sender is transmitting to the receiver of the game.
  • the blocks in the image are quantized one by one, and the last block is quantized. At this point, the encoding is completed. During that time, as many indexes as the number of blocks are output as encoded data, and when decoding, each index is received one by one.
  • the blocks are decoded one by one by vector quantization and decoding. Decoding ends when the index of the last block has been decoded.
  • FIG. 16 shows a conventional contour preserving filter.
  • FIG. 16 is a block diagram showing a configuration example of a conventional contour preserving filter.
  • (45) is a one-line delay element
  • (6) is a one-sample delay element
  • ( ⁇ ) is an adder
  • ( 4) is a subtractor
  • (216) is an eye pixel sample to be smoothed
  • (217) and (218) are left and right on the screen two-dimensional array.
  • ⁇ is an absolute value calculator
  • SO Is the selector (221) 'is the horizontal difference absolute signal
  • (222) is the vertical difference absolute signal
  • (223) is the horizontal filter output with horizontal smoothing
  • (224) is the vertical filter output with vertical smoothing
  • (225) is the horizontal and vertical filter output with horizontal and vertical smoothing
  • 226) is the cell filter output.
  • Cormorant line control of click data output signal Selector Address instruction signal, (227) is Ru output pixel sub emission flop Rudea obtained by smoothing the paying attention pixel sub emission pull-.
  • the conventional contour-preserving filter is configured as described above.
  • the contour-preserving filter depends on the amount of fluctuation of the pixel value due to the peripheral pixels of the target pixel to be smoothed. De-detection is performed, but the effect and the amount of variation of the filter do not always correspond, and there is a problem that erroneous determination occurs and image quality is degraded.
  • Fig. 17 shows an example using an information generation amount control circuit that smoothes the information generation amount.
  • FIG. 17 is a block diagram showing the configuration of the encoding device of the inter-frame adaptive vector quantization encoding device.
  • (1) is an A / D conversion and block division circuit
  • (51) is a block for performing conditional pixel replenishment based on average, variance, and threshold values.
  • a block identification circuit that outputs block identification information, ( 7) outputs a vector index by vector-quantizing the normalized vector j, and outputs a vector index;
  • a vector quantization encoder that performs DPCM on the average value and the variance, and ( 9 ) is used for block identification according to the amount of information stored in the transmission buffer. It is an information generation amount control circuit as an encoding control circuit for controlling the threshold.
  • FIG. 4 is a block diagram showing a configuration of an n-stage tree search vector quantizer coder that introduces an pipeline process, where (207) is an input vector, and (521) is an input vector.
  • Encoder first stage encoded output (302) is encoder second stage encoded output
  • (303) is encoder (D-1) stage encoded output
  • (304) is encoded
  • the output of the n-th stage coded output that is, the output vector index (a latch that takes in the index and outputs it at a certain timing, (210) is an encoder output signal.
  • FIG. 7 is a block diagram showing a configuration example of the encoder a stage.
  • (56) indicates that the input vector (207) is latched at each stage.
  • the register (57) has a tree structure generated so that the output vector corresponding to the node at each stage has the minimum distortion based on the distribution of the input vector.
  • a code table storing a pair of output vectors in the n-th stage of the output vector set, and (305) and (306) are the code tables described in the above.
  • An output vector read from the force vector is a distortion operation circuit that calculates the distortion between the input vector (207) and the output vectors (305) and (306), and ⁇ is A comparator that determines the magnitude of the two distortions output from the distortion calculation circuit, (307) is a signal indicating the determination result in the comparator glue, and (60) is a signal indicating the ( n— 1) Add 0 'or * 1' to the round-coded output (303) This is an index register that outputs the n-th stage encoded output. The configuration of the encoder from the first stage to the n-th stage is almost the same.
  • the differences are the contents of the output vector code table of each stage, the fact that the first stage does not receive the encoded output of the previous stage, and the input stage of the nth stage (final stage). This means that the input vector is not transmitted from the register to the next stage (indicated by the broken line in Fig. 18).
  • FIG. 20 is a block diagram showing a configuration example of a vector quantizer / decoder.
  • (61) denotes an index signal input to the decoder.
  • Register (304) is latched, and (62) is the true output vector (equivalent to the content of the code table at the last stage of the encoder) corresponding to the terminal node of the tree.
  • the stored code table (163) is used for latching the output vector read out from the 6-input power source.
  • the register (212) is an output vector.
  • the output vector code of the encoder is about twice the number of true output vectors.
  • table memory capacity was required.
  • Fig. 53 shows the configuration of a conventional image coding transmission device for transmitting moving images and still images.
  • (826) is moving.
  • the video camera (827) encodes the video signal output from the video camera (826), (828) encodes the video signal (827), and encodes the video encoded data (829).
  • a video encoding / decoding device (hereinafter abbreviated as codec) for decoding to a video signal (832) (829) is video encoded data, and (830) is a video codec (828) or still image code.
  • codec video encoding / decoding device for decoding to a video signal
  • (830) is a video codec (828) or still image code.
  • (831) is the multiplexed data that is transmitted by the transmission control station (830), (832) is the video signal decoded by the video codec (828), and (833) is the video signal image.
  • (834) is a still image camera, (835) is a still image signal, (836) is a still image codec that encodes and decodes still images, and (837) is a still image codec.
  • Still picture encoded data (838) is a monitor for displaying a still picture signal, and (839) is a monitor for displaying the still picture signal (838).
  • FIG. 54 is a block diagram showing an example of a moving image encoding device of a conventional image encoding and transmitting apparatus, where (801) is an input signal obtained by digitizing the signals from cameras and (802). ) Is a blocking circuit that blocks and outputs a signal scanned in the raster direction, and (804) is an input that is a blocked coding unit.
  • Signal sequence (805) is the dynamic vector quantizer, (806) is the DVQ index, (807) is the DVQ output vector, and (825) is the noise accumulation.
  • (809) is the DVQ output vector passed through the filter
  • (810) is the subtractor
  • (811) is the difference vector between frames
  • (812) Is an adaptive vector quantizer
  • (813) is an adaptive vector quantizer
  • AVQ (814) is the AVQ output vector
  • (815) is the adder
  • (816) is the local decoding vector
  • (817) is the number of pixels of the moving image.
  • the domain, (818) is the delayed frame vector vector.
  • FIG. 55 is a block diagram showing an example of decoding in a conventional image encoding and transmitting apparatus, where (806) is a DVQ index, and (820) is a dynamic vector.
  • (825) is a digital relay filter
  • (809) is a DVQ output vector passed through a filter
  • (813) is AVQ encoded information
  • (819) ) Is the adaptive vector quantizer decoding city
  • (814) is the difference vector between frames decoded by the local city
  • (815) is an adder
  • (816) is the local city decoding.
  • Vector, (817) is the field memory for the number of pixels of the moving image
  • (823) is the deblocker that scan-converts the blocked signal sequence in one raster direction.
  • the locking circuit, (824), is a video output signal sequence. ⁇
  • the video is converted into an electric signal by a moving image camera (826) to obtain a moving image signal (827).
  • the video signal (827) is compressed and encoded by the video codec (Deck) (828), and the video encoded data is
  • the still image codec (836) does not normally perform the encoding operation, and only outputs the still image signal (835) from the still image camera (834) when it is necessary to transmit the still surface. Is encoded and sent to the transmission control station (830) as still image encoded data (837).
  • still image encoded data In general, in still image coding, the number of samples is larger than in moving images, and coding using the correlation between consecutive frames can be performed as in moving images. For this reason, one-screen still image encoded data is much more than one-screen video encoded data. Therefore, when the still image transmission is started, the transmission control unit temporarily suspends the transmission and reception of the moving image coded data in order to end the still image transmission in the shortest time.
  • the input signal sequence (801) input from the camera and digitized is a blocking circuit.
  • 802) is the input vector (804) which is blocked into m x n pixels in the quantization unit.
  • the input vector (804) is obtained by the dynamic vector quantizer (805), which is the previous frame read out from the file memory 817). It is compared with the dynamic code table consisting of the signal (81S), etc., and the frame frame before the position displaced around the position in the screen of the input vector (804). Quantize to vectors As a result, a DVQ index (806) and a DVQ output vector (807) corresponding to the displacement are obtained.
  • the DVQ output vector (807) is smoothed by a digital filter (825) to prevent accumulation of quantization noise.
  • the DVQ output vector (809) smoothed by the filter enters the subtractor (810) and is subtracted from the input vector (804) to obtain the difference between the frames.
  • the inter-frame difference vector (811) is subjected to adaptive processing such as motion detection and average separation normalization by an adaptive vector quantizer (812), and the AVQ output vector is calculated. (814) and AVQ encoded information (813) such as indexes are output.
  • the AVQ output vector is added by a DVQ output vector (809) smoothed by a filter and an adder (815) to become a local decoding vector (816). Written to the corresponding location in the field memory (817).
  • the contents of the field memory (817) are quoted in DVQ when the next frame is encoded.
  • the AVQ encoded information (813) and the DVQ index (806) are variable-length coded and transmitted as transmission data by the transmission control station, but the amount of transmitted information is kept constant. On the other hand, if the amount of generated information is large, the frame to be encoded is thinned out and the drop-out control is performed.
  • the DVQ index (806) and the AVQ encoded information (813) are decoded into a video signal sequence (824).
  • the DVQ index (806) enters the DVQ decoding city (820) and the digital filter (825).
  • the previous frame vector at the position displaced according to the DVQ index (806) from the corresponding position of the previous frame decoded image in the field memory (817) is The data is read out and equalized by the digital filter (825).
  • the AVQ coded information (813) is decoded into an inter-frame difference local decoding vector (814) by the AVQ decoding device (819), and is smoothed by the filter by the adder (815).
  • the result is added to the decoded previous frame vector (809) to obtain the local decoding vector (816).
  • the local decryption vector (816) is written to the corresponding location in the feed memory (817) for decryption of the next frame.
  • the above is the operation of the video codec.
  • the number of pixels is reduced in order to encode a moving image within a limited information amount.
  • high resolution is required for the encoding of still images and documents, and it is difficult to encode moving images and still images with the same number of pixels. Therefore, when transmitting moving images and still images, it is necessary to prepare a still image codec that is independent of the moving image codec.
  • the present invention relates to a differential amplitude suppression circuit that suppresses the amplitude value of inter-frame difference decoding block data in block units in a non-linear manner according to a motion detection threshold value. Is inserted before the interframe adder of the decoding unit in the encoding unit, and the non-linear characteristic is moved by the encoding control circuit and the transmission data buffer is output together with the threshold value to be detected. In this method, control is performed based on the amount of stored data, and means for transmitting a motion detection threshold value is used.
  • the differential amplitude suppression circuit when the differential amplitude suppression circuit has a large amount of motion, the subjective quality is not significantly reduced and the increase in the amount of encoded information is suppressed. Encoding and decoding can be performed, and the ability to follow the movement of the reproduced moving image is improved.
  • a buffer for each video frame is placed between the pre-processing capital and the encoding capital in the encoder, and the time of the video frame is set using the same noise. It has a control circuit that performs integration, and leads to the video frame-based notches in accordance with the amount of buffer storage for smoothing the amount of transmission information. It has a circuit that controls the video signal, and a buffer for each video frame is placed between the decoding city and the video output city in the decoder.
  • the image frame to be coded is first written into the frame memory while time-integrating, and then written. Since the amount of information generated is encoded and transmitted in small increments after a short time, the delay time can be reduced, and no aliasing occurs even if the pieces are broken. In addition, since it is possible to encode an image frame in which the inter-frame correlation is maintained, there is an effect that a high-quality image can be efficiently encoded and transmitted.
  • Vector quantizers are connected in multiple stages, and the subsequent vector quantizer quantizes the residual of the preceding vector quantizer, and the encoding and decoding processes are performed in order from the previous stage. What we tried to do
  • contour preserving filter as a spatial filter is used to determine the filter adaptive switching of the smoothed pixel of interest, and to determine the pixel of interest from up, down, left, right, or diagonal directions.
  • the signal of the difference between the sum of the values of the two pixels sandwiching it and the value twice as large as the value of the target pixel is used.
  • the information generation amount control circuit as an encoding control circuit has a plurality of threshold value-to-generation information amount characteristics according to the amount of movement.
  • a threshold control table having an encoding control table and its inverse characteristic, and referring to the encoding control table as an input of a threshold value and an amount of generated information. The amount of movement is detected, the amount of movement and the amount of generated information are inputted, and a new threshold value is determined with reference to the threshold value table. If the amount of recording is small for a certain period of time, the threshold value is kept high. The threshold value is controlled so that the amount of information generated is smoothed. In addition, the effect of improving the ability to follow the start of movement of the image can be obtained.
  • the vector quantizer consists of a tree search vector quantizer, and the tree search vector quantizer separates the average from the input vector.
  • a stage where a circuit is provided the mean value is separated by this mean value normalization circuit, and the mean is separated as a new input vector, and a tree structure output vector set for the encoder is generated.
  • the left and right half output vectors are arranged.
  • the image encoding and transmitting apparatus uses a common encoding unit for encoding a moving image and a still image when transmitting a moving image and a still image, and sets the resolution of the still image horizontally to the moving image. Double and double in the vertical direction, and the number of fields in the inter-frame encoding / decoding loop is equal to the number of pixels of the moving image. Only the outside of the decoding loop has the frame memory of the number of pixels of the still image, so the cost is low, and both the video and still image quality
  • the purpose of the present invention is to obtain a high-performance image coding transmission device.
  • FIG. 1 is a block diagram showing the configuration of an encoding unit of a conventional interframe encoding / decoding device
  • Fig. 2 is a block diagram of the decoding unit
  • Fig. 3 is a conventional frame.
  • FIGS. 4 and 5 show an example of an encoding control method of the encoding method of the inter-frame encoding / decoding device
  • FIG. 4 and FIG. 5 show the transmission and reception buffers doubled.
  • FIGS. 6 and 7 show the use of a spatial filter.
  • FIG. 8 A coding unit showing the configuration of a conventional interframe coding / decoding device and a block diagram showing the configuration of a decoding device
  • Fig. 8 Fig. 9 and Fig. 9 are block diagrams of vector quantization encoder and decoder
  • Fig. 10 and Fig. 11 are other conventional frames.
  • Block diagrams of the encoder and decoder in the inter-system encoding / decoding device, and Figs. 12 and 13 show the dynamic vector quantization encoder and decoding.
  • Figures 14 and 15 are block diagrams showing the configuration of the adaptive vector quantization encoder and decoder
  • Fig. 16 is the information generation amount control circuit.
  • Fig. 17 is a block diagram showing the configuration of a conventional encoding city using, Fig.
  • FIG. 17 is a block diagram showing the configuration of a conventional contour preserving filter
  • Fig. 18 is a tree search vector
  • FIG. 19 is a block diagram showing the configuration of the quantization encoder
  • FIG. 19 is a block diagram showing an example of the configuration of the 11 stages.
  • FIG. 20 is a block diagram showing a configuration example of a decoder
  • FIG. 21 is a block diagram showing a configuration of a coding apparatus of an interframe coding / decoding apparatus according to an embodiment of the present invention
  • FIG. 22 is a block diagram showing a configuration of a decoding unit of the interframe coding / decoding apparatus according to one embodiment of the present invention
  • FIG. 23 is an embodiment of the present invention.
  • FIG. 24 is an explanatory diagram showing an example of input / output characteristics of a differential amplitude suppression circuit of an interframe encoding / decoding device according to an example.
  • FIG. FIG. 25 is a block diagram showing the configuration of the time integration circuit in FIG. 24, and FIG.
  • FIG. 26 is a block diagram of a decoding device showing another embodiment of the present invention.
  • FIG. 27 is a block diagram of an encoding device showing another embodiment of the present invention
  • FIG. 28 is a block diagram of a decoding device showing another embodiment of the present invention.
  • Click view FIG. 29 is adapted space off I filter theory
  • FIG. 30 is a block diagram of an encoding device showing another embodiment of the present invention
  • FIG. 31 is an encoding diagram showing another embodiment of the present invention.
  • FIG. 32 is a block diagram of a decoding device showing another embodiment of the present invention
  • FIG. 33 is an explanation showing an example of coding by the coding device shown in FIG. 32.
  • FIGS. 34 and 35 are block diagrams of an encoding unit and a decoding unit showing another embodiment of the present invention.
  • FIGS. 36 and 37 are operation diagrams of a pixel number reduction circuit.
  • FIG. 38 is a block diagram of an encoding system showing another embodiment of the present invention
  • FIG. 39 is a block diagram of its decoding unit
  • FIG. 40 is its constituent elements.
  • Fig. 41 and Fig. 42 are explanatory diagrams of the adaptive space filter
  • Fig. 38 and Fig. 39 are block diagrams of the encoding city and another example of the configuration of Fig. 39.
  • the block diagram of Fig. 43 is
  • FIG. 44 is a block diagram of a contour preserving filter as a spatial filter used in the invention of FIG. 44, FIG.
  • FIG. 44 is an image signal arrangement diagram for explaining its operation
  • FIG. FIG. 46 is a block diagram of an encoding control circuit showing one embodiment of the present invention.
  • FIG. 46 is an explanatory diagram showing an example of a method of creating an encoding control table.
  • FIG. 47 is a threshold value control.
  • FIG. 48 is an explanatory diagram showing an example of table creation
  • FIG. 48 is a block diagram of the encoding of a tree search vector quantizer according to an embodiment of the present invention
  • FIG. 49 is the code thereof.
  • FIG. 50 is a block diagram showing the configuration of the first stage of the encoder
  • FIGS. 50 and 51 are explanatory diagrams showing the structure of the output vector set of the encoder.
  • FIG. 52 shows the structure of the present invention.
  • FIG. 53 shows the conventional image and video transmission.
  • FIG. 54 is a block diagram of the encoding city
  • FIG. 55 is a block diagram of the decoding city
  • FIG. FIG. 57 is a block diagram of an image encoding and transmitting apparatus of an image encoding and transmitting apparatus according to an embodiment of the present invention
  • FIG. 57 is a block diagram of the same decoding apparatus
  • FIG. 59 is an explanatory diagram showing the arrangement of still image encoded pixels
  • FIG. 59 is an explanatory diagram of the operation of an adaptive filter used in the image encoding and transmitting apparatus according to one embodiment of the present invention.
  • FIGS. 21 and 22 (71) is a block coding circuit for coding the inter-frame difference block data in block units, and (72) is a block coding circuit in block units.
  • This is a differential amplitude suppression circuit that suppresses, and is otherwise the same as the conventional one shown in FIGS. 1 and 2.
  • the inter-frame difference block data ej (205) obtained in the same manner as the conventional one is detected by the motion detection circuit (6) for each block, and the motion information is obtained. (209) is output.
  • the motion detection can be executed together with the motion detection threshold value (208), for example, by the following calculation. k
  • the information (209) and the motion detection threshold value T (9 (208) ) are supplied to the transmission data buffer ( 8), which is a conventional transmission data buffer ( 8) .
  • the motion information (209) and the block coded data (216) are converted into coded data such as a variable length code and stored for a certain period of time.
  • the data storage amount in the buffer (211) is calculated and supplied to the encoding control circuit ( 9) , and the data used for motion detection is also transmitted.
  • can detect Ki have values (208) that be transmitted to the encoding full record over unitless.
  • the off signal (232) and the motion detection threshold value (208) are controlled on a frame-by-frame basis.
  • the detected threshold value (208) is supplied to the differential suppression circuit 3) described later.
  • the motion information (209) and the block-encoded data are decoded in a block decoding circuit (72), and the inter-frame differential decoding block data ⁇ (212) is obtained. Played.
  • the inter-frame difference decoding block data e (212) is moved by the difference amplitude suppression circuit ( 73 ), and the amplitude value is nonlinearly suppressed in block units according to the detected threshold value. It is done.
  • Fig. 23 shows an example of nonlinear suppression characteristics.
  • the inter-frame differential decoding block data ⁇ * (217) suppressed by the differential amplitude suppressing circuit ( 73 ) is delayed for a predetermined time through a variable delay circuit 0 in an adder ⁇ .
  • the block data ⁇ (204) in the frame memory thus added is added to the decoded block data S (213), and the decoded block data S (213) is restored. Updates the block data at the block position.
  • the motion information "(209) and the block coded data (216) received by the reception data buffer and subjected to variable length decoding and speed conversion are transmitted to the encoding unit.
  • the data is decoded in the block decoding circuit (72), and the inter-frame differential decoding block data £ (212) is reproduced.
  • the differential amplitude suppression circuit (73) similar to the encoder shown in FIG. 23, the block data (212) is obtained by the motion detection threshold (208) received through the transmission line. And the suppressed inter-frame differential decoding block data (217) is obtained. And the block data f (204) in the frame memory output through the variable delay circuit.
  • the decoded and reproduced block data C (213) is restored by the same processing as in the encoding method, and the decoded / reproduced block data S (213) is used as a block-noraser-scan conversion circuit.
  • An A-converter ⁇ and the same processing as the conventional one is performed to obtain a playback output video signal (215). It is.
  • the block coding circuit and the block decoding circuit in the above-described embodiment use a vector quantization encoder and a vector quantization decoding like the conventional ones. It may be configured using a container
  • the motion detection circuit in the above embodiment detects the motion by comparing the sum of the absolute values of the amplitudes in the inter-frame difference block with the motion detection threshold.
  • the means for performing the comparison is used, the means for comparing the average value and the amplitude component in the block with the threshold value for detecting the motion can be used in the same manner as in the conventional example. Similar effects can be obtained.
  • FIG. 24 is a block diagram of an encoding system showing another embodiment of the present invention, wherein (202) is a digital video signal, is a time integration circuit, and (75) is a front frame.
  • the memory (220) sequentially reads the contents of the buffer on the write side of the pre-frame memory (which has a double-knob structure) to read the digital data.
  • the video signal (202) is a signal that matches the pixel position on the video frame, (221) is the time-integrated input signal, ( 76 ) is the switch, and (77) is the prefix.
  • Frame memory # 1, 8) is the front frame memory # 2
  • (79) is the switch
  • (8 (H or (222) is the control signal of the pre-frame memory
  • (223) is the locally decoded signal
  • (224) is the locally decoded value subjected to the frame delay.
  • (225) is a mark Of information
  • 1) the transmission Roh Tsu off ⁇ # 1, 2) the transmission Roh Tsu off # 2 and ⁇ are selectors
  • (226) is a signal indicating the accumulated amount of transmission buffer in a double buffer structure, and the status of each transmission buffer. This is a transmission signal.
  • FIG. 25 is a block diagram showing a configuration example of the time integration circuit in FIG.
  • FIG. 26 is a block diagram showing a configuration example of a decoding device.
  • (227) is a transmission signal
  • (229) is a reception coded signal
  • (230) is a decoding signal subjected to a frame delay.
  • (86) is post-frame memory
  • (87) is switch
  • (88) is post-frame memory ') # 1
  • (90) is the post-frame memory # 3,) is the selector.
  • the input video signal (201) is digitized by the A / D converter (1).
  • the time integration circuit (74) is a signal (220) which sequentially reads the contents of the buffer on the write side of the pre-frame memory ⁇ having a double buffer structure. By using, the signal obtained by performing time integration of the input signal (202) for a plurality of frames is written to the buffer on the pre-writing side. In the time integration, a difference between the input signal (202) and the signal (220), that is, a frame-to-frame difference (228) is obtained, a value is converted by a weighting circuit ⁇ , and the input signal (202) is further converted.
  • the time integration is represented by the following calculation.
  • the pre-frame memory (75) is used to record one frame of video frame data while time-integrating the other frame.
  • the switch (TO) By switching by the switch (TO), the encoded video frame signal and the frame memory read signal (220) necessary for time integration on the writing side are converted.
  • Output Reading of the encoded video frame signal, which is the output of the read-out side of the pre-frame memory (), is performed intermittently by the control signal (222). The purpose of this is to smooth out the amount of information generated in small increments and will be explained in detail later.When a single video frame is read out, the double buffer is switched off.
  • the content of the buffer on which the time integration has been performed up to that point is read out as an encoded video frame, that is, the time integration is based on the double buffer.
  • the number of video frames that are continuously time-integrated will be interrupted by the acquisition of the encoded video frame. It depends on how much time it takes for the video frame being transmitted. That corresponds to your only that information generated amount to nothing. Information generation amount and has come large This means that the motion is large in interframe coding.
  • the number of video frames that are time-integrated continuously increases when the scene moves rapidly. In other words, images that are blurred in the time direction are captured.
  • time integration is interrupted by double buffer switching, so when a new time integration begins, the output of the weighting circuit ( 84) must be It is necessary to reset the contents of the frame memory to zero.
  • the parameter k described above is set to 0 immediately after the double buffer is switched, and thereafter, the value is increased exponentially according to the input video frame sequence. Going forward is also effective.
  • the encoded video frame that starts encoding by double buffer switching is a video frame that has undergone time integration, and is stored in the frame memory. Since the coding processing speed can be selected arbitrarily, there is a margin for multiplexing the circuit by setting the processing time corresponding to the low transmission speed. Occurs, and the device scale can be reduced.
  • the inter-frame coding circuit uses a frame memory for a signal [223] which has already been coded and locally decoded by using a frame memory ⁇ .
  • the inter-frame prediction signal (224) formed by giving a frame delay, the above-mentioned encoded video frame signal is inter-frame encoded.
  • the encoded information (225) becomes a transmission signal (227) via the transmission buffer (8) and is transmitted to the transmission path.
  • the transmission buffer ( 8) sends a signal (226) indicating the accumulated amount / status to the controller of the pre-frame memory, and indirectly encodes the signal.
  • the amount of information generation is smoothed by stopping and restarting.
  • the transmission buffer ( 8) has a double buffer structure. Now, assume that a video frame with a prefix frame memory # 1 (is being read. The read data is encoded and transmitted. When the accumulated amount of the buffer (81) exceeds a preset threshold value Th1, the pre-frame memory is written to the buffer # 1 (si). Controller Yanagi stops reading from the pre-frame memory # 1 (77), and reads the amount of data stored in transmit buffer # 2 (82). Then, when it becomes 0, the double buffer of the transmission buffer is switched.
  • the encryption information (225) is written in the transmission buffer # 2 ( 82 ).
  • the encoded information stored in the transmission buffer # 1 (81) is transmitted to the transmission path.
  • storing the transmitting buffer # 2 (82) during reading It may fall below the capacity Th2.
  • the transmission buffer ( 8) is switched to the double notch. By the switching, the reading of the pre-frame memory # 1 (force reading is restarted.
  • the transmission time is reduced without delay, the transmission buffer capacity is reduced, and the threshold value Th1 is set on one side of the transmission buffer. Since the amount of information to be embedded is specified, it is determined from the delay time and the transmission speed.
  • the threshold value Th2 is a case where the amount of information is insufficient for the transmission framing, so the transmission Determined by speed and format of transmit framing.
  • the frame delay is applied to the already decoded signal by the frame memo for the reception buffer (the reception coded signal (229) via L4).
  • the inter-frame prediction signal (230) thus formed, decoding is performed in the inter-frame decoding circuit ⁇ , and the decoded signal (231) is post-frame-measured.
  • the post-frame memo has a “to” pull-buffer structure, and one buffer is read out according to the frame synchronization of the image output system.
  • the other buffer is writing the decoded signal, and the other buffer is stopped.
  • the writing of the received and decoded video frame signal is completely asynchronous with the reading according to the frame synchronization of the image output system. Both that Do necessary because the interruption is not allowed.
  • Ko ⁇ Fu les over arm MEMO The read signal from (186) becomes a decoded video signal (215) by the D / A converter ( ⁇ ).
  • the time from when a certain video frame is read out from the front frame memory (75) until the same video frame is decoded and played back It is specified by the time required for one cycle of the coded transmission cycle of one video frame. Therefore, the lower the transmission speed, the greater the effect of reducing the delay time as compared with the conventional device.
  • FIG. 27 is a block diagram showing another embodiment of the present invention.
  • (7) is a vector quantization encoder
  • W is a vector quantization decoder
  • the control parameter controls the amount of information in a transmission data buffer.
  • the adaptive space filter which is used as a filter, is a selector that is switched by a valid / invalid block identification code from the motion detection circuit (6).
  • FIG. 28 is a diagram showing a pixel arrangement for explaining an adaptive space filter, which is a decoding device.
  • the vector data (203) obtained by the raster-block scan conversion circuit (3) is processed by the subtractor ( 4) at the same position in the frame memory $.
  • the previous frame vector (204) with the adaptive space filter ⁇ is subtracted from the previous frame vector (224) based on the lock, and the frame is subtracted.
  • An inter-frame difference input vector (205) is obtained.
  • the adaptive space filter ⁇ applies its smoothing characteristic to the amount of data in the transmission data buffer ( 8) as in the case of the threshold control of the motion detection circuit (6).
  • the ° lame evening (226) It is controlled for each system, and the parameter (226) is sent to the receiving side as a control signal.
  • the inter-frame difference input vector (205) is encoded by the vector quantization encoder (7), and the motion detection circuit ( 6) transmits the transmission data buffer (205). 8) Motion detection is performed with a threshold value that changes with a parameter (226) corresponding to the amount of data in (2). As a result of the motion detection, the encoded data (225) obtained by encoding the inter-frame difference input vector (205) determined to be valid is transmitted data buffer ( 8).
  • the received data (227) from the transmission line is stored in the received data notch CM), Read out according to the decoding speed.
  • the adaptive space filter changes the smoothing characteristic for each frame by the transmitted filter control signal (228).
  • the selector is controlled for each block by the valid / invalid identification code (229) received in the same manner.
  • the decoded signal (213) written to the frame memory ⁇ is converted into a raster form by a block-no-raster one-scan conversion circuit ⁇ and then converted by the DZ ⁇ converter ⁇ . It is output as an analog image signal (215).
  • Control parameter (0 to 1) ⁇ takes the maximum value of 1 when the amount of transmission buffer data is small, and takes a small value when the amount of notch data is large. 0
  • the threshold value for motion detection decreases, and the smoothing of the adaptive space filter becomes weaker.
  • the previous frame vector (204) passed through the filter ⁇ is the previous frame vector (224) It will be very close. Therefore, for the still area of the input image, the difference input vector between frames (205 becomes extremely small, and it is determined that the block is invalid by valid / invalid block identification.
  • the motion detection threshold value is low, so it is determined to be valid, and coding is performed.
  • Adaptive spatial filter smoothing of 2 is weak, so coding Amount of vector generated by quantization block
  • the effect of removing quantization noise is small, when the motion is small, the power of the frame difference signal is small. There is no problem because generation of quantization noise is small.
  • the adaptive spatial filter (the smoothing of 2 becomes stronger and the front frame vector frame becomes frame Since the output of the memory is smoothed, the amount of the strong edge is smoothed in the static region, so the amount of the edge difference is input to the interframe difference input signal. However, since the threshold for motion detection has risen, the edges in the still area are not valid and are not coded. Although it is effective and coded, the vector quantization noise is removed because the adaptive space filter (21) has a stronger smoothing characteristic.
  • a raster-type input image signal (201) is converted to a digital signal by a digital D converter (1) and then blocked by a raster block scan conversion circuit (3).
  • the input vector (203) is converted into a king and vector. Form.
  • the dynamic vector quantization encoder ⁇ compares the input vector (203) with the previous frame vector (224) and outputs the dynamic output. Outputs the vector index (230).
  • the dynamic vector quantization decoder ⁇ outputs a dynamic vector quantization signal (231).
  • the signal (232) obtained by multiplying the dynamic vector quantized signal (231) by the adaptive spatial filter according to the present embodiment is the input vector (203).
  • the residual signal is then subjected to vector quantization of the residual signal, which is effective after motion detection, vector quantization encoding and decoding.
  • the dynamic vector quantization signal (232) passing through the spatial filter selected by the selector ⁇ is added.
  • the zero vector from the vector quantization decoder aa and the dynamic vector quantization signal (231) selected by the selector ⁇ are obtained.
  • the decoded signal (223) thus decoded is written to the frame memo "( ⁇ ).
  • strong smoothing is performed, such as by performing strong smoothing.
  • the input signal and the dynamic vector quantization In the following, the power of the residual signal from the signal is often small, so that even if it is coded, the quantization noise is small and it depends on the value at which the motion is detected.
  • the spatial filter be weakly smoothed because it may be invalidated. If the output vector is a frame memory output at a position where a relatively large displacement is applied to the input block, a spatial filter with enhanced smoothing is used. By encoding the residual with the DVQ signal in which the quantization noise has been smoothed as a characteristic, accumulation of the quantization noise can be prevented.
  • FIG. 31 is a block diagram of an encoding unit showing another embodiment of the present invention.
  • ⁇ 2 writes input image data at a speed synchronized with an input video clock, and At least one image data
  • a rate conversion input memory for storing frames, and reading out the input image data at an encoding rate synchronized with a clock multiplied by the clock of the transmission line clock, (93) Converts the output vector index and the adaptive vector quantized coded data into appropriate code words for each input block, and converts the code word into input block units.
  • the number of effective blocks generated by the adaptive vector quantization encoder is output by one video frame, while the format is sequentially output in the format delimited by Variable-length coder with a function to print data.
  • the operation is performed using the number of effective blocks and the block identification threshold value that occurred during the previous and previous encoding.
  • Estimate the amount determine a new threshold value from the movement amount, and write and read the speed conversion input memory based on the accumulated amount of the transmission data buffer.
  • FIG. 32 is a block diagram of a decoding city, in which a code string of received data is in a format which is divided into input ports in a format).
  • a variable length decoder that decodes into a mix output vector index and adaptive vector quantized coded data.
  • (96) decodes and reproduces image data at the decoding speed.
  • a speed conversion output memory that writes, stores at least one frame of the image data, and reads out the decoded reproduction image data at a speed synchronized with the output video clock. . Next, the operation will be described.
  • the analog signal in the raster format is converted into a digital signal sequence by an AD converter, and then the speed conversion input memory (921 is a specified field or Captures the digital signal sequence of the frame while thinning it out, and stores the digital signal sequence, that is, the input image data, into the input video port.
  • the speed conversion input memory 921 is a specified field or Captures the digital signal sequence of the frame while thinning it out, and stores the digital signal sequence, that is, the input image data, into the input video port.
  • Write at a synchronized rate store a predetermined number of video frames, for example, one video frame, and then read out in synchronization with the encoding speed of the transmission path that is determined by the transmission rate. In this way, the speed of the input plane image data is converted, and at the same time the data is read out, the input image data for the next new video frame can be written.
  • the speed-converted input image data is the same as the conventional code at the coding speed.
  • the encoding is performed.
  • the contents of one video field are updated every one frame period, but the resolution switching signal is one video frame.
  • the first field is subjected to inter-field encoding using the above-mentioned encoded frame memory, and then the second field is continued.
  • the field is an inter-field code while reading the reproduced image locally decoded in the above-mentioned encoding process from the head address of the above-mentioned encoded frame memory in order.
  • Read-in is controlled in field units.
  • the coding frame memory capacity will be half if one video field is used. Can be implemented.
  • the input image data for one video frame is processed between frames when the resolution is 1 video field, and when the resolution is 1 video frame. It performs processing between fields.
  • the resolution switching signal (501) is transmitted through a transmission path.
  • the input vector blocked by the raster-block scan conversion circuit is converted to a dynamic vector quantized encoder ⁇ , a dynamic vector It is coded through a mix vector quantization decoder 63, an adaptive spatial filter, a subtractor ( 4) , and an adaptive vector quantization coder (7).
  • the encoded data is output at every input block (for example, 16 ⁇ 8 samples).
  • a variable length coding circuit (in 9 converts the above coded data into appropriate codewords and sequentially outputs the data in a format delimited for each input block.
  • the format is input.
  • Fig. 33 shows an example of a block size 16 x 8 sample and a small block size of 4 x 4 samples.
  • the identification information is For example, it can be encoded as pattern information of * 0 ', 1' in a group of eight.
  • the number of effective blocks (502) for which the block identification information is * 1 ' is counted down during one video frame (or field) encoding period. And supplies it to the coding control circuit (9).
  • the transmission data buffer (8) converts the codeword supplied from the variable-length coding circuit (93) into a serial code string, and converts the codeword at a rate synchronized with the coding rate. Code strings are sequentially written, and the written code strings are immediately read out immediately at a speed synchronized with a transmission line clock determined by a transmission rate. The encoding rate and the transmission rate are converted. In addition, the amount of code remaining after reading during one video frame (or field) encoding period, that is, the accumulated amount (211), is calculated. The stored amount is supplied to the encoding control circuit (9) at a timing synchronized with the input video frame pulse.
  • the coding control circuit ( 9) calculates the number of valid blocks supplied from the variable-length coding circuit and the corresponding block identification threshold in the past two video frames ( Or field :) divides, ie, remembers the last and previous encodings, the two valid block counts and the two block identification thresholds corresponding to them. Estimate the amount of movement by focusing on the fluctuation of the image, and use the amount of movement to estimate the amount of movement, and use the new block to be used in encoding the next video frame (or field).
  • the threshold for determining the threshold is determined and supplied to the adaptive vector quantization encoder ( 7 ).
  • the storage amount When the value is larger than the predetermined amount, the reading of the speed conversion input memory (92) is prohibited for a certain period of time, so that the speed conversion is performed so that the input image is dropped. Supplies the input memory control signal (232).
  • the movement amount display circuit $ 4 the movement amount (505) supplied from the encoding control circuit (9) is displayed on an indicator using, for example, an LED element or the like so that a human can visually recognize the movement amount (505). It is a motion amount display circuit with a DZA conversion function as shown.
  • the adaptive vector quantization coding data (210) is decoded by the adaptive vector quantization decoder ⁇ to obtain a reproduction residual vector (212).
  • the reproduction vector (213) is decoded and reproduced by adding the reproduction residual signal vector (212) and the output signal sequence of the selector ⁇ by an adder ⁇ , Written to the coded frame memory.
  • the coded data supplied from the transmission line is first encoded by the variable-length decoder (95) at the rate synchronized with the transmission line port at each input port unit.
  • the encoded data is inversely transformed from the codeword and decoded.
  • the coded data is written into the receive data buffer at a speed synchronized with the transmission line clock, and the decoding speed is immediately synchronized with the clock which is a multiple of the transmission line clock. Reads out in input block units with.
  • the dynamic output vector index (233) is supplied to a dynamic vector quantization decoder and an adaptive spatial filter, and Adaptive vector quantization coding data such as lock identification information, average value, amplitude, normalized output vector index, etc.
  • the data (210) are supplied to the adaptive vector quantization decoder ⁇ , and the reproduction vector (210) is periodically performed at the decoding speed by a decoding operation similar to the conventional one. 2 13) is decrypted and reproduced, and written in the decrypted frame memory ⁇ .
  • the reproduction vector (213) stored in the decrypted frame memory is a block-noise-first scan conversion circuit ( ⁇ through a block-no-last-type digital converter). It is inversely converted into a digital signal sequence, and the reproduced image data for one video frame is written in the speed conversion output memory (96) in synchronization with the decoding speed.
  • the speed conversion output memory (96) After storing a predetermined number of image data, for example, one video frame, the image data is read out at a speed synchronized with the video clock that is asynchronous with the encoding device, and output through the DA converter ⁇ . You.
  • the coding control circuit (9) in order to estimate the amount of movement in the coding control circuit (9), the coding control circuit (9) generates the video frame by the coding before the two video frames.
  • the number of effective blocks was used, but instead of the number of effective blocks, the total code amount of the dynamic output vector index or the transmission data buffer accumulation Amount may be used.
  • FIGS. 34 and 35 are block diagrams showing another embodiment of the present invention.
  • (97) is a block diagram showing a configuration in which the digital signal converted by the analog D converter (1) is reduced.
  • a frame memory capable of storing at least one image frame ( 9 is a controller for reducing the number of pixels, (99) is a frame memory).
  • the address counter of (97), and (100) is the frame memory (97) which finally reads the counter output.
  • (234) a control signal for the controller (98) to control the matching conversion, and (235) a free signal.
  • (236) is a digital video signal read by controlling the address
  • (6) is a motion detection circuit
  • (209 :) is a motion detection result.
  • Inter-frame data (103) is a frame memory capable of holding data of the entire screen by the decoded signal (212) and the restored data (238).
  • the input video signal (201) is thickened and quantized by the AZD converter (1) to become a digital video signal (202).
  • Frame memo 1 ) (97) stores the video signal (202).
  • the user gives an instruction to the pixel reduction controller ( 9 ) on how to reduce pixels or not according to the operation mode.
  • the upper and lower surface elements are truncated, they are given as an encoded input signal (236).
  • the number of pixels is reduced by truncation.
  • the image resolution is not required at all. Therefore, even if subsampling is performed as shown in Fig. 7 (b), no significant image quality degradation occurs. In this case, the number of pixels is reduced by the subsample. Of course, it is also possible to keep the number of pixels unchanged.
  • the read address is generated by the counter (99).
  • the mapping conversion circuit (100) converts the output of the counter (99) into a matching signal according to a control signal (234) from the controller (98). In this way, the final read address (235) is output. By mapping this address, the contents of the frame memory (97) can be read in a specified format.
  • the signal (236) with the reduced number of pixels as described above is already coded and decoded one frame before at the same position on the screen.
  • the read signal is read from the frame memory, and motion detection (valid / invalid judgment) is performed.
  • the judgment result signal (209) output from the motion detection circuit ( 6 ) is sent to the driver (101).
  • the driver (101) calculates the amount of movement by integrating the judgment result signal (209), and drives the meter ($ 4) based on the amount of movement.
  • the judgment result signal (209) and The latest frame signal (236) is interframe-coded by the coded decoded signal (239) one frame before read from the frame memory ⁇ .
  • the transmission buffer ( 8) sends the coded information (210) to the transmission path.
  • the information (240) on the reduction of the number of pixels from the pixel reduction controller (98) may be transmitted by being added to, for example, the head of the frame.
  • the transmission bath ( 8) outputs a control signal for smoothing the information generation amount in accordance with the stored amount, and controls the detection sensitivity in the motion detection circuit.
  • the decoding unit fetches the transmission signal (227) into the reception buffer, and the decoding circuit ⁇
  • the decoded signal (212) is stored in the frame memory, and is used for decoding the next and subsequent frames.
  • insertion of dummy data into the decoded signal (212) in a state where the number of pixels has been reduced is performed for each of the truncated portions. Interpolation is performed on the extracted image. That is, the decoded signal, the insertion data and the interpolation data [238] are written in the frame memory (103), and the data for the entire screen is eventually stored. Since the output signal of the frame memory (103) includes all pixels, a reproduced video signal (215) is obtained by the D / N converter ⁇ .
  • FIG. 38 and FIG. 39 show another embodiment of the present invention.
  • FIG. 38 is a block diagram showing the configuration of an encoding system.
  • (401) encodes an input signal sequence obtained by blocking a plane image signal
  • (104) encodes an input signal sequence.
  • the first-stage vector quantizer, (402) is the index that is the encoded output of the first-stage vector quantizer (104), and (403) is the first stage that has been locally decoded.
  • the output vector, (404) is the quantization error signal of the first-stage vector quantizer (104), and this quantization error signal (404) is the same as the signal from the input signal sequence (401).
  • the first stage output vector and are input to the subtractor (105).
  • (106) is a second-stage vector quantizer for quantizing the quantization error signal (404), and (405) is an encoded output of the second-stage vector quantizer (106).
  • (406) is a second-stage output vector, and (407) is a quantization error signal of the second-stage vector quantizer (106).
  • the signal (407) is obtained from a subtractor (107) that inputs the quantization error signal (404) and the second-stage output vector (406).
  • (108) is the third-stage vector quantizer, and (408) is the index that is the encoded output of the third-stage vector quantizer (108). Then, a combination of the n vector quantizers and subtractors constitutes a hierarchical multistage vector quantizer.
  • (109) is the index of each stage quantizer (104), (106), (108).
  • Index notifiers for storing (402), (405), and (408), (110) is the encoded output selector, and (227) is the code from the encoding city. This is encoded data that is output as encoded output.
  • FIG. 39 is a block diagram showing the configuration of the decoding system of the vector quantization coding apparatus.
  • (227) indicates the coded data to be decoded
  • (111) indicates the decoding data.
  • the vector quantization decoders (112), (113), and (114) described later are used according to the number of quantizer stages when the encoded data is quantized by the encoding device.
  • the switching circuit (111) is provided on the input side and the output side of the vector quantization decoders (112), (113), and (114).
  • (112) is the first stage vector quantization decoder
  • (409) is the first stage output vector
  • (113) is the second stage vector quantization decoder
  • (410) is the second stage vector quantization decoder.
  • Stage output vector (114) is the third stage vector quantization decoder, 11) is the third stage output vector, (115) is the decoded image frame memo, (412) is the decoded image signal, and (116) is the sum of the output of the switching circuit (116) and the decoded image signal (412) of the decoded image frame memory (115).
  • This code uses multistage connection using three stages of vector quantizers to block image signals.
  • the input signal sequence (1) is used as an input vector and quantized by a first-stage vector quantizer (104).
  • the vector is 64 (8 ⁇ 8) dimensions in the first stage.
  • the index (3) based on the quantization result of the first stage is stored in the index notifier (109).
  • the first-stage vector quantizer (104) outputs the output vector ⁇ based on the quantization result, and obtains the difference from the first-stage input signal sequence (401) to obtain the first-stage quantization.
  • An error signal (404) is obtained.
  • the first-stage quantization error signal (404) is the second-stage vector quantizer.
  • the second stage index (405) is stored in the index notch (109).
  • the difference signal (407) from the (404) sequence is obtained and used as the input signal to the third-stage vector quantizer (108).
  • the dimension of the vector in the second stage vector quantizer (106) is lower than the first stage.
  • the third-stage vector quantizer (108) also outputs an output index (408), like the first-stage and second-stage vector quantizers (104) and (106). You The dimension of the vector in the third-stage vector quantizer (108) is 4 (2 x 2).
  • the index notifier (109) is an encoded output selector.
  • the output is selected by (110), and the first-stage index
  • the switching circuit (111) selects the first-stage vector quantization decoder (112), and the first-stage index is decoded. , first-stage output base click preparative Le (409) is obtained, et al is, the switching circuit (111), is written to the adder (116) via the full record over arm Note Li (II 5).
  • the first stage output vector (409) is added to the frame memory output (412) and the adder (116) before the frame memory (115).
  • the contents of the frame memory at the corresponding position are zero, so the contents of the frame memory (115) are output to the first stage output vector (409).
  • the image is formed.
  • the decoded image signal (412) output from the frame memory removes quantization distortion by an adaptive spatial filter (117) that switches the smoothing characteristics according to the number of decoding stages. , And is output to the display as a decoded image signal (413).
  • the switching circuit (111) selects the second-stage vector quantization decoder (113), and the second-stage index is decoded.
  • the output vector of the second stage (410) is the decoded image of the first stage already written in the frame memo (115).
  • the signal (412) is added by the adder (116), and an image having less quantization error is recorded in the frame memory (115).
  • the quantization distortion becomes small, so that the smoothing characteristic of the adaptive space filter (117) is weaker than that in the first stage. In this way, the decoded image signal output has better image quality than in the first stage.
  • the switching circuit (111) operates the third-stage vector quantization decoder (114). Select The output vector of the third stage is added to the encoding result of the second stage already written in the frame memory (115), and is added to the frame memory. Written in Mori (115).
  • the adaptive spatial filter (117) further weakens the smoothing characteristics compared to the second stage, and the decoded surface image signal (415) that has been decoded is output to the display. .
  • FIG. 40 is an explanatory diagram showing an example of the adaptive space filter (117) used in the above-mentioned decoding method.
  • the filter characteristics of the adaptive space filter (117) are expressed by an equation, if the filter output at the pixel position of X is X 'with respect to the pixel arrangement of FIG.
  • Control parameter C 0 ⁇ 1) An example is such a characteristic.
  • the control parameters when there is a large amount of quantization distortion in the decoded output, as in the first-stage vector quantization decoding, the control parameters must be adjusted to enhance the smoothing characteristics. If the value is set to a small value and the decoding output has a small quantization distortion and the resolution is to be ensured, as in the case of the third-stage vector quantization decoding, it is necessary to weaken the smoothing characteristic. , N is set to a value close to 1. Also, in the second stage vector quantization decoding in the middle, it is better to set ⁇ in the middle.
  • the adaptive spatial filter (117) as described above, the quantization distortion of the plane image displayed during decoding is reduced, and the sequential reproduction process is more natural.
  • the number of vector quantizers provided is equal to the number of quantization stages.However, one quantizer is repeatedly used to obtain the same effect as multi-stage connection. Can play 0
  • FIG. 41 shows vector quantization coding of an image signal according to the present invention in which a coding loop is formed using a vector quantization device capable of adaptively switching the number of dimensions.
  • FIG. 2 is a block diagram showing a configuration of an encoding device of the device.
  • (118) is a block size variable blocking circuit that blocks the input 'f' sequence 1 in accordance with the dimension of the vector quantizer.
  • (414) is the residual obtained by subtracting the quantization result from the input signal vector to the previous stage by the subtractor (1 19).
  • Signal vector (120) is a variable-dimensional vector quantizer, (121) is an output vector code table for each stage, (415) is an index, (416) ) Is the output vector based on the quantization, (417) is the image vector of the quantization result up to the number of quantization stages, and this image vector is the quantization vector up to the previous stage.
  • (123) is the block size variable frame memory
  • (418) is the image vector of the quantization result up to the previous stage.
  • FIG. 42 is a block diagram showing the configuration of a decoding device to which the above-mentioned index signal (415) is input.
  • (124) is a variable-dimensional vector quantization decoder
  • (125) is an output vector code table for each stage
  • (419) is an output vector
  • (126) is a block.
  • Variable size frame memory (420) is the image vector of the quantization result up to the previous stage
  • (127) is the addition that adds the output vector and the image vector Vessel.
  • the input image signal from the input signal sequence (401) enters a block size variable blocking circuit (118), and is initially blocked by 8 ⁇ 8 pixels. It is converted to a 64-dimensional vector.
  • the vector (418) of the quantization result up to the previous stage is subtracted by the subtractor (119) from the blocked vector. Since the content of the corresponding position of the memory (123) is zero, the output of the blocking circuit (118) is variable as it is. It becomes the input vector (414) of the dimension vector quantizer (120).
  • the variable-dimensional vector quantizer (120) operates as the first-stage quantizer, and outputs the first-stage code table from the output vector code table (121) according to the number of stages. Perform 64-dimensional vector quantization from the quoted force. As the output of the variable dimension vector quantizer (120), the index (415) of the first-stage quantization and the output vector (416) of the first-stage quantization are output. The vector is added by the adder (122) to the output (418) of the frame memory (123) (zero in the first-stage quantization), and then the result of the first-stage quantization (417) is added. Then, 88 pixels are written to the block size variable frame memory (123).
  • the blocking circuit (118) blocks the 4 ⁇ 4 pixels, outputs a 16-dimensional vector, and outputs the first-stage quantized result vector ( The residual obtained by subtracting 418) is used as the input vector (414) of the variable-dimensional vector quantizer (120).
  • variable-dimensional vector quantizer (120) quotes the code table for the second stage from the output vector code table (121) according to the number of stages. Dimension vector quantization is performed, and the second-stage index (415) and output vector (416) are output. The output vector (416) is added to the vector (418) of the pre-stage quantization result by the adder (122), and the quantum up to the second stage is obtained. The resulting image power is written to the block size variable frame memory (123). Similarly, when the second-stage quantization is completed over the entire screen, the third-stage quantization is performed in the same loop.o
  • the block size of the block circuit (118) is 2 ⁇ 2 pixels, and a 4-dimensional vector is created, and a variable-dimensional vector quantizer is used.
  • the index (415) of the third-stage quantization is output by citing the code table for the third stage. In this way, the indexes of the first-stage quantization are output so that the indexes of the third-stage quantization can be transmitted or recorded in order.
  • the captured index (415) is output to a variable-dimensional vector quantization decoder (124), which acts as a first-stage decoder, and is output by stage.
  • the code table (125) is decoded into a 64-dimensional vector while citing the code table for the first stage.
  • the output vector (419) of the variable-dimensional vector quantization decoder (124) is added to the frame memory output (420) of the frame memory (126). However, in the first stage decoding, the contents of the frame memory (126) are zero, so the output vector (419) is left unchanged.
  • the contents written in the frame memory (126) are the same as those in the encoding system shown in FIG.
  • the output of the frame memory (126) is an adaptive space filter with variable smoothing characteristics. And output as a decoded image signal output (413).
  • the second-stage and third-stage decoding are performed in the same manner as in the encoding.
  • the coarse quantization becomes finer one by one and the image quality is improved. Go.
  • FIG. 43 shows an embodiment of a spatial filter according to the present invention.
  • ⁇ 9 is a one-line delay element of an image signal
  • ⁇ is a one-sample delay element
  • W is an adder
  • ⁇ is an absolute value calculator
  • ⁇ is a comparator
  • ⁇ is a selector
  • (601) is a surface element sample adjacent to the right of the pixel of interest to be smoothed.
  • (602) is the pixel sample adjacent to the pixel of interest
  • (603) is the pixel sample of interest
  • (604) is the pixel sample adjacent to the left of the pixel of interest
  • (605) is the pixel sample of the pixel of interest.
  • (606) is the horizontal high-frequency component signal
  • (607) is the vertical high-frequency component signal
  • (608) is the horizontal filter-one output signal
  • (609) is the horizontal filter high-frequency component signal.
  • a vertical filter output signal, (610) is a selector instruction signal
  • (611) is an image smoothing filter output signal.
  • each pixel sample indicated by (601) to (605) is located on the two-dimensional array of images in a relationship as shown in FIG. m is the horizontal pixel number, 11 is the vertical pixel number, and the pixel sample of interest to be smoothed is S (m, n).
  • the eye pixel sample S (m, n) is composed of four pixel samples S ( m —1, n ), S (m + 1, n), and S adjacent in the horizontal and vertical directions. From (m, n-1) and S (m, n + 1) forces, the high frequency components attenuated by the filter are calculated both horizontally and vertically.
  • the absolute value signal is Ah in the horizontal direction and Av in the vertical direction, it is defined by the following equation.
  • the above-mentioned eyepiece element sample S (m, is determined by one of the horizontal filters composed of the adjacent samples in the horizontal direction among the adjacent samples. The following calculation is performed to obtain the horizontal direction smoothed signal Ph.
  • Ph ⁇ S Cm-1, ⁇ ) + 2S (m, ⁇ ) + S (m + 1, n) ⁇ / 4
  • a vertical filter smoothed signal Pv is obtained by a vertical filter composed of adjacent samples in the vertical direction.
  • the two smoothed signals Ph and Pv obtained by the above calculation are input to the selector), and the smoothed filter one output signal F (611) is input by the comparator. Is output as The comparator ⁇ calculates the smaller of the values of the signals Ah (606) and (607) indicating the absolute value of the high-frequency component attenuated by the filter, and selects the smaller value as follows. Switch the output of data 6.
  • smoothing is performed in the direction in which the high frequency component in the horizontal and vertical directions is small, thereby suppressing only noise having no correlation between pixels.
  • the above embodiment has a horizontal and vertical two-way smoothing circuit and similarly extracts Takashiro components in two directions, it also has a diagonal direction and a four-way smoothing circuit to provide high-frequency components. It goes without saying that better image quality can be obtained by performing the extraction.
  • FIG. 45 shows another embodiment of the present invention, in which an encoding control table having a plurality of threshold value-to-generated information amount characteristics according to the amount of motion and a threshold value having an inverse characteristic thereof. It has a control table.
  • (128) is a frame drop controller that performs frame drop control when the amount of information stored in the transmission buffer exceeds a certain value, and (129) outputs the amount of information stored one period ago.
  • (1 30) is a generated information amount calculator for calculating the generated information amount
  • (1 31) is a previously encoded frame based on the generated information amount and the previous coding control threshold.
  • (1 32) is a generated information amount target value calculator for calculating a generated information amount target value for realizing the accumulated information amount target value
  • (1 33) is a motion amount target value calculator for calculating the generated information amount target value.
  • a threshold value determiner for determining a threshold value for realizing the generated information amount target value in the motion amount; (134) outputs a preset high threshold value when the small amount of movement continues for n (n is a positive integer) times or more, and otherwise sets the above threshold value.
  • a threshold discriminator that outputs the output of the value discriminator, and (135) is a delay circuit that outputs the threshold value of the output of the threshold discriminator at the time of the next encoding.
  • the frame drop control circuit (128) performs frame drop control.
  • the generated information amount calculator (130) calculates and outputs the generated information amount (702). Based on the amount of generated information and the threshold value (703) used for the previous encoding, the amount of movement (704) is determined by the amount of movement detector (131) with reference to the encoding control table described later. Detect and output.
  • the generated information amount target value calculator (132) calculates and outputs a generated information amount target value '(705) for the next encoding based on the stored information amount and the stored information amount target value.
  • the threshold value determiner (133) the target value (705) of the amount of generated information in the movement amount (704) is realized with reference to a threshold value control table described later.
  • the threshold (706) is output.
  • the threshold value discriminator (134) determines in advance that the amount of movement (704) is smaller than the previous encoding by a predetermined number of times D (II is a positive integer) or more consecutive times. High threshold to be set Select a threshold value, otherwise select the threshold value (706) determined by the threshold value determiner (133) and use the threshold value (707) for the next encoding Is output.
  • the delay circuit (135) holds the above-mentioned threshold value (707) and outputs it at the next encoding.
  • the encoding control table will be described with reference to FIG. For example, when the threshold value Th is 2, the generated information amount is divided as shown in the figure, and the movement amount M is output.
  • the above-Ki have value and the amount of information generated Ri by the and the child with the classification tape over table of the amount of information generated that corresponds to each and Ki have value in the same manner detect the motion-out amount 1 O o o
  • the generated information amount is classified and the threshold value Th is output as shown in the figure.
  • a threshold value is determined by inputting the movement amount and the generated information amount target value.
  • the threshold value control method based on the amount of information stored in the transmission buffer has been described. However, the total number of valid blocks or the effective control method for all blocks is described. A threshold value control method using a block ratio may be used, and the same effects as in the above embodiment can be obtained.
  • the case of the inter-frame adaptive vector quantization apparatus has been described, but the moving picture by another method is described.
  • the encoding device may have the same effect as the above embodiment.
  • FIG. 48 shows the details of the vector quantizer of the present invention.
  • FIG. 48 shows an n-stage tree search vector quantizer code incorporating pipeline processing.
  • FIG. 21 is a block diagram showing the configuration of an encoder, in which 21 is the first stage of an encoder in which each stage is pipelined, (53) is the second stage of the encoder, and (55) ) Is a latch that takes in the index and outputs it at a fixed timing.
  • ( 5) is a latch that takes the input vector as an average value and amplitude.
  • a normalization circuit for separating the average value into three components of a normalization input vector.
  • FIG. 49 is a block diagram showing an example of the configuration of the first stage of the encoder. Is a register that latches the input vector at each stage, (57) is a normalized output vector code table,
  • (136) is a polarity inversion circuit for inverting the polarity of the normalized input vector or normalized output vector, and (58) is the input vector (207) and the normalized output vector.
  • the distortion vector for calculating the distortion of the output vector of the record table ⁇ and the normalized output vector whose polarity has been inverted by the polarity inversion circuit (136).
  • the circuit and the leg are comparators for judging the magnitude of the two distortions output from the distortion calculation circuit, and (60) is output to the (n ⁇ 1) -th stage coded output (303) according to the judgment result (307). , 0 'or an index register which outputs the n-th stage encoded output (304),
  • (137) is a selector, and the configuration from the first stage to the a-th stage of the encoder is almost the same as ⁇ : '. The difference is that the output The contents of the vector code table.
  • the first stage does not receive the previous stage coded output, and the nth stage (last stage) input vector register indicates the next. No input vector is sent to the stage
  • FIG. 52 is a block diagram showing a configuration example of a vector quantizer decoder.
  • (S1) denotes an index input to the decoder.
  • Register (62) is a true output vector corresponding to the terminal node of the tree (equivalent to the contents of the code table at the last stage of the encoder).
  • (6) is an output vector read from the code table (62) according to the index signal (304).
  • the register to be touched, (138) includes an amplitude multiplication circuit for multiplying a normalized output vector by an amplitude component and adding an average value, and an average value addition circuit.
  • the normalized output vector of each stage is composed of multiple normalized input vectors that have been average-separated and normalized. Is generated such that the sum of the distortions is minimized based on the distribution of.
  • Etc. can also be used.
  • the normalized output vectors arranged at each stage are symmetrical about the origin in the signal space, with half the number on the left and right of the tree, in the signal space. That is, they are arranged in an inverted relationship.
  • y 0 and y or yo 0 and 0, y 0 ! And i ... are in an inverse relationship to each other.
  • the root is the normalized output vector of the first stage.
  • the normalized output vector is One first-stage normalized output vector _ ( 0 ) (309) read from the code table and (the first stage obtained by inverting ⁇ through the polarity inversion circuit (136))
  • the inverted normalized output vector yd) (310) is input to the distortion operation circuit (58), and the two signals X *, y (0 ) and X *) and (1)
  • the distortion is calculated.
  • the comparator (5 judges the magnitude of the two distortions and outputs a signal (307) indicating the magnitude of the two distortions.
  • the index register (60) outputs the comparator output signal.
  • the index signal is set as the information indicating the polarity of the normalized output vector at the most significant bit position of the n-digit index, and the index signal is output.
  • the normalized input vector (308) is inverted together with the inverted normalized input vector (311) passed through the polarity inverting circuit (136).
  • the selector (137) supplies the normalized input vector (308) to the first stage comparator output signal (307) when the power S 'is applied.
  • the inverted normalized input vector (311) is selected and sent to the second-stage encoder. At this time, the inverted normalized input vector (311) is selected. If (311) is selected, branch selection is performed using the normalized output vector set in the right half of Fig. 51 equivalently from the second stage onwards. . The operation of the encoder in the second and subsequent stages is the same as that shown in Fig. 19, and the true output vector that minimizes the distortion through the distortion operation and comparison operation in each stage. Is searched. Finally, an (n-1) digit binary sequence is added to the second and subsequent bit positions from the most significant bit of the index signal, and an n-digit binary sequence is represented. A index signal (304) is formed. The index signal (304) is taken into the latch ⁇ together with the average value and the amplitude output from the average value separation / normalization circuit ( 5) , and is coded. Sent as output signal (210).
  • the decoder takes the encoder output signal (210) formed through the above process into a latch and separates it into an index signal (304) and average and amplitude information (311). You. Then, the normalization stored on the address represented by the (n-1) digit binary sequence excluding the most significant bit of the index signal (304). The output vector is read from the normalized output vector code table for decoding (62), and the most significant bit power of the index signal (304) is> '. When the value is 0 ', the normalized output vector is output as it is, and when the value is 1', the polarity of the normalized output vector is inverted and output. ⁇ By multiplying the amplitude by the average value addition circuit (138), adding the average value, and latching the result in the register (63), the final output vector is obtained. (212) is obtained.
  • FIG. 56 is a block diagram showing an example of an encoding unit of an image encoding and transmitting apparatus for transmitting moving images and still images according to another embodiment of the present invention.
  • (801) is an input signal sequence obtained by digitizing a signal from a camera
  • (802) is a signal obtained by blocking a signal scanned in one direction of the raster.
  • Blocking circuit for output (803) is a still image controller for controlling the block when transmitting a still image, and (804) is a blocked image controller.
  • the input vector as the coding unit, (805) is a dynamic vector quantizer, (806) is a DVQ index, and (807) is a DVQ output Vector, (808) is an adaptive filter that changes the characteristics by the DVQ index, and (809) is the DVQ output vector that has passed through the adaptive filter (808).
  • (810) is a subtractor (811) is an inter-frame difference vector, (812) is adaptive vector quantization, (813) is AVQ coding information, and (814) is AVQ Output Vector, (815) is an adder, (816) is a local decoding vector, (817) is field memory for the number of pixels in the video, and (818) is delayed. This is the previous frame vector.
  • FIG. 57 is a block diagram showing an example of decoding of the image encoding and transmitting apparatus according to the present invention, wherein (806) is a DVQ index, and (820) is a dynamic block. (808) is an adaptive filter whose characteristics are changed by a DVQ index, and (809) is an adaptive filter (808). (813) is the AVQ encoded information, (819) is the adaptive vector quantizer decoder, and (814) is the difference vector between frames that has been locally decoded.
  • Vector (815) is an adder, (816) is a local decoding vector, (817) is the field memory for the number of pixels of the video, (821) is a frame memo that has the capacity of the number of still image pixels (four times as large as a moving image), (822) is a still image output signal sequence, and (803) is a still image control. (823) is a deblocking circuit that scan-converts the blocked vector in one direction in the raster.
  • (824) is a moving image output signal sequence.
  • FIG. 56 in the case of encoding a moving image, the same operation as in the conventional column is performed.
  • the smoothing characteristic is adaptively changed by the DVQ index (806) in the filler in the interframe coding / decoding loop.
  • An adaptive filter (808) is used. This operation is expressed by the following equation when the filter output of the X pixel is X 'in the pixel arrangement of FIG. 58.
  • control variable ⁇ is expressed by the following equation, where u is the horizontal component of the moving vector indicated by the DVQ index, and V is the vertical component.
  • e “lul + lvl) is a positive constant determined by the statistical properties of the image.
  • the above equation uses the absolute value distance of the moving vector. May be used.
  • the pixels corresponding to the positions of double circles, circles, triangles, and squares in Fig. 58 are encoded separately. Try to do.
  • the encoded pixel of the moving image is assumed to be the position of the double circle mark.
  • still image coding first, only the double-circle pixels are blocked, and the data is transmitted after intra-frame coding. When this is completed, inter-frame encoding is performed using the signal quantized and written in the field memory (817) as a predicted value.
  • the input signal (801) does not change during the inter-frame encoding, so that the inter-frame encoding repeatedly encodes the adaptive vector quantization error. become.
  • the decoded value of the double circle pixel converges over time.
  • the still image controller (803) blocks the pixels marked with circles in Fig. 58 so as to block them. Give instructions to the king circuit.
  • the pixels with circles start encoding using the decoded value of the pixel with double circles encoded immediately before as the predicted value.
  • the triangular pixel encoding is performed, and after that, the four sequences are performed in order, such as square pixels. .
  • the decoding of a moving image in the decoding city is the same as the operation of the conventional example, but in the case of decoding a still image, the decoded signal is stored in the still image frame memory (821). Taken and taken in. If the encoding device on the still image transmitting side encodes and transmits the double circle pixel shown in Fig. 58, the still image controller (803) on the decoding device on the receiving side transmits the still image. Control is performed such that the decoded signal is written at the pixel position of the double circle in the frame memory (821). Even if only double circle pixels are transmitted to the decoding device on the receiving side, it is possible to display a rough whole image at an early point in still image transmission by performing interpolation processing. is there.
  • the adaptive filter is controlled by the DVQ index even during still image transmission.
  • another control as follows is performed. Is good.
  • frame-to-frame coding of the pixels marked with a circle in Fig. 58 starts, at this time, the size of the lid is reduced, and gradually approaches * 1 '. .
  • the input of the camera displaying the still image does not change during the still surface transmission; the still image frame is provided at the entrance of the encoding city.
  • the still image frame is provided at the entrance of the encoding city.
  • the camera input can be changed.
  • the increase in hardware can be reduced by sharing it with the still picture frame memory of the decryption city.
  • An image signal encoding / decoding device is applied to a television conference device or a television telephone device.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)

Abstract

On utilise la corrélation entre des images adjacentes d'un signal d'image animée pour coder et décoder le signal tout en détectant le mouvement de chaque bloc d'une image. Un circuit supprimant l'amplitude différentielle supprime de façon non linéaire l'amplitude des données codées d'un bloc d'une différence entre images fondée sur une valeur seuil servant à la détection du mouvement. Ce circuit supprime nettement l'amplitude lorsqu'une valeur de mouvement détectée est importante, pour supprimer l'augmentation du nombre de données codées de sorte que l'image animée puisse être suivie avec plus de fidélité. Lorsque le mouvement est faible, les caractéristiques de suppression sont réduites pour améliorer la qualité de l'image telle qu'elle est perçue. En outre, la séquence du signal d'image est intégrée avec un temps pour chaque image au moyen d'un circuit à intégration de temps dont le signal de sortie est, en même temps, stocké dans une mémoire d'images et affiché. Donc l'appareil n'est pas encombrant et il est possible d'éliminer la diminution de l'efficacité du codage et l'augmentation de la génération des informations en maintenant un temps de retard raisonnable et une corrélation entre images appropriée.
PCT/JP1988/000796 1988-08-11 1988-08-11 Appareil de codage et de decodage d'image Ceased WO1992005667A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US07/340,009 US5010401A (en) 1988-08-11 1988-08-11 Picture coding and decoding apparatus using vector quantization
PCT/JP1988/000796 WO1992005667A1 (fr) 1988-08-11 1988-08-11 Appareil de codage et de decodage d'image

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP1988/000796 WO1992005667A1 (fr) 1988-08-11 1988-08-11 Appareil de codage et de decodage d'image

Publications (1)

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WO1992005667A1 true WO1992005667A1 (fr) 1992-04-02

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2162280C2 (ru) * 1993-10-13 2001-01-20 Рка Томсон Лайсенсинг Корпорейшн Устройство компрессии с дифференциальной импульсно-кодовой модуляцией

Citations (7)

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Publication number Priority date Publication date Assignee Title
JPS61237519A (ja) * 1985-04-12 1986-10-22 Mitsubishi Electric Corp フレ−ム間適応ベクトル量子化符号化装置
JPS62108687A (ja) * 1985-11-06 1987-05-19 Fujitsu Ltd 画像信号符号化パラメ−タ制御方式
JPS62164391A (ja) * 1986-01-14 1987-07-21 Mitsubishi Electric Corp 画像符号化伝送装置
JPS62164392A (ja) * 1986-01-14 1987-07-21 Mitsubishi Electric Corp フレ−ム間適応ベクトル量子化符号化装置
JPS62176279A (ja) * 1986-01-29 1987-08-03 Mitsubishi Electric Corp 映像符号化復号化装置
JPS63155888A (ja) * 1986-12-18 1988-06-29 Mitsubishi Electric Corp 画像符号化制御方式
JPS63160485A (ja) * 1986-12-24 1988-07-04 Mitsubishi Electric Corp 画像符号化伝送方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61237519A (ja) * 1985-04-12 1986-10-22 Mitsubishi Electric Corp フレ−ム間適応ベクトル量子化符号化装置
JPS62108687A (ja) * 1985-11-06 1987-05-19 Fujitsu Ltd 画像信号符号化パラメ−タ制御方式
JPS62164391A (ja) * 1986-01-14 1987-07-21 Mitsubishi Electric Corp 画像符号化伝送装置
JPS62164392A (ja) * 1986-01-14 1987-07-21 Mitsubishi Electric Corp フレ−ム間適応ベクトル量子化符号化装置
JPS62176279A (ja) * 1986-01-29 1987-08-03 Mitsubishi Electric Corp 映像符号化復号化装置
JPS63155888A (ja) * 1986-12-18 1988-06-29 Mitsubishi Electric Corp 画像符号化制御方式
JPS63160485A (ja) * 1986-12-24 1988-07-04 Mitsubishi Electric Corp 画像符号化伝送方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2162280C2 (ru) * 1993-10-13 2001-01-20 Рка Томсон Лайсенсинг Корпорейшн Устройство компрессии с дифференциальной импульсно-кодовой модуляцией

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