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WO1992003848A2 - Stacking of integrated circuits - Google Patents

Stacking of integrated circuits Download PDF

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Publication number
WO1992003848A2
WO1992003848A2 PCT/GB1991/001459 GB9101459W WO9203848A2 WO 1992003848 A2 WO1992003848 A2 WO 1992003848A2 GB 9101459 W GB9101459 W GB 9101459W WO 9203848 A2 WO9203848 A2 WO 9203848A2
Authority
WO
WIPO (PCT)
Prior art keywords
wafer
conductive material
integrated circuit
electrically conductive
plug
Prior art date
Application number
PCT/GB1991/001459
Other languages
French (fr)
Other versions
WO1992003848A3 (en
Inventor
Niko Miaoulis
Original Assignee
Lsi Logic Europe Plc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lsi Logic Europe Plc filed Critical Lsi Logic Europe Plc
Publication of WO1992003848A2 publication Critical patent/WO1992003848A2/en
Publication of WO1992003848A3 publication Critical patent/WO1992003848A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
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    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
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    • H01L2924/01033—Arsenic [As]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Definitions

  • This invention relates to the stacking of a plurality of integrated circuits on top of each other, and also to the product of that process and the intermediate product which forms part of the stack.
  • an integrated circuit comprising a substrate having holes therethrough, said holes being filled with plugs of electrically conductive material which protrude above the surface of the substrate on at least one face of the substrate.
  • the invention also includes a stack of integrated circuits wherein the circuits are spaced from each other by the protruding plugs and are electrically interconnected by one or more such plugs of conductive material.
  • a method of fabricating a wafer for an integrated circuit which comprises the steps of making a hole through a wafer with an electrically insulating surface layer in the hole, and filling the hole with an elect "ically conductive material to form a plug which protrudes above the surface of the wafer on at least one face of the wafer.
  • a method of fabricating a wafer for an integrated circuit comprising the steps of making a well in the wafer with an electrically insulating surface layer, filling the well with a plug of electrically conductive material, grinding the wafer, to remove the wafer material below the well thereby to expose the bottom of the electrically conductive material, and providing a protruding portion of electrically conductive material at at least one end of the plug.
  • Figs. 1 to 5 show the stages in the fabrication of the intermediate product of the invention.
  • Fig. 6 shows a stack of individual integrated circuit chips.
  • the first stage in the fabrication process of a silicon wafer 10 of initial thickness T is the creation of a plurality of deep wells 12 in the silicon wafer. These can be made by a suitable etching or cutting process.
  • the wells 12 can be purpose-designed contact areas or existing bond pad sites, and the depth of the wells will depend upon the desired final wafer thickness.
  • each well 12 is coated with a suitable insulating medium to form an insulating layer 14. If the wells are cut by a laser, with oxygen present, this will form a silicon oxide layer on the surface of the well, and in this case there will be no need for a separate insulating layer 14.
  • the wells 12 are then filled with a suitable electrically conductive material 16, up to the top surface of the wafer, to form a plug.
  • the underside of the wafer 10 is ground away to reduce the wafer to a lesser thickness t. This exposes the conductive material 16 at the back surface of the wafer, as shown in Fig. 4.
  • the back of the wafer is covered by a suitable layer 18 of electrically insulating material and holes are made through this to the electrical contacts which are constituted by the plugs of electrically conductive material 16.
  • the back contact areas are covered by a "bump" of suitable electrically conductive material in order form a protruding pad 20.
  • Each pad 20 contacting the top surf ⁇ ⁇ of the plug of the adjacent chip one has an electrical contact which extends through the plurality of chips and forms a continuous through contact.
  • a suitable wire bond 22 can be connected to the through contact plug.
  • the individual chips can be stacked together after wafer sawing, or a combination of different chips can be combined together.
  • the protruding pad is at the bottom of the wafer, one could alternatively or additionally provide a protruding pad at the upper face of the wafer.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

An integrated circuit wafer (10) is made with a through-going plug (16) of electrically conductive material which protrudes above the wafer surface so that one can stack integrated circuits spaced from each other but interconnected electrically by the plugs (16) which extend therethrough in mutual contact.

Description

STACKING OF INTEGRATED CIRCUITS
This invention relates to the stacking of a plurality of integrated circuits on top of each other, and also to the product of that process and the intermediate product which forms part of the stack.
It is an object of the present invention to provide a method of stacking integrated circuits one on top of another in such a manner that they are electrically connected together and also in such a way that the resulting product can be processed and packaged in the normal manner using conventional assembly methods.
In accordance with the present invention there is provided an integrated circuit comprising a substrate having holes therethrough, said holes being filled with plugs of electrically conductive material which protrude above the surface of the substrate on at least one face of the substrate. The invention also includes a stack of integrated circuits wherein the circuits are spaced from each other by the protruding plugs and are electrically interconnected by one or more such plugs of conductive material. Also in accordance with the invention there is provided a method of fabricating a wafer for an integrated circuit which comprises the steps of making a hole through a wafer with an electrically insulating surface layer in the hole, and filling the hole with an elect "ically conductive material to form a plug which protrudes above the surface of the wafer on at least one face of the wafer.
Also in accordance with the present invention there is provided a method of fabricating a wafer for an integrated circuit, comprising the steps of making a well in the wafer with an electrically insulating surface layer, filling the well with a plug of electrically conductive material, grinding the wafer, to remove the wafer material below the well thereby to expose the bottom of the electrically conductive material, and providing a protruding portion of electrically conductive material at at least one end of the plug.
In order that the invention may be more fully understood, one presently preferred embodiment will now be described by way of example and with reference to the accompanying drawings, in which:
Figs. 1 to 5 show the stages in the fabrication of the intermediate product of the invention; and
Fig. 6 shows a stack of individual integrated circuit chips.
As shown in Fig. 1, the first stage in the fabrication process of a silicon wafer 10 of initial thickness T is the creation of a plurality of deep wells 12 in the silicon wafer. These can be made by a suitable etching or cutting process. The wells 12 can be purpose-designed contact areas or existing bond pad sites, and the depth of the wells will depend upon the desired final wafer thickness.
As shown in Fig. 2, the internal surface of each well 12 is coated with a suitable insulating medium to form an insulating layer 14. If the wells are cut by a laser, with oxygen present, this will form a silicon oxide layer on the surface of the well, and in this case there will be no need for a separate insulating layer 14.
As shown in Fig. 3, the wells 12 are then filled with a suitable electrically conductive material 16, up to the top surface of the wafer, to form a plug. Next, the underside of the wafer 10 is ground away to reduce the wafer to a lesser thickness t. This exposes the conductive material 16 at the back surface of the wafer, as shown in Fig. 4. Next, as shown in Fig. 5, the back of the wafer is covered by a suitable layer 18 of electrically insulating material and holes are made through this to the electrical contacts which are constituted by the plugs of electrically conductive material 16. After this, the back contact areas are covered by a "bump" of suitable electrically conductive material in order form a protruding pad 20. This pad 20 <• ables t..a fabricated wafer to become one component i** a block or stack of wafers as shown in Fig. 6. With each pad 20 contacting the top surfέ Ϊ of the plug of the adjacent chip one has an electrical contact which extends through the plurality of chips and forms a continuous through contact. A suitable wire bond 22 can be connected to the through contact plug. The individual chips can be stacked together after wafer sawing, or a combination of different chips can be combined together.
Although in the embodiment described above the protruding pad is at the bottom of the wafer, one could alternatively or additionally provide a protruding pad at the upper face of the wafer.

Claims

CLAIMS :
1. An integrated circuit comprising a substrate having holes therethrough, said holes being filled with plugs of electrically conductive material which protrude above the surface of the substrate on at least one face of the substrate.
2. An integrated circuit as claimed in claim 1, in which the plugs protrude above a surface of the substrate which is otherwise covered with a layer of electrically insulating material.
3. An integrated circuit as claimed in claim 1 or 2, in which the holes have an electrically insulating surface layer.
4. A stack of integrated circuits as claimed in any preceding claim, wherein the circuits are spaced from each other by the protruding plugs and are electrically interconnected by one or more such plugs of conductive material.
5. A method of fabricating a wafer for an integrated circuit which comprises the steps of making a hole through a wafer with an electrically insulating surface layer in the hole, and filling the hole with an electrically conductive material to form a plug which protrudes above the surface of the wafer on at least one face of the wafer.
6. A method of fabricating a wafer for an integrated circuit, comprising the steps of making a well in the wafer with an electrically insulating surface layer, filling the well with a plug of electrically conductive material, grinding the wafer to remove the wafer material below the well thereby to expose the bottom of the electrically conductive material, and providing a protruding portion of electrically conductive material at at least one end of the plug.
7. A method as claimed in claim 6, which includes coating the wafer material around the exposed bottom of the plug with a layer of electrically insulating material.
PCT/GB1991/001459 1990-08-28 1991-08-28 Stacking of integrated circuits WO1992003848A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB909018766A GB9018766D0 (en) 1990-08-28 1990-08-28 Stacking of integrated circuits
GB9018766.7 1990-08-28

Publications (2)

Publication Number Publication Date
WO1992003848A2 true WO1992003848A2 (en) 1992-03-05
WO1992003848A3 WO1992003848A3 (en) 1992-07-23

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WO1994025982A1 (en) * 1993-05-05 1994-11-10 Siemens Aktiengesellschaft Contact structure for vertical chip connections
WO1994025981A1 (en) * 1993-05-05 1994-11-10 Siemens Aktiengesellschaft Process for producing vertically connected semiconductor components
EP0693778A3 (en) * 1994-07-20 1997-01-02 Mitsubishi Electric Corp Semiconductor device with integrated heat sink
WO1998019337A1 (en) 1996-10-29 1998-05-07 Trusi Technologies, Llc Integrated circuits and methods for their fabrication
EP0851492A3 (en) * 1996-12-06 1998-12-16 Texas Instruments Incorporated Surface-mounted substrate structure and method
US6322903B1 (en) 1999-12-06 2001-11-27 Tru-Si Technologies, Inc. Package of integrated circuits and vertical integration
EP1233444A3 (en) * 1992-04-08 2002-12-11 LEEDY, Glenn J. Membrane dielectric isolation ic fabrication
US6498074B2 (en) 1996-10-29 2002-12-24 Tru-Si Technologies, Inc. Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners
WO2003003423A1 (en) 2001-06-29 2003-01-09 Xanoptix, Inc. Topside active optical device apparatus and method
WO2002049107A3 (en) * 2000-12-13 2003-04-17 Medtronic Inc Method for stacking semiconductor die within an implanted medical device
US6717254B2 (en) 2001-02-22 2004-04-06 Tru-Si Technologies, Inc. Devices having substrates with opening passing through the substrates and conductors in the openings, and methods of manufacture
US6848177B2 (en) 2002-03-28 2005-02-01 Intel Corporation Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme
EP1503406A2 (en) 1996-10-29 2005-02-02 Tru-Si Technologies, Inc. Back-side contact pads of a semiconductor chip
US6882030B2 (en) 1996-10-29 2005-04-19 Tru-Si Technologies, Inc. Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate
US6908845B2 (en) 2002-03-28 2005-06-21 Intel Corporation Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme
EP1248295A3 (en) * 2001-04-06 2005-07-13 Shinko Electric Industries Co. Ltd. Semiconductor element, connection structure thereof, semiconductor device using a plurality of such elements and processes for making the same
WO2008005586A3 (en) * 2006-06-30 2008-02-07 Sony Ericsson Mobile Comm Ab Flipped, stacked-chip ic packaging for high bandwidth data transfer buses
US8841778B2 (en) 1997-04-04 2014-09-23 Glenn J Leedy Three dimensional memory structure

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US6714625B1 (en) 1992-04-08 2004-03-30 Elm Technology Corporation Lithography device for semiconductor circuit pattern generation
US5915167A (en) 1997-04-04 1999-06-22 Elm Technology Corporation Three dimensional structure memory

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