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WO1992001089A1 - Procede de cristallisation - Google Patents

Procede de cristallisation Download PDF

Info

Publication number
WO1992001089A1
WO1992001089A1 PCT/GB1991/001086 GB9101086W WO9201089A1 WO 1992001089 A1 WO1992001089 A1 WO 1992001089A1 GB 9101086 W GB9101086 W GB 9101086W WO 9201089 A1 WO9201089 A1 WO 9201089A1
Authority
WO
WIPO (PCT)
Prior art keywords
gold
silicon
crystallisation
amorphous silicon
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/GB1991/001086
Other languages
English (en)
Inventor
John Stoemenos
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BAE Systems Electronics Ltd
Original Assignee
GEC Marconi Ltd
Marconi Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GEC Marconi Ltd, Marconi Co Ltd filed Critical GEC Marconi Ltd
Publication of WO1992001089A1 publication Critical patent/WO1992001089A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B1/00—Single-crystal growth directly from the solid state
    • C30B1/02—Single-crystal growth directly from the solid state by thermal treatment, e.g. strain annealing
    • C30B1/023—Single-crystal growth directly from the solid state by thermal treatment, e.g. strain annealing from solids with amorphous structure
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02672—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using crystallisation enhancing elements

Definitions

  • This invention relates to the crystallisation of amorphous silicon.
  • Figure 1 shows a plan view taken after fifteen minutes anneal, with a diffraction inset showing amorphous material. One minute later, rapid crystallisation occurred resulting in micron size crystal formation, see Figure 2. Area A, as seen in Figure 3, is a large single crystal as can be seen from the diffraction pattern.
  • a number of black contamination spots are visible on all of the plan view figures relating to in situ-heating, and serve as position markers. Their presence is normal.
  • TEM, XTEM and SEM were used to characterise the crystallisation resulting from annealing amorphous silicon (a-Si ) films prepared using Plasma Enhanced Chemical Vapour Deposition (PECVD) overlying a thin gold film on a thermally-oxidised silicon base.
  • a-Si amorphous silicon
  • PECVD Plasma Enhanced Chemical Vapour Deposition
  • the a-Si thickness was estimated as l ⁇ m and the gold thickness as O.l ⁇ m.
  • the a-Si was hydrogenated during deposition.
  • Sample A is as described above.
  • Sample B the gold was distributed in an array of 50 ⁇ diameter dots in a lattice of several millimetres spacing.
  • Sample C was the control sample in which no gold was present.
  • Samples A, B and C were annealed at 600°C for 24hrs in a furnace after being sealed in an evacuated ampoule.
  • the film was completely amorphous.
  • a gold layer was present.
  • the film was amorphous.
  • the a-Si thickness was 0.9 m and the gold layer was about 40 to 50nm thick, see Figure 6.
  • Bad adhesion was observed both macro and microscopically. Immersion into acetone was sufficient to peel away large sections of the film due to the surface tension of the acetone. XTEM confirms this, as poor adhesion is seen in both the a-Si/gold layer and the gold/Si 0 2 layer. This bad adhesion was also seen macroscopically in sample B in the region of the gold dots. Note that there was no adhesion problem in sample C which had no gold content.
  • Gold dots Annealed at 600°C for 24 hrs.
  • the microstructure was mostly a-Si with areas of defective mosaic polysilicon. SEM impression (secondary image, no tilt, cleaning or coating).
  • Films of amorphous silicon of thickness 300nm were deposited onto silicon wafers by LPCVD, rather than PECVD as used before, in order to reduce the hydrogen content and thereby reduce the damage to the film from hydrogen evolution during the anneal/crystallisation. These films were cleaned by plasma etching and then coated with 60nm of gold. Samples were taken from these wafers and were placed in quartz ampoules which were evacuated and then annealed for 24 hours, some at 500°C and some at 600°C.
  • FIGS 11,12 are cross sectional TEMs from the hazy areas of the sample which show that a film of pure silicon has been formed over the surface of the sample and a gold/silicon alloy nearest the substrate. Between pure silicon film and the gold/silicon alloy is a thin interlayer about 1.5nm thick. In addition, a number of small gold particles remain on the surface of the sample.
  • FIG. 13 A plan view micrograph (Figure 13) from the same area shows a mixture of silicon and gold crystallites, but diffraction patterns from the film reveal the presence of substantial single crystalline areas (see insets to Figures 11 and 13). This is attributed to the "single" crystalline silicon overlayer, which is clearly revealed by the cross sectional mi rographs.
  • the gold in order for this process to occur, the gold must be in intimate contact with the amorphous silicon, i.e. intermediate contamination layers of, for example, native oxide must not be present or must be very thin. Except in so far as it may affect the nature of any intermediate layers, it does not matter whether the gold is on top of the silicon or vice versa. Both positions have been shown to be effective.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Thermal Sciences (AREA)
  • Recrystallisation Techniques (AREA)
  • Organic Low-Molecular-Weight Compounds And Preparation Thereof (AREA)
  • Low-Molecular Organic Synthesis Reactions Using Catalysts (AREA)

Abstract

Dans un procédé de cristallisation de silicium amorphe, de l'or est placé en contact intime avec le silicium amorphe, et le silicum et l'or sont recuits à une température d'au moins 400 °C. Le silicium amorphe est de préférence déposé sur un substrat, l'or étant placé sur le silicium ou entre le silicium et le substrat. L'or peut être déposé sous forme d'une matrice de points.
PCT/GB1991/001086 1990-07-03 1991-07-03 Procede de cristallisation Ceased WO1992001089A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB909014723A GB9014723D0 (en) 1990-07-03 1990-07-03 Crystallisation process
GB9014723.2 1990-07-03

Publications (1)

Publication Number Publication Date
WO1992001089A1 true WO1992001089A1 (fr) 1992-01-23

Family

ID=10678581

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB1991/001086 Ceased WO1992001089A1 (fr) 1990-07-03 1991-07-03 Procede de cristallisation

Country Status (4)

Country Link
EP (1) EP0489900A1 (fr)
JP (1) JPH05501701A (fr)
GB (2) GB9014723D0 (fr)
WO (1) WO1992001089A1 (fr)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0612102A3 (fr) * 1993-02-15 1994-10-19 Semiconductor Energy Lab Couche semi-conductrice cristallisée, dispositif semi-conducteur l'utilisant et leur procédé de fabrication.
EP0609867A3 (fr) * 1993-02-03 1995-01-11 Semiconductor Energy Lab Procédé de fabrication d'une couche semi-conductrice cristallisée et procédé de fabrication d'un dispositif semi-conducteur l'utilisant.
EP0656644A1 (fr) * 1993-12-02 1995-06-07 Semiconductor Energy Laboratory Co., Ltd. Procédé de fabrication d'une couche cristallisée semi-conductrice et de dispositifs semi-conducteurs l'utilisant
KR100273831B1 (ko) * 1993-10-29 2001-01-15 야마자끼 순페이 반도체 장치의 제조 방법
US6730549B1 (en) 1993-06-25 2004-05-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for its preparation
US6997985B1 (en) 1993-02-15 2006-02-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor, semiconductor device, and method for fabricating the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1987003916A1 (fr) * 1985-12-19 1987-07-02 Allied Corporation Procede de formation de monocristaux de silicium par cristallisation laser a germe cristallin d'une couche epitaxiale a l'etat solide
EP0334110A2 (fr) * 1988-03-24 1989-09-27 Siemens Aktiengesellschaft Procédé de fabrication de couches polycristallines à gros cristaux pour composants à semi-conducteurs en couches minces, en particulier des cellules solaires

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU616739B2 (en) * 1988-03-11 1991-11-07 Unisearch Limited Improved solution growth of silicon films

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1987003916A1 (fr) * 1985-12-19 1987-07-02 Allied Corporation Procede de formation de monocristaux de silicium par cristallisation laser a germe cristallin d'une couche epitaxiale a l'etat solide
EP0334110A2 (fr) * 1988-03-24 1989-09-27 Siemens Aktiengesellschaft Procédé de fabrication de couches polycristallines à gros cristaux pour composants à semi-conducteurs en couches minces, en particulier des cellules solaires

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
Applied Physics Letters, vol. 58, no. 11, 18 March 1991, American Institute of Physics, US; J. Stoemenos et al.: "Crystallization of amorphous silicon by reconstructive transformation utilizing gold", pages 1196-1198, see page 1196, left-hand column, paragraphs 4,5; page 1196, right-hand column, paragraph 3 *
Applied Surface Science, vol. 36, nos. 1-4, North-Holland Physics Publ. Division, Amsterdam, NL; S. Caune et al.: "Combined CW laser and furnace annealing of amorphous silicon and germanium in contact with some metals", pages 597-604, see page 602, paragraphs 3 and 4, table 2 *
J. Appl. Phys., vol. 62, no. 9, 1 November 1987, American Institute of Physics, US; L. Hultman et al.: "Crystallization of amorphous silicon during thin-film gold reaction", pages 3647-3655, see abstract (cited in the application) *
Journal Of Non-Crystalline Solids, vol. 7, 1972, S.R. Herd et al.: "Metal contact induced crystallization in films of amorphous silicon and germanium", pages 309-327, see page 311, paragraphs 3-5 *

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6610142B1 (en) 1993-02-03 2003-08-26 Semiconductor Energy Laboratory Co., Ltd. Process for fabricating semiconductor and process for fabricating semiconductor device
EP0609867A3 (fr) * 1993-02-03 1995-01-11 Semiconductor Energy Lab Procédé de fabrication d'une couche semi-conductrice cristallisée et procédé de fabrication d'un dispositif semi-conducteur l'utilisant.
EP1207549A3 (fr) * 1993-02-03 2010-07-07 Semiconductor Energy Laboratory Co., Ltd. Procédé de fabrication d'un composant à base de semiconducteur
EP0997950A3 (fr) * 1993-02-03 2009-01-28 Semiconductor Energy Laboratory Co., Ltd. Procédé d amélioration de crystallisation des couches semi-conductrices particulièrement pour transistors à couches minces
KR100267145B1 (ko) * 1993-02-03 2000-10-16 야마자끼 순페이 박막트랜지스터 제작방법
CN100416750C (zh) * 1993-02-03 2008-09-03 株式会社半导体能源研究所 半导体制造工艺和半导体器件制造工艺
US6997985B1 (en) 1993-02-15 2006-02-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor, semiconductor device, and method for fabricating the same
EP0612102A3 (fr) * 1993-02-15 1994-10-19 Semiconductor Energy Lab Couche semi-conductrice cristallisée, dispositif semi-conducteur l'utilisant et leur procédé de fabrication.
US6084247A (en) * 1993-02-15 2000-07-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a catalyst enhanced crystallized layer
US6730549B1 (en) 1993-06-25 2004-05-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for its preparation
US6756657B1 (en) 1993-06-25 2004-06-29 Semiconductor Energy Laboratory Co., Ltd. Method of preparing a semiconductor having controlled crystal orientation
US7148094B2 (en) 1993-06-25 2006-12-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for its preparation
US6285042B1 (en) 1993-10-29 2001-09-04 Semiconductor Energy Laboratory Co., Ltd. Active Matry Display
US6335541B1 (en) 1993-10-29 2002-01-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor thin film transistor with crystal orientation
KR100273827B1 (ko) * 1993-10-29 2001-01-15 야마자끼 순페이 반도체 장치
US6998639B2 (en) 1993-10-29 2006-02-14 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor device
KR100273831B1 (ko) * 1993-10-29 2001-01-15 야마자끼 순페이 반도체 장치의 제조 방법
US7998844B2 (en) 1993-10-29 2011-08-16 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor device
EP0656644A1 (fr) * 1993-12-02 1995-06-07 Semiconductor Energy Laboratory Co., Ltd. Procédé de fabrication d'une couche cristallisée semi-conductrice et de dispositifs semi-conducteurs l'utilisant

Also Published As

Publication number Publication date
EP0489900A1 (fr) 1992-06-17
JPH05501701A (ja) 1993-04-02
GB2245552A (en) 1992-01-08
GB9014723D0 (en) 1990-08-22
GB9114398D0 (en) 1991-08-21

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