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WO1991011827A1 - Substrat de silicium passive - Google Patents

Substrat de silicium passive Download PDF

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Publication number
WO1991011827A1
WO1991011827A1 PCT/US1991/000392 US9100392W WO9111827A1 WO 1991011827 A1 WO1991011827 A1 WO 1991011827A1 US 9100392 W US9100392 W US 9100392W WO 9111827 A1 WO9111827 A1 WO 9111827A1
Authority
WO
WIPO (PCT)
Prior art keywords
silicon
layer
silicon dioxide
dioxide layer
hydrazine
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US1991/000392
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English (en)
Inventor
Marc J. Madou
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commtech International
Original Assignee
Commtech International
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commtech International filed Critical Commtech International
Publication of WO1991011827A1 publication Critical patent/WO1991011827A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02329—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen
    • H01L21/02332—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen into an oxide layer, e.g. changing SiO to SiON
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition

Definitions

  • the present invention relates to a silicon chip which has been passivated in a manner which renders it highly resistive to degradation in the presence of high humidity and/or liquid water.
  • the process is useful in preparing silicon chips for semiconductor processing applications and for producing icroelectrochemical cells on or below the surface of silicon chips.
  • Such insulation layers can comprise silicon dioxide, silicon nitride or silicon oxynitride.
  • silicon dioxide silicon dioxide
  • silicon nitride silicon oxynitride.
  • one or the other of these layers is used although there are instances, set forth, for example, in U.S. Patent 4,062,040, issued December 6, 1977 to S.A. Abbas and R.C. Dockerty, wherein one of these dielectric layers (in. the specific instance mentioned a silicon nitride layer) is deposited over another of these layers (in the instance mentioned a silicon dioxide layer) .
  • the silicon dioxide layer is produced, as is conventionally done, by reaction of the silicon chip with dry oxygen at a temperature of, for example, 800#C, and that the silicon nitride layer is made conventionally, for example by reaction of ammonia and silane or of ammonia and tetrachlorosilane, the thicknesses of each layer can be controlled as is needed for the particular device being formulated.
  • xx. is also known to provide a silicon oxynitride layer, for example by annealing silicon nitride in an oxygen atmosphere, or by annealing silicon dioxide in an ammonia atmosphere, both at elevated temperature.
  • Silicon nitride layers made as discussed above are generally relatively permeable to vaporous water and liquid water (generally due to the existence of small holes) which can pass through such layers and damage the circuitry lying beneath them.
  • the silicon dioxide layers themselves are relatively permeable to water (again generally due to the existence of small holes) which can pass through such layers thereby damaging the device of which they form a part.
  • the present invention is directed to overcoming one or more of the problems as set forth above.
  • a passivated silicon substrate is set forth in accordance with an embodiment of the invention.
  • the passivated substrate comprises a silicon substrate having a surface region on which a passivation coating is required.
  • a silicon dioxide layer covers the surface region, the silicon dioxide layer being no more than about 1,000 Angstroms thick.
  • a silicon oxynitride layer covers the silicon dioxide layer, the silicon oxynitride layer being no more than about 300 Angstroms thick and having been produced by reaction of ammonia, hydrazine or methyl amine with an initially thicker silicon dioxide layer.
  • a silicon nitride layer covers the silicon oxynitride layer.
  • the silicon nitride layer is at least about 250
  • Angstroms thick and is produced by chemical vapor deposition.
  • a method is set forth of passivating a silicon substrate.
  • the method comprises providing a silicon dioxide layer of a desired initial thickness on the surface of the substrate whereat a passivation covering is desired .
  • the silicon dioxide layer is reacted with ammonia, hydrazine or methyl amine to form a silicon oxynitride layer over the silicon dioxide layer.
  • the silicon dioxide layer after the reacting, is from about 10 to about 1,000 Angstroms in thickness.
  • the resulting silicon oxynitride layer is from about 10 to about 300 Angstroms in thickness.
  • a silicon nitride layer at least about 250 Angstroms in thickness is chemically vapor deposited over the silicon oxynitride layer.
  • a passivated silicon substrate in accordance with the present invention has a unique advantage of being substantially moisture impermeable because of the presence of the intermediate silicon oxynitride layer.
  • silicon substrates can be utilized in highly moist environments for long periods of time without deterioration due to the moisture.
  • the thickness of the silicon dioxide layer and the thickness of the silicon nitride layer can be controlled as desired by the device fabricator so as to be appropriate for whatever device is being fabricated.
  • Such a passivation technique is particularly useful in those situations wherein a silicon substrate is to be directly exposed to water containing solutions (liquids). Such can be the case if the device is a microelectrochemical cell which lies upon, or in a well leading into the surface of, a silicon wafer or chip.
  • Figure 1 illustrates, in cross-sectional view, a silicon substrate passivated in accordance with the present invention
  • Figure 2 illustrates, in cross-sectional view, a microchemical sensor passivated in accordance with an embodiment of the present invention.
  • the passivated silicon substrate structure 10 includes a silicon substrate 12 having a surface region 14 on which a passivation coating 16 is required.
  • a silicon dioxide layer 18 covers the surface region 14.
  • the silicon dioxide layer 18 is generally no more than about 1,000 Angstroms thick, and is preferably in the range from about 50 Angstroms thick to about 300 Angstroms thick.
  • a silicon oxynitride layer 20 covers the silicon dioxide layer 18.
  • the silicon oxynitride layer is generally at least about 10 Angstroms thick and is no more than about 300 Angstroms thick. It is produced by reaction of ammonia, hydrazine or methyl amine, preferably ammonia, with an initially thicker silicon dioxide layer 18.
  • the reaction with the ammonia is carried out by flowing very pure ammonia over the silicon dioxide layer 18 at a temperature which falls within a range from about 1,000#C to about 1,400#C. Suitably, the temperature can be about 1,350#C.
  • the ammonia is generally flowed over the wafer at about atmospheric pressure but pressure and flow rate are not critical. Other reactive chemicals which might interfere with the reaction must be excluded during the reaction with ammonia. However, chemically inert gases such as nitrogen, argon, helium and the like can be present. Hydrazine or methyl amine may substitute for the ammonia. Mixtures of two or more such compounds can also be used.
  • a silicon nitride layer 22 covers the silicon oxynitride layer 20, the silicon nitride layer 22 being at least about 250 Angstroms, preferably at least about 500 Angstroms thick and having been produced by chemical vapor deposition.
  • chemical vapor deposition can be carried out in any of the ways known in the art.
  • silicon nitride deposition may be affected at temperatures which' fall within the range from about 600#C to about 1, 100#C in accordance with reactions such as the following:
  • Hydrazine or methyl amine can substitute for the ammonia. Mixtures of all or any two such chemicals can also be utilized. However, ammonia is the preferred chemical for this purpose.
  • the silicon dioxide layer 18 can be made by conventional procedures, for example by reacting dry oxygen with underlying silicon substrate 12, for example at a temperature which falls within a range from about 600#C to about 1,000#C.
  • silicon dioxide can be deposited from silane or silicon tetrachloride in accordance with the following reactions at temperatures which fall within a range from about 800#C to about 1,100#C:
  • silicon dioxide can be deposited from silane oxidation at a temperature in the range from about 300#C to about 500#C according to the equation:
  • Figure 2 illustrates an embodiment wherein the technique has been utilized to passivate the surface of an electrochemical cell having a well 24 which includes an electrode 26 and is filled with a water containing electrolytic medium 28.
  • the electrolytic medium can be a liquid solution, a gel, or a solid polymer electrolyte which includes a significant portion of water.
  • a conductor 30 fills a passivated passage 32 -and comes from a backside 34 of the silicon substrate 12 to the electrode 26. The passivation also serves to insulate the conductor 30 from the substrate 12 " .
  • the present invention provides a passivated silicon substrate 10 useful in the semiconductor industry, particularly for the making of integrated circuits, transistors and the like. It is also useful for the manufacture of microelectrochemical cells and half cells.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

L'invention se rapporte à une structure avec substrat de silicium passivé (10) qui comporte une région de surface (14) couverte par une couche de dioxyde de silicium (18) d'une épaisseur ne dépassant pas 1000 Angströms environ. Une couche d'oxynitrure de silicium (20) d'une épaisseur ne dépassant pas 300 Angströms environ couvre la couche de dioxyde de silicium. La couche d'oxynitrure de silicium est produite par réaction d'ammoniac, d'hydrazine ou de méthylamine avec une couche de dioxyde de silicium initialement plus épaisse. Une couche de nitrure de silicium (22) couvre la couche d'oxynitrure de silicium. La couche de nitrure de silicium a une épaisseur d'au moins 250 Angströms environ. Elle est produite par déposition en phase vapeur par procédé chimique. Une couche de passivation ainsi produite assure une isolation électrique et se caractérise par une résistance élevée à l'attaque de l'humidité.
PCT/US1991/000392 1990-01-29 1991-01-22 Substrat de silicium passive Ceased WO1991011827A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US47142390A 1990-01-29 1990-01-29
US471,423 1990-01-29

Publications (1)

Publication Number Publication Date
WO1991011827A1 true WO1991011827A1 (fr) 1991-08-08

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PCT/US1991/000392 Ceased WO1991011827A1 (fr) 1990-01-29 1991-01-22 Substrat de silicium passive

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CA (1) CA2074809A1 (fr)
WO (1) WO1991011827A1 (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5304840A (en) * 1992-07-24 1994-04-19 Trw Inc. Cryogenic radiation-hard dual-layer field oxide for field-effect transistors
US5608252A (en) * 1993-03-10 1997-03-04 Sharp Microelectronics Technology, Inc. Semiconductor with implanted dielectric layer having patched pin-holes
US6011308A (en) * 1996-06-14 2000-01-04 Nec Corporation Semiconductor device having a barrier film formed to prevent the entry of moisture and method of manufacturing the same
WO2000004581A1 (fr) * 1998-07-17 2000-01-27 Infineon Technologies Ag Couche de passivation pour semiconducteurs de puissance a jonctions pn apparaissant a la surface
US20230369070A1 (en) * 2022-05-12 2023-11-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package structure and method of manufacturing thereof

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4062040A (en) * 1975-11-26 1977-12-06 Ibm Corporation Field effect transistor structure and method for making same
JPS5691453A (en) * 1979-12-26 1981-07-24 Hitachi Ltd Manufacturing of semiconductor device
JPS6195515A (ja) * 1984-10-16 1986-05-14 Nec Corp 半導体活性層の形成方法
US4621277A (en) * 1978-06-14 1986-11-04 Fujitsu Limited Semiconductor device having insulating film
US4901133A (en) * 1986-04-02 1990-02-13 Texas Instruments Incorporated Multilayer semi-insulating film for hermetic wafer passivation and method for making same
US4972250A (en) * 1987-03-02 1990-11-20 Microwave Technology, Inc. Protective coating useful as passivation layer for semiconductor devices

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4062040A (en) * 1975-11-26 1977-12-06 Ibm Corporation Field effect transistor structure and method for making same
US4621277A (en) * 1978-06-14 1986-11-04 Fujitsu Limited Semiconductor device having insulating film
JPS5691453A (en) * 1979-12-26 1981-07-24 Hitachi Ltd Manufacturing of semiconductor device
JPS6195515A (ja) * 1984-10-16 1986-05-14 Nec Corp 半導体活性層の形成方法
US4901133A (en) * 1986-04-02 1990-02-13 Texas Instruments Incorporated Multilayer semi-insulating film for hermetic wafer passivation and method for making same
US4972250A (en) * 1987-03-02 1990-11-20 Microwave Technology, Inc. Protective coating useful as passivation layer for semiconductor devices

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN, Vol. 13, No. 1, June 1970, P.J. BURKHARDT, "Composit Silicon Dioxide - Silicon Oxynitride Insulating Layer", page 21. *
IBM TECHNICAL DISCLOSURE BULLETIN, Vol. 13, No. 9, February 1971, V.Y. DOO, "Selective Etch of Silicon Nitride Films", page 246B. *
IBM TECHNICAL DISCLOSURE BULLETIN, Vol. 19, No. 1, June 1976, K.D. BEYER, "Yield Improvement for Thin Si3N4 Layers in Preemitter Passivation Layer Structure of NPN Transistors", pages 134 and 138. *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5304840A (en) * 1992-07-24 1994-04-19 Trw Inc. Cryogenic radiation-hard dual-layer field oxide for field-effect transistors
US5608252A (en) * 1993-03-10 1997-03-04 Sharp Microelectronics Technology, Inc. Semiconductor with implanted dielectric layer having patched pin-holes
US6011308A (en) * 1996-06-14 2000-01-04 Nec Corporation Semiconductor device having a barrier film formed to prevent the entry of moisture and method of manufacturing the same
WO2000004581A1 (fr) * 1998-07-17 2000-01-27 Infineon Technologies Ag Couche de passivation pour semiconducteurs de puissance a jonctions pn apparaissant a la surface
US20230369070A1 (en) * 2022-05-12 2023-11-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package structure and method of manufacturing thereof

Also Published As

Publication number Publication date
CA2074809A1 (fr) 1991-07-30

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