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WO1990009093A1 - Structure semi-conductrice a integration poussee et procede pour sa fabrication - Google Patents

Structure semi-conductrice a integration poussee et procede pour sa fabrication

Info

Publication number
WO1990009093A1
WO1990009093A1 PCT/US1990/000069 US9000069W WO9009093A1 WO 1990009093 A1 WO1990009093 A1 WO 1990009093A1 US 9000069 W US9000069 W US 9000069W WO 9009093 A1 WO9009093 A1 WO 9009093A1
Authority
WO
WIPO (PCT)
Prior art keywords
forming
wiring layer
integrated circuit
decal
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US1990/000069
Other languages
English (en)
Inventor
Scott Laurence Jacobs
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Polylithics Inc
Original Assignee
Polylithics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US07/301,792 external-priority patent/US5059290A/en
Application filed by Polylithics Inc filed Critical Polylithics Inc
Publication of WO1990009093A1 publication Critical patent/WO1990009093A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Definitions

  • This invention relates to the packaging of integrated circuit chips and more particularly to high density, high reliability, extended integration packaging of one or more integrated circuit chips.
  • VLSI Very Large Scale Integration
  • ULSI Ultra Large Scale Integration
  • Multi-chip packaging generally requires wide spacing of chips to accommodate wiring channels, which results in longer wiring distances for chip interconnection, and leads to increased parasitic capacitance and a decrease in system speed.
  • complex packaging structures are inherently expensive and unreliable.
  • the multilayer ceramic substrate provides interconnections for about 100 integrated circuit chips and includes up to 33 internal wiring layers and about 1800 brazed input/output pins for connecting to a next level of packaging.
  • the multilayer ceramic substrate is extremely expensive to fabricate, and the fabrication methods employed limit the density of the substrate's internal wiring.
  • the reliability of the chip to ceramic substrate interconnections generally solder bumps or balls degrades when small, high density interconnections are used because of thermal mismatches between the chips and substrate.
  • Thin film technology has also been employed without the multilayer ceramic substrate in an attempt to provide improved packaging for integrated circuit chips.
  • This technology employs thin film metallization techniques, similar to those employed on the chips themselves, for chip interconnection and packaging.
  • thin film technology for packaging is described in U.S. Patent 4,714,516 to Eichelberger, et al., in which a thin film multilayer wiring structure is sequentially formed over a plurality of fully formed integrated circuit chips disposed adjacent one another on an underlying substrate.
  • the thin film structure comprises alternating layers of polymer insulator and metal, which are formed, layer by layer, over the integrated circuit chips.
  • a thin film decal is formed on a first surface, and then transferred onto a chip or packaging substrate.
  • decals for chip interconnection is disclosed in U.S. Patent 4,755,866 to Marshall, et al. in which an array of high density chips include a plurality of decals, each of which overlies a single chip and part of the adjacent chip. The chips are directly connected to a frame or heat sink. Unfortunately, the use of multiple decals creates alignment, assembly and repair problems.
  • WSI Water Scale Integration
  • a method of forming an extended integration semiconductor structure in which a support substrate, for example wafer-sized transparent glass, has formed thereon a thin film decal having one or more wiring layers separated by dielectric.
  • the insulator is a transparent polymer, for example polyimide, and the thin film wiring layers are formed on the transparent support substrate one layer at a time.
  • Each wiring layer may be tested after it is formed using well-known optical testing techniques, for example by shining light on the glass substrate, polyimide and wiring layer, and comparing the transmitted radiation with an expected pattern.
  • At least one integrated circuit chip is aligned to the thin film decal.
  • Chip alignment may be performed using conventional optical alignment techniques through the transparent substrate and thin film decal.
  • the aligned chip is attached to the thin film decal, and the aligning and attaching steps are performed for second and subsequent chips if desired.
  • a support ring is then mounted on the thin film decal surrounding the aligned integrated circuit chips. Finally, the support substrate is removed, so that the decal is held under tension by the support ring.
  • a plurality of vias referred to as "reach-through vias" are formed through the newly exposed surface of the thin film decal to the integrated circuit chips, using lithographic or other techniques.
  • An extended integration semiconductor structure is thereby formed, comprising a thin film decal having at least one wiring layer therein and a support ring which is attached to the decal and which maintains the decal under tension inside the support ring. At least one integrated circuit chip is attached to the decal inside the support ring, with the chip or chips being aligned to the decal. Reach-through vias form electrical connections between the wiring layer and the integrated circuit chips.
  • the present invention provides an interconnection and packaging technology which allows the chip manufacturer to "integrate" circuitry beyond the boundaries of the actual chips themselves.
  • the extended integration structure creates a "virtual" large area chip which electrically behaves as if it were monolithic.
  • the support substrate is only a temporary substrate for thin film processing, which is removed after mechanical chip attachment, leading to a thin, lightweight structure. Since no substrate is used, electrical and mechanical contacts to a next level of packaging may be made at all points on both sides of the structure.
  • the Usual vertical configuration of a semiconductor chip has not been altered.
  • the thin film decal is formed on the transparent substrate and may be tested layer by layer to promote high yields. Moreover, a defective decal may be tested and rejected or repaired before it is integrated to the chips so that the decal yields are decoupled from those of the chips.
  • Testing of the decal and alignment of the chips may employ well known conventional optical techniques. Unlike electrical continuity testing, optical testing indicates the exact location of a defect, so that repair is facilitated. Customized alignment masks and/or direct writing lithography are not required. Parallel fabrication of the chips and decals keeps cycle time for package fabrication to a minimum. Internal reach-through via connections are employed between the decal and the chip surface.
  • the large area decal to chip connection with internal vias is subject to less mechanical stress than solder ball or other localized connection schemes, resulting in increased reliability. Spacing is held to an absolute minimum, and high input/output and dense wiring capability allow chip designs to "spill over" onto separate dies, without the need for output buffering devices such as slow, high power drivers. High speed is provided due to shortened signal paths. Material costs are negligible, with the support substrate being reusable. Since the design "ground rules" (such as minimum line width) for the decal will usually be more relaxed than that of the chip "ground rules", state of the art fabrication, testing and alignment equipment need not be used, resulting in low capital equipment cost. Accordingly, a low cost, lightweight, fast, dense and reliable extended integration structure is provided.
  • Figures 1A-1D illustrate a method of forming a thin film decal for an extended integration structure according to the present invention.
  • Figures 2A-2E illustrate a method of forming an extended integration semiconductor structure according to the present invention.
  • Figures 3A-3B illustrate top and side plan views of an extended integration structure according to the present invention.
  • Figure 4 illustrates a plurality of different size extended integration structures on a wafer size substrate, prior to removal, according to the present invention.
  • Figures 5A-5D illustrate methods of forming thin film wiring layers for an extended integration structure according to the present invention.
  • Figures 6A-6G illustrate methods of forming reach-through vias for an extended integration structure according to the present invention.
  • Figures 7A-7B illustrate top and side cross- sectional views of one of the reach-through vias of Figure 6B.
  • Figure 8 illustrates a single-chip extended integration structure according to the present invention.
  • FIG. 1A illustrates support substrate 10.
  • Support substrate 10 is preferably a transparent piece of wafer-sized glass.
  • a transparent substrate is employed so that optical alignment and testing techniques may pass light through the transparent substrate as will be described below.
  • a wafer-sized substrate is preferably employed so that conventional lithographic, deposition, testing and other tools may be employed for processing.
  • a first insulating layer 11 preferably a transparent insulating layer of dielectric polyimide is deposited on substrate 10 using conventional techniques.
  • Polyimide 11 may be DuPont 2525 polyimide manufactured by E.I. DuPont Nemoirs, or any other dielectric polyimide. The polyimide is then cured, for example by heating at 400°C for 30 minutes.
  • Metal layer 12 may be a conventional aluminum or copper wiring layer or preferably a more complex chromium clad copper or nickel clad copper layer. Since wiring layer 12 will connect input/output pads on chips, lower density ground rules may be used compared with chip metallization ground rules. For example, 2 ⁇ m ground rules may be employed compared with l ⁇ m or submicron chip ground rules, so that 1:1 projection lithography may be employed, using low cost tools.
  • dielectric layer 11 and wiring layer 12 are l-3 ⁇ m thick to allow for low capacitance and high conductivity interchip wiring.
  • first wiring layer 12 After first wiring layer 12 has been fabricated, it may be tested using conventional optical testing means, for example a KLA model 221 tester manufactured by KLA Corporation. Radiation is passed through support substrate 10, first insulating layer 11 and first wiring layer 12. The radiation pattern is detected by a diode array or other detection means, and compared to an expected pattern of radiation. In one embodiment, the transmitted radiation pattern is compared to an expected pattern stored in a database. In another embodiment, when multiple identical patterns are reproduced in the wiring, a pattern may be compared to its nearest neighbor and any differences may be detected. If the comparison indicates open or short circuits, the metallization may be repaired, the wiring layer may be discarded, or the defective portion may be registered so that it is not used later to form a completed structure. It will also be understood by those skilled in the art that mechanical probes may be employed for continuity testing, by providing probe pads in layer 12.
  • a first internal via layer 13 is formed on first wiring layer 12.
  • Internal via layers connect wiring layers to one another.
  • the process described in Figures IB, 1C and ID is then repeated to form the required number of internal wiring layers in the decal.
  • the polyimide in a previous layer may be partially etched away in a reactive ion etching process, to thereby undercut the metal in the wiring layer.
  • the exposed undercut wiring layer provides a mechanical joint for the next layer of polyimide.
  • each wiring layer may be fabricated in parallel on a separate substrate, and tested as was described in connection with Figures 1A-1C. After testing, each tested layer may be sequentially transferred onto first layer 12 to form the completed decals. Reach through vias may be formed to selectively connect the individual wiring layers.
  • Figure 2A illustrates thin film decal 15 which has been fully formed by repeatedly performing the process of Figures IB-ID to build up an X wiring plane 16 an internal via layer 17, a Y wiring plane 18 and a ground a plane 19, all within an insulator 20, for example polyimide.
  • Polyimide 20 is transparent as is substrate 10, so that the entire structure of Figure 2A is transparent except for the wiring layers. This will become important when aligning a chip to the substrate as will be described below.
  • ground plane 19 is a continuous planar layer (except for a few alignment marks or windows) as opposed to a patterned wiring layer. If ground plane 19 is fabricated first, it is impossible to optically test the remaining wiring layers as they are fabricated. Fabricating ground plane 19 last also provides an electrical shield for the x and y wiring layers in the decal from the chips which are subsequently attached thereto. The shield prevents return currents from being set up in the semiconductor chips, resulting in slow wave propagation of the signals due to the imperfect dielectric or conductive properties of the semiconductor.
  • a thin clear inorganic layer such as silicon nitride (not shown) may be formed and patterned between substrate 10 and first wiring layer 16, to act as a prepatterned lithography layer for the final chip-to-decal-electrical connections or reach-through-vias.
  • a first integrated circuit chip 25a is aligned and mechanically attached to the thin film decal 15. It will be understood by those having skill in the art that integrated circuit chip 25a may be a custom-designed or conventional off-the-shelf integrated circuit chip having a plurality of interconnection pads at the top surface thereof, one of which is illustrated at 26a.
  • Substrate 10 is rotated 180° from the position shown in Figure 2A and is placed over integrated circuit chip 25a.
  • a surface attachment layer 27 is formed on the top surface of chip 25a.
  • Surface attachment layer 27 preferably comprises an adhesion promoter, for example X-amino-propyl-diethoxysiloxane marketed under the designation A-1100 by Petrach Company, on the surface of chip 35a.
  • a very thin (e.g. 1000 A) coating of permanent curable dielectric polyimide (for example DuPont 2525) is formed on the adhesion promotor.
  • a thick coating of soluble polyimide, for example XU-218 manufactured by Ciba Geigy is formed on the permanent polyimide layer.
  • a solvent for example n-methyl-pyrollidinone (NMP) may be applied to the soluble polyimide layer to soften the layer.
  • NMP n-methyl-pyrollidinone
  • the last formed polyimide layer in decal 15 be of a soluble polyimide.
  • a microscope or other conventional alignment tool for example a model MA56 contact printer manufactured by Karl-Sues, Kunststoff, Germany, may be employed to align the pads 26a or other alignment marks on integrated circuit chip 25a with wiring layers 16-19 (through windows in the ground plane) , or other alignment marks (for example in the ground plane) formed in thin film decal 15.
  • Conventional alignment tools may be employed to align chip 25a to decal 15 to within a l ⁇ m tolerance.
  • decal 15 is pressed down onto chip 25 to attach the two structures as shown in Figure 2C.
  • a combination of heat, ultraviolet radiation, vacuum and/or pressure may be employed to remove the residual solvent and harden the soluble polyimide so that chip 25a is firmly attached to decal 15 in an aligned position.
  • second and third chips 25b and 25c having connector pads 26b and 26c, respectively thereon are also aligned and attached to thin film decal 15.
  • chips 25 are "re-integrated” to thin film decal 15 using individual alignment so that alignment tolerances are maintained over the length of thin film decal 15. It will be understood by those having skill in the art that discrete components such as resistors or capacitors may also be “re-integrated” to this film decal 15.
  • a support ring 33 is attached to thin film decal 15 surrounding chips 25.
  • Support ring 33 may be attached using the chip attach techniques described above. After all the chips 25 and support ring 33 are attached, the polyimide 20 may be further cured by heating at 230"C for 30 minutes.
  • support ring 33 may be a simple low expansion ceramic, or metal (for example Invar Alloy 42) or other solid material. Ring 33 need not be the same thickness as chips 25, nor need it be on the same side of decal 15 as chips 25. Complex support rings which include internal capacitors, terminating resistors, internal feed through or wiring layers, internal chips or other active devices, and/or external pad or pin connectors may also be employed. Substrate 10 is then removed, leaving the thin film decal 15 as the sole means of support for chips 25. Many techniques may be employed for removing substrate 10. In one technique, a channel 34 (Fig. 2D) is etched through thin film decal 15 outside support ring 33 down to .the surface of the support substrate 10.
  • a channel 34 Fig. 2D
  • BHF buffered hydrofluoric acid
  • a plurality of reach- through vias 21 are selectively formed between the appropriate internal wiring layers 16-19 and the appropriate pads 26 on chips 25.
  • Reach through vias 21 may be formed using modified (deep) known techniques for forming internal vias between wiring layers of chip metallization, some of which will be described below in connection with Figure 6.
  • Vias 21 are "reach-through” vias in that they are formed from a wiring layer in decal 15 to contact the chip pads through the decal. The vias thereby reach through an existing metal and dielectric stack. It will be noted that reach through vias 21 connect the side of the wiring layer which is opposite chips 25, to pads 26. Reach-through-vias from the opposite side of a wiring layer have not heretofore been employed for chip connections.
  • the structure of the present invention includes thin film decal 15 having at least one wiring layer therein and a support ring 33 attached to the decal for maintaining the decal under tension inside the support ring. At least one integrated circuit chip 25 is attached to the decal inside the support ring in alignment with the decal. A plurality of vias 21 form electrical connections between the wiring layers of the decal and the integrated circuit chips.
  • both faces of the extended integration structure may be used for next level package considerations, such as input/output connection and thermal management.
  • solder bumps may be employed on the exposed surface of decal 15 or on the support ring 33 or both.
  • Thermally conductive pistons may be placed adjacent the backs of the chips.
  • Metal foil may be brazed to the ring 33 to hermetically seal off the front and back of the assembly.
  • Other known connection techniques like tape automated bonding or wire bonding may be employed.
  • the extended integration structure may be mounted on a still larger extended integration structure using decal-to-decal connection. Alternatively, further metal wiring layers may be formed on the decal 15.
  • the extended integration structure may be treated like a very large integrated circuit chip for next level packaging considerations. It should be noted, however, that for next level packaging consideration, the extended integration structure of the present invention is superior to a similarly sized monolithic chip (if such a chip could be made) because stress is relieved at the joints of the separate chips. In contrast, a very large silicon chip would possess large internal stresses, when mounted in a package.
  • the structure of the present invention also facilitates the replacement of a defective chip without discarding the entire structure. If a chip is found to be defective prior to final cure, the reach-through vias 21 connecting the defective chip to the substrate may be removed. To facilitate reach-through via removal, the reach-through vias may be formed of a different metal than the internal wiring layers.
  • the vias may be aluminum.
  • the aluminum vias may be removed with an etchant, for example phosphoric/nitric acid, which will not attack copper or polyimide.
  • the bond between the decal and chip may be dissolved, and a new chip may be substituted therefor. Prior to dissolving the bond, the defective chip must be isolated from the remaining chips so that the bond between functional chips and the decal is not dissolved.
  • the thickness of the layers shown in Figures 1 and 2 have been greatly exaggerated in order to illustrate the details of the thin film decal 15. In order to provide a better perspective of the relative dimensions in the extended integration structure of the present invention.
  • FIG 3 illustrates top and side views of a four chip extended integration structure.
  • the extended integration structure comprises four chips 25 and support ring 33 all mounted on thin film decal 15.
  • the chips 25 may be 8mm square with the gap between adjacent chips being on the order of 0.5mm.
  • the gap between the chips 25 and support ring 33 may be on the order of 0.5 to several millimeters while the support ring 33 may be several millimeters wide.
  • the total package may be 22-25mm on a side.
  • the thickness of the chips 25 and support ring 33 may be on the order of 0.5mm, while the total thickness of the thin film decal 15 may be on the order of 15 ⁇ m.
  • An optional foil hermetic seal 23 is also shown attached to support ring 33.
  • Figure 4 illustrates the fabrication of one nine-chip structure, four four-chip structures and four single-chip structures, each surrounded by a support ring 33 and fabricated on a single support substrate 10 according to the present invention.
  • support substrate 10 may be a conventional lOO m glass substrate.
  • the plurality of extended integration structures may be separated into individual extended integration structures by cutting the thin film decal outside the support rings 33.
  • Figure 5 four techniques for forming internal thin film wiring layers of decal 15 are shown. It will be understood by those having skill in the art that other conventional metal patterning processes may be employed to form the thin film wiring layers.
  • Figures 5A and 5B illustrate subtractive processes for forming patterned metal layers
  • Figures 5C and 5D illustrate additive processes for forming metal layers
  • Figure 5A illustrates a wet etch subtractive process using phosphoric/nitric acid to pattern aluminum layer 37 using a patterned layer of photoresist 38
  • Figure 5B illustrates the use of a dry etch or reactive ion etch using Cl 2 BC1 3 or SiCl 4 to etch metal layer 39 through patterned photoresist mask 40.
  • Figure 5C illustrates an additive plating process in which metal layers (copper) 41 are plated on an underlying metal layer using a mask 42 of photoresist.
  • Figure 5D illustrates liftoff processes in which liftoff underlayer 43 and mask layer 44 are defined and a discontinuous metal layer 45a, b is deposited by evaporation. The underlayer 43 is then dissolved, removing the unwanted portion of metal layer 45a thereon, with metal layer 45b remaining.
  • the liftoff method of Figure 5D is preferred because better quality copper metal may be obtained then by the plating method of Figure 5C, with a higher aspect ratio (height/width) then may be achieved by the wet etching process of Figure 5A.
  • the dry etch method of Figure 5B is not preferred for copper, as the etch product is not volatile at reasonable temperatures. It will be understood by those having skill in the art that other conventional thin film metal patterning processes may also be employed.
  • Figure 6 a number of techniques for forming reach-through vias 21 for connecting metal wiring layers 16-19 to the connector pads 26 of integrated circuit chip 25 (Figure 2E) are illustrated. Several of these methods need not be described and illustrated in detail because they are variations of techniques well known to those having skill in the art for chip metallization and decal fabrication. However, it should be noted that these techniques have not heretofore been employed to connect the side of a wiring layer opposite a chip, to the chip pad.
  • Figure 6A illustrates a reach-through via 21 formed using conventional metallization techniques. A sloped via is first etched into the dielectric 20 which is patterned with thick photoresist. Metal 21 is then evaporated or sputtered into the via creating an electrical contact.
  • FIG. 6B illustrates a reach-through via 21 which may be "pre” formed as part of the lithography steps of one of the internal wiring layers.
  • Figure 6C illustrates a "lost wax" reach-through via 21 formed by building up metal layers during the fabrication of each internal wiring layer of thin film decal 15. The built up metal is selectively etched leaving a hole in the dielectric. This thins the dielectric. A final short etch is all that is required to complete the cavity. The metal 21 may then be applied as described in
  • Figure 6D illustrates a reach-through via 21 in the form of a plug or stud, fabricated using other "lost wax" techniques.
  • a plug 21 may be formed from the bottom side (as illustrated) .
  • the plug may be removed by etching as described in connection with Figure 6C and the via completed as described in Figure 6C.
  • the plug 21 may be a contiguous raised area of substrate 10.
  • the surface needs to be planarized prior to chip attach due to build up of polyimide over the plug during processing.
  • a via would be automatically formed as the molded cavity which corresponded to the raised area would be left in place upon the decal removal step.
  • Figure 6E illustrates a reach-through via from an intermediate layer to pad 26 which may be formed by removing an area around the pad 26 and depositing solder in the removed area. This may be accomplished by dipping in molten solder thereby wetting the exposed Cu lines and gold chip pads 26.
  • Figure 6F illustrates the use of a liftoff technique to form a central target followed by solder deposit to form vias 21. The solder is deposited through a liftoff mask. The solder is then melted to cause it-to flow. The solder 21 is shown in Figure 6F after evaporation but prior to melting.
  • Figure 6G illustrates the formation of a deep stud or post via 21 followed by further contact pattern metallization layer 22. A deep post 21 is formed in an etched hole by evaporation so that it is higher than the surface. The surface is then polished or milled so that the post surface is perfectly planarized. Contact 22 is then completed by an additional metal step.
  • Figure 7 illustrates detailed top and side views ( Figures 7A and 7B respectively) of the liftoff vias 21 described in Figure 6B.
  • a metal or preferably a thermally stable, optically transparent, thin (e.g. 2000A) dielectric layer 50 e.g. silicon nitride or silicon containing polyimide
  • RIE oxygen Reactive Ion Etch
  • Layers 16 through 18 are sequentially fabricated and optically tested as was described in connection with Figure 2A.
  • Layer 18 is then overcoated with polyimide dielectric and a second, (thinner than the first layer 50, e.g. 1000A) inert dielectric layer 53 is then deposited. Openings 54a, 54b are patterned corresponding to the chip pads 26 and electrically isolated traces 55 (not at ground) which are to be formed in the next metal layer which is the ground plane level 19.
  • a thin polymer dielectric layer 56 is then applied. Via holes 57 are patterned and etched from the location of traces 55 to be formed in the ground layer 19 to conductor lines in layer 18. Ground layer 19 is then formed. An electrically conductive path by means of the ground layer metal step from the proximity of the chip pads 26 to conductive layer 18 is thereby formed. 093
  • Substrate 10 is then removed by the adhesion failure method previously described.
  • the assembly is then etched by means of oxygen RIE, with the process conditions being dynamically altered during the entire course of the etch.
  • the etch is first performed under anisotropic conditions to clear the first surface unpatterned layer 11 and cut into the body of the dielectric through the prepatterned openings 51 in layer 50.
  • the RIE conditions are slowly changed during the course of the etch from initially anisotropic (vertical profile sidewalls etched in the polyimide) to isotropic (undercut profile sidewalls) , as indicated at 61. This is accomplished by changing the pressure and cathode bias in the etch tool.
  • the etch proceeds to etch the polyimide with a pattern corresponding to openings 51 until the inert layer 53 is reached. At this time the RIE conditions are fully isotropic. The etch is stopped by the inert layer except through openings 54a, 54b in inert layer 53. The isotropic conditions cause the polyimide to be etched in such a fashion so that the openings 54a, 54b are undercut. The sidewalls of the polyimide etched under openings 54a, 54b will thereby have gently sloped angles.
  • the RIE conditions are chosen as such so that good metal step coverage will be realized for conductor line 21 without the problem of undercutting opening 51 to a deleterious extent.
  • a fluorine containing gas e.g. SF6 or CF4
  • SF6 or CF4 fluorine containing gas
  • Metal is then evaporated into the overhung cavity forming electrical contact 21 between chip pads 26 and metal trace 55. Electrical contact is thereby established from chips 25 to decal conductor layer 18.
  • a second upper ground or power plane 60 is simultaneously fabricated during this last evaporation.
  • It may be fabricated to electrically contact with lines in layer 16 by creating openings 57 in inert layer 50 over subsequently processed metal pads 58 of layer 16 which were stepped down to just above the level of inert layer 50 by means of vias 59 during the first metal step.
  • the method described in Figure 7 is preferred for creating decal to chip contacts as it does not require a lithography step following mechanical chip attachment and because the vertical distance between chip pad and package contact is minimized which allows for a higher area density of contacts to be made.
  • Figure 7A also illustrates a reduced capacitance internal wiring line 18.
  • the internal wiring layers of decal 15 may be formed of a ladder structure illustrated in Figure 7A.
  • the ladder structure has less capacitance than a solid metal line of the same width.
  • the "rungs" 46 of the ladder form links , around open circuits in siderails 47, thus improving the yield.
  • the yields expected of a wide line may be achieved, with the decreased capacitance that would be expected of a narrow line.
  • Ladder lines may be employed in any thin film metallization, for example for chip metallization or decal metallization, where decreased capacitance is desired.
  • FIG. 8 it will be seen that a single chip 25 and a single mounting ring 33 are employed to redistribute the contacts 26 from chip 25 to form a new input/output (I/O) pattern.
  • the I/O contacts for conventional chip dies are ordinarily arranged for simplest wiring to the periphery of the integrated circuit chip itself, while a system designer usually desires a different wiring pattern.
  • the extended integration structure may re-orient the fanin/fanout distribution of the chip contacts to form a new chip package having the desired pattern.
  • an arbitrary size extended integration structure is formed, in a simple and low cost manner, using conventional tools and processes.
  • the extended integration structure of the present invention eliminates the need to use larger and larger chips in an attempt to overcome packaging limitations. Accordingly, it may be foreseen that the present invention will lead to the use of smaller higher yielding chip dies, with the extended integration package including a larger part of the metallization.
  • large size chips may also be employed, and even wafer size chips may be employed. In a wafer scale integration application the wafer itself may form the support ring.
  • the present invention will satisfy current demands and will extend far into the future as the Input/Output pad size is on the order of microns (vs the order of mils for wirebonding, solder bumps and tape automated bonding techniques) so that the total number of connections may be made very large (on the order of thousands) for present day state of the art chip size (about 8 mm square) .

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Une structure semi-conductrice à intégration poussée, peu onéreuse, légère, rapide, dense et fiable est réalisée par la formation d'une décalcomanie de câblage multicouche (15) à couche mince sur un substrat de support et par l'alignement et la fixation, sur la décalcomanie, d'une ou de plusieurs puces intégrées. Un anneau de support (33) est fixé à la décalcomanie entourant le substrat intégré aligné et fixé, et le substrat de support est enlevé. Des interconnexions traversantes relient la décalcomanie de câblage aux puces.
PCT/US1990/000069 1989-01-25 1990-01-10 Structure semi-conductrice a integration poussee et procede pour sa fabrication Ceased WO1990009093A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/301,792 US5059290A (en) 1988-01-29 1989-01-25 Electroanalytical method
US301,792 1989-01-25

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GB2274200A (en) * 1991-10-29 1994-07-13 Gen Electric A High density interconnect structure including a spacer structure and a gap
EP0662709A3 (fr) * 1994-01-11 1996-03-20 Siemens Ag Méthode de test de couches de circuit semi-conducteur.
WO2003075344A3 (fr) * 2002-02-28 2003-12-18 Motorola Inc Procede de traitement de multiples dispositifs a semi-conducteurs pour essai
WO2004051737A3 (fr) * 2002-11-27 2005-02-24 Advanced Micro Devices Inc Procede de fabrication en deux parties de circuits a semi-conducteurs
US7138295B2 (en) 1997-04-04 2006-11-21 Elm Technology Corporation Method of information processing using three dimensional integrated circuits
US7176545B2 (en) 1992-04-08 2007-02-13 Elm Technology Corporation Apparatus and methods for maskless pattern generation
US7307020B2 (en) 1992-04-08 2007-12-11 Elm Technology Corporation Membrane 3D IC fabrication
US7507638B2 (en) 2004-06-30 2009-03-24 Freescale Semiconductor, Inc. Ultra-thin die and method of fabricating same
WO2013116167A1 (fr) * 2012-02-02 2013-08-08 Harris Corporation Procédé de fabrication de tranche redistribuée à l'aide de couches de redistribution pouvant être transférées
WO2013116168A1 (fr) * 2012-02-02 2013-08-08 Harris Corporation Procédé de fabrication d'un dispositif électronique redistribué au moyen d'une couche de redistribution pouvant être transférée

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US5403700A (en) * 1990-02-14 1995-04-04 Eli Lilly And Company Method of making a thin film electrical component
EP0442674A3 (en) * 1990-02-14 1992-02-26 Eli Lilly And Company Thin film electrical component
GB2274200B (en) * 1991-10-29 1996-03-20 Gen Electric A high density interconnect structure including a spacer structure and a gap
GB2274200A (en) * 1991-10-29 1994-07-13 Gen Electric A High density interconnect structure including a spacer structure and a gap
US7385835B2 (en) 1992-04-08 2008-06-10 Elm Technology Corporation Membrane 3D IC fabrication
US7479694B2 (en) 1992-04-08 2009-01-20 Elm Technology Corporation Membrane 3D IC fabrication
US7615837B2 (en) 1992-04-08 2009-11-10 Taiwan Semiconductor Manufacturing Company Lithography device for semiconductor circuit pattern generation
US7550805B2 (en) 1992-04-08 2009-06-23 Elm Technology Corporation Stress-controlled dielectric integrated circuit
US7485571B2 (en) 1992-04-08 2009-02-03 Elm Technology Corporation Method of making an integrated circuit
US7307020B2 (en) 1992-04-08 2007-12-11 Elm Technology Corporation Membrane 3D IC fabrication
US7176545B2 (en) 1992-04-08 2007-02-13 Elm Technology Corporation Apparatus and methods for maskless pattern generation
US7242012B2 (en) 1992-04-08 2007-07-10 Elm Technology Corporation Lithography device for semiconductor circuit pattern generator
US7223696B2 (en) 1992-04-08 2007-05-29 Elm Technology Corporation Methods for maskless lithography
US5610531A (en) * 1994-01-11 1997-03-11 Siemens Aktiengesellschaft Testing method for semiconductor circuit levels
EP0662709A3 (fr) * 1994-01-11 1996-03-20 Siemens Ag Méthode de test de couches de circuit semi-conducteur.
US8928119B2 (en) 1997-04-04 2015-01-06 Glenn J. Leedy Three dimensional structure memory
US7138295B2 (en) 1997-04-04 2006-11-21 Elm Technology Corporation Method of information processing using three dimensional integrated circuits
US8841778B2 (en) 1997-04-04 2014-09-23 Glenn J Leedy Three dimensional memory structure
US7474004B2 (en) 1997-04-04 2009-01-06 Elm Technology Corporation Three dimensional structure memory
US7504732B2 (en) 1997-04-04 2009-03-17 Elm Technology Corporation Three dimensional structure memory
US8907499B2 (en) 1997-04-04 2014-12-09 Glenn J Leedy Three dimensional structure memory
US8933570B2 (en) 1997-04-04 2015-01-13 Elm Technology Corp. Three dimensional structure memory
US9401183B2 (en) 1997-04-04 2016-07-26 Glenn J. Leedy Stacked integrated memory device
US6905891B2 (en) 2002-02-28 2005-06-14 Frrescale Semiconductor, Inc. Method for processing multiple semiconductor devices for test
WO2003075344A3 (fr) * 2002-02-28 2003-12-18 Motorola Inc Procede de traitement de multiples dispositifs a semi-conducteurs pour essai
US7195931B2 (en) 2002-11-27 2007-03-27 Advanced Micro Devices, Inc. Split manufacturing method for advanced semiconductor circuits
WO2004051737A3 (fr) * 2002-11-27 2005-02-24 Advanced Micro Devices Inc Procede de fabrication en deux parties de circuits a semi-conducteurs
US8198705B2 (en) 2004-06-30 2012-06-12 Freescale Semiconductor, Inc. Ultra-thin die and method of fabricating same
US7507638B2 (en) 2004-06-30 2009-03-24 Freescale Semiconductor, Inc. Ultra-thin die and method of fabricating same
WO2013116167A1 (fr) * 2012-02-02 2013-08-08 Harris Corporation Procédé de fabrication de tranche redistribuée à l'aide de couches de redistribution pouvant être transférées
WO2013116168A1 (fr) * 2012-02-02 2013-08-08 Harris Corporation Procédé de fabrication d'un dispositif électronique redistribué au moyen d'une couche de redistribution pouvant être transférée
US8685761B2 (en) 2012-02-02 2014-04-01 Harris Corporation Method for making a redistributed electronic device using a transferrable redistribution layer
US8772058B2 (en) 2012-02-02 2014-07-08 Harris Corporation Method for making a redistributed wafer using transferrable redistribution layers
KR101495014B1 (ko) 2012-02-02 2015-02-23 해리스 코포레이션 이동가능한 재배치층을 이용하여 재배치된 전자 디바이스의 제조방법

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