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WO1990008362A3 - Method for analyzing datapath elements - Google Patents

Method for analyzing datapath elements Download PDF

Info

Publication number
WO1990008362A3
WO1990008362A3 PCT/US1990/000266 US9000266W WO9008362A3 WO 1990008362 A3 WO1990008362 A3 WO 1990008362A3 US 9000266 W US9000266 W US 9000266W WO 9008362 A3 WO9008362 A3 WO 9008362A3
Authority
WO
WIPO (PCT)
Prior art keywords
stage
datapath
analyzing
delays
datapath elements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US1990/000266
Other languages
French (fr)
Other versions
WO1990008362A2 (en
Inventor
Creighton Satoshi Asato
Suresh Kishorbhai Dholakia
Christoph Ditzen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Philips Semiconductors Inc
Original Assignee
VLSI Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by VLSI Technology Inc filed Critical VLSI Technology Inc
Publication of WO1990008362A2 publication Critical patent/WO1990008362A2/en
Publication of WO1990008362A3 publication Critical patent/WO1990008362A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3875—Pipelining a single stage, e.g. superpipelining
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Noise Elimination (AREA)
  • Position Fixing By Use Of Radio Waves (AREA)
  • Monitoring And Testing Of Transmission In General (AREA)
  • Complex Calculations (AREA)

Abstract

According to a technique for determining delays through multi-stage datapath elements, estimates of the delays through each stage of the datapath element are computed in accordance with an equation such as: Ds=DbNb+C; where Ds is the estimated stage delay, Db is a delay associated with communication between bits in the stage, Nb is the number of bits in the datapath element, and C is a constant. The estimated stage delays are used to determine positions of pipelining stages in the datapath element.
PCT/US1990/000266 1989-01-13 1990-01-12 Method for analyzing datapath elements Ceased WO1990008362A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US29705789A 1989-01-13 1989-01-13
US297,057 1989-01-13

Publications (2)

Publication Number Publication Date
WO1990008362A2 WO1990008362A2 (en) 1990-07-26
WO1990008362A3 true WO1990008362A3 (en) 1990-09-07

Family

ID=23144674

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1990/000266 Ceased WO1990008362A2 (en) 1989-01-13 1990-01-12 Method for analyzing datapath elements

Country Status (4)

Country Link
JP (1) JPH04502677A (en)
DE (1) DE4090021T (en)
GB (1) GB2244829B (en)
WO (1) WO1990008362A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5519626A (en) * 1993-07-09 1996-05-21 Hewlett-Packard Company Method of dividing a pipelined stage into two stages in a computer-aided design system
JPH07141148A (en) * 1993-11-16 1995-06-02 Kanebo Ltd Pipeline parallel multiplier
US9110689B2 (en) * 2012-11-19 2015-08-18 Qualcomm Technologies, Inc. Automatic pipeline stage insertion

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3875391A (en) * 1973-11-02 1975-04-01 Raytheon Co Pipeline signal processor
US4263651A (en) * 1979-05-21 1981-04-21 International Business Machines Corporation Method for determining the characteristics of a logic block graph diagram to provide an indication of path delays between the blocks
US4549280A (en) * 1982-12-20 1985-10-22 Sperry Corporation Apparatus for creating a multiplication pipeline of arbitrary size
US4736333A (en) * 1983-08-15 1988-04-05 California Institute Of Technology Electronic musical instrument
US4799182A (en) * 1984-10-16 1989-01-17 The Commonwealth Of Australia Cellular floating-point serial pipelined multiplier
JPS61114338A (en) * 1984-11-09 1986-06-02 Hitachi Ltd multiplier
US4736335A (en) * 1984-11-13 1988-04-05 Zoran Corporation Multiplier-accumulator circuit using latched sums and carries
US4698760A (en) * 1985-06-06 1987-10-06 International Business Machines Method of optimizing signal timing delays and power consumption in LSI circuits
US4827428A (en) * 1985-11-15 1989-05-02 American Telephone And Telegraph Company, At&T Bell Laboratories Transistor sizing system for integrated circuits
US4811260A (en) * 1986-11-13 1989-03-07 Fujitsu Limited Signal processing circuit

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
IEEE Transactions on Computers, Vol. C-27, No. 9, September 1978, IEEE, J.R. JUMP et al.: "Effective Pipelining of Digital Systems", pages 855-865 see page 856, column 2, lines 46-49; page 857, column 1, lines 8-10; page 859, column 1, line 31 - column 2, line 20; figures 1,3 *
Proc. IEEE International Conference on Acoustics, Speech and Signal Processing, Tampa, Florida, 26-29 March 1985, Vol. 4, IEEE, C.E. HAUCK et al.: "The Systematic Exploration of Pipelined Array Multiplier Performance", pages 1461-1464 see page 1462, column 1, lines 51-62; page 1462, column 2, lines 30-36; figures 1-5 *
Proc. of the Custom Integrated Circuits Conference, San Diego, 15-18 May 1989, IEEE, (New York, US), C. ASATO et al.: "A Datapath Multiplier with Automatic Insertion of Pipeline Stages", pages 23.2.1-23.2.4 see the whole article *

Also Published As

Publication number Publication date
GB2244829A (en) 1991-12-11
JPH04502677A (en) 1992-05-14
WO1990008362A2 (en) 1990-07-26
GB9114332D0 (en) 1991-09-04
GB2244829B (en) 1993-01-13
DE4090021T (en) 1991-11-21

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