WO1990006595A1

WO1990006595A1 - Ultrathin submicron mosfet with intrinsic channel

Info

Publication number: WO1990006595A1
Application number: PCT/US1989/005327
Authority: WO
Inventors: Kyle W. Terrill; Prahalad K. Vasudev
Original assignee: Hughes Aircraft Co
Current assignee: Raytheon Co
Priority date: 1988-12-09
Filing date: 1989-11-27
Publication date: 1990-06-14
Anticipated expiration: 1991-06-09
Also published as: JPH03503227A; EP0401356A1

Abstract

A submicron MOSFET is fabricated on an ultrathin layer (16) with a generally intrinsic channel (14) having a dopant concentration less than about 1016cm-3. The channel (14) thickness is preferably not greater than about 0.2 micron; the ratio of channel thickness to length is less than about 1:4, and preferably not greater than about 1:2. Punchthrough and other short-channel effects are inhibited by the application of an appropriate backgate voltage, which may also be varied to adjust the voltage threshold.

Description

ULTRATHIN SUBMICRON MOSFET WITH INTRINSIC CHANNEL

BACKGROUND OF THE INVENTION Field of the Invention

This invention relates to semiconductor transistor devices, and more particularly to submicron metal-oxide- semiconductor field effect transistors (MOSFETs) , fabricated in ultra-thin silicon film.

Description of the Related Art

New techniques such as SIMOX (separation by im- planted oxygen) layers have recently been developed for fabricating high quality thin silicon films on buried oxides. For example, see the article by the present inventors together with S. Seymour, "A High Performance Submicrometer CMOS/SOI Technology Using Ultrathin Silicon Films on SIMOX", 1988 VLSI Technology Symposium Tech. Digest. This technique has been used to improve radiation hardness and to promote volume inversion. An example of such a device is given in a published letter by Tsao et al., "Gate Coupling and Floating-Body Effects in Thin-Film SOI MOSFETs", Electronics Letters. February 18, 1988, Vol. 24, No. 4, pages 238-39 ("SOI" refers to silicon-on-insulator) . This letter discloses the fabrication of long channel (channel length of about 3 microns) n-channel MOSFETs with a thin silicon film 0.13 micron thick and channel doping concentration of 2xl0¹⁶/cm^~3. Typical ultrathin MOSFET designs with channel lengths below 1 micron require high dopant densities in the channel region to prevent device punchthrough. Punchthrough occurs when electric field lines from the drain extend toward the source and reduce the potential barrier height. This effect is normally prevented by sufficiently doping the channel so that the source is shielded from the drain by a space-charge region. For submicron devices the required dopant density substan- tially exceeds 10¹⁶cm^"3, and can be as large as 10¹⁷cm^"3. This level of channel doping has also been found to be useful in preventing short-channel effects, principally a threshold roll-off effect in which the device's voltage threshold falls off as the channel length is reduced. Another short channel effect overcome by doping the channel in this manner is a degradation in the sub-threshold current-voltage characteristic as the channel length is reduced, which is reflected by a reduction in turn-off performance. However, in addition to requiring the fabrication step of a channel implant, these devices are somewhat limited in terms of electron mobility and transconductance. Due to their subthresh- old characteristics they also do not turn off as rapidly as might be desired.-

SUMMARY OF THE INVENTION

In view of the above problems, the present inven¬ tion seeks to provide an ultrathin MOSFET with submicro- eter channel lengths that avoids punchthrough and other short-channel effects encountered in conventional bulk MOSFETs, but in addition has excellent turn-off, sub- threshold and transconductance characteristics.

Another goal is to provide a new type of ultrathin MOSFET in which the threshold voltage can be selected and adjusted by an appropriate selection of a bias voltage level, independent of channel doping.

The present invention achieves these goals by means of an ultrathin MOSFET in which the channel region is generally intrinsic, rather than heavily doped. Punch- through and short-channel effects are inhibited by using a very thin silicon film and applying a selectable back¬ gate bias voltage, rather than by doping the channel. With a channel dopant concentration less than about 10¹⁶cm^-3, these results are achieved if the ratio of the channel thickness to its length is kept less than about 1:2, and preferably no greater than about 1:4. The absolute value of channel thickness is preferably less than about 0.2 microns.

The device is formed in an SOI configuration, preferably upon a buried oxide layer, which in turn is provided on a bulk semiconductor substrate. The voltage threshold for the device can be set and adjusted by applying a suitable back-gate voltage to the substrate. The resulting MOSFET avoids punchthrough and short- channel effects, and otherwise has improved operating characteristics compared to prior MOSFETs with heavily doped channels.

These and other features and advantages of the invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings, in which:

DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional diagram of a MOSFET constructed in accordance with the present invention;

FIG. 2 is a cross-sectional diagram of a pair of such MOSFETs arranged in a CMOS configuration;

FIGs. 3 and 4 are plots of electric potential for devices with channel dopings of 10¹⁶cm~³ and lθ"cm^"3, respectively; FIG. 5 is a graph plotting the calculated minimum channel length as a function of semiconductor film thickness;

FIG. 6 is a graph illustrating the sub-threshold I-V characteristics of a device formed according to the invention for various back-gate bias voltages;

FIG. 7 is a graph plotting drain current (gain) and transconductance as a function of gate voltage for two difference values of drain voltage; and F Gs. 8 and 9 are graphs illustrating the temper¬ ature dependence of the transconductance and output characteristics, respectively, for a device constructed in accordance with the invention.

DETAILED DESCRIPTION OF THE INVENTION

A cross-sectional view of a mesa isolated n-channel MOSFET constructed in accordance with the invention is shown in FIG. 1. The invention is equally applicable to p-channel devices, in which the doping of the source and drain and the polarity of the bias voltages would be reversed. The device shown in FIG. l can be implemented with conventional fabrication techniques. It consists of an ultrathin (generally less than a half micron) layer of semiconductor material 2 fabricated on a buried insulator layer 4. Silicon is preferred for the semi¬ conductor material because fabrication is relatively easy, but other semiconductor materials could also be used. The buried insulator layer 4 is preferably an oxide, but other insulating materials such as nitrides could also be used. The SIMOX (separation by implanted oxygen) technique is preferably employed for the fabri¬ cations.

Oxide layer 4 is formed on a bulk silicon or other semiconductor wafer 6, which carries a back-gate elec- trode 8 on its opposite side. Electrode 8 is formed from a conductive material such as metal or heavily doped semiconductor, and receives a back-gate bias voltage which sets the operating characteristics of the device. Spaced regions of semiconductor layer 2 are heavily doped to form a drain region 10 and source region 12. The intermediate portion of the semiconductor layer which extends between the drain and source forms a channel region 14. This region is generally intrinsic, meaning that it is only lightly doped. Bulk silicon normally comes with a certain level of dopants, but these are impurities rather than deliberately intro¬ duced. The dopant impurity concentration in bulk silicon is typically on the order of lθ"cm^'3, and sometimes more. The present invention will work with either undoped bulk silicon for the channel region, or with a generally low level of channel doping consider¬ ably less than channel dopings previously employed. The channel region may be regarded as "generally intrinsic", which for purposes of the invention is defined as ranging from a bulk semiconductor dopant impurity level on the order of 10¹⁴cm^"3 or less through a level no greater than about lθ¹⁶cm^"3.

A thin oxide layer 16 is provided over the channel region 14 (in practice this oxide layer will normally extend over the entire device) . The insulating oxide layer 16 is surmounted by a polysilicon gate 18 in alignment with the channel region.

It has been discovered that a device of this type can be designed to operate without punchthrough or short-channel effects. These phenomena are prevented by the application of a bias voltage to the back-gate 8, which tends to accumulate charged carriers at the interface between the semiconductor channel region 14 and the buried oxide layer 4. The applied back-gate bias produces an electric field which induces charged carriers in the channel region without having to intro¬ duce dopants into the channel. The carriers and elec¬ tric field induced by the back-gate bias voltage have been found to effectively prevent punchthrough and short-channel effects.

The achievement of proper operation has been found to be dependent upon the absolute channel thickness as well as the ratio of channel thickness to channel length. While submicron channel thicknesses in general are permissible, it is preferred that the channel be not more than about 0.2 microns thick. The ratio of channel thickness to length should be less than 1:2, and prefer¬ ably not more than 1:4. The buried oxide layer 4 is preferably about 0.3-0.5 microns thick and the gate insulating layer 16 about 0.012 microns thick, although both elements can vary from these dimensions.

In one n-channel implementation of the invention, MOSFETs were fabricated on ultra-shallow SOI material with a silicon film thickness of about 0.2 microns. The channel doping in these films was determined by the bulk doping concentration of about 5xl0¹⁵cm^"3. While this channel doping concentration was over an order of magnitude less than the concentration generally required to prevent punchthrough and short-channel effects in submicron MOSFETs, fully functional devices were ob¬ tained by the application of a -15 volt back-gate bias. N-channel MOSFETs with more conventional (much higher) channel implants were fabricated on the same wafer. When the two types of devices were compared, it was found that the devices formed in accordance with the invention with generally intrinsic channels showed an increase in electron mobility of over 100 cm²/vs. The sub-threshold slope factor S (mv/decade) was also reduced by about 10 v/ decade in the unimplanted device, resulting in an improved turn-off characterist¬ ic.

The invention is applicable to various circuit configurations. A CMOS example is illustrated in FIG. 2. An n-channel device 20 is shown on the left hand^" side of the structure, with a p-channel device 22 on the right hand side. Both devices are constructed in a manner similar to that shown in FIG. 1, with the ele¬ ments of n-channel MOSFET 20 identified by the letter A and those of p-channel MOSFET 22 identified by the letter B. Back-gate voltages of opposite polarity are applied to their respective substrates 6A and 6B. To provide further isolation between the two devices, they are fabricated on an additional oxide layer 24, which in turn is carried by a semiconductor substrate 26.

The mechanism by which punchthrough is prevented is illustrated in FIGs. 3 and 4. FIG. 3 shows an electric potential plot for a MOSFET formed with a 0.1 micron thick silicon film 28 on a 0.35 micron thick buried oxide layer 30. Source 32, drain 34 and channel 36 regions are formed in silicon film 28. In FIG. 3 the channel doping was 10¹⁶cm^~3, while in FIG. 4 the channel was nearly intrinsic (about 10¹⁴cm^"3) . A back-gate bias of -2 volts was used for a simulation of both n-channel devices. In FIG. 3, with a channel doping less than that required by prior submicron MOSFETs, it can be seen that the equal potential lines are deflected out of the channel area. Since the electric field lines are normal to the lines of equal potential, this means that the electric field lines are progressively deflected out of the channel area and do not extend all the way from the drain to the source. Accordingly, punchthrough is pre¬ vented. FIG. 4 shows that, although the field lines emanating from the source and drain approach somewhat more closely with a channel region that is more nearly true intrinsic, punchthrough still does not occur.

FIG. 5 shows the results of an analytical model that was developed to predict the scalability of fully depleted and near-intrinsic MOSFETs fabricated on ultrathin SIMOX films. The analysis proceeded by plotting the minimum channel length as a function of SOI ilm thickness for both fully depleted and near-intrin¬ sic (about lθ"cm^"3) MOSFETs. The results are for a uniform channel dopant distribution as a function of depth. The level of channel doping in the near-intrin¬ sic device was too low to provide any significant punchthrough protection. Punchthrough was inhibited by the electric field lines from the drain fringing toward both the top and bottom gates, rather than reaching the source; this effect was a result of the applied back¬ gate bias, which was -5 volts in the analysis.

For an increasing SOI thickness (the thickness of the silicon film which includes the channel) , FIG. 5 indicates that the minimum channel length for proper operation increased somewhat less than linearly. For an SOI thickness of 0.5 microns, the minimum channel length was about 1.1 microns, for a ratio just under 1:2. The ratio was about 1:3 for a 0.2 micron channel thickness, and about 1:4 for a 0.1 micron channel thickness.

FIG. 6 shows the subthreshold I-V characteristics as a function of gate voltage for an n-channel device fabricated with a channel 0.75 microns long, 20 microns wide and 0.18 microns thick, and operated with a 1 volt drain-source voltage at a temperature of 85*κ. The I-V characteristics of the device are shown with back-gate biases varying from zero to 10 volts. It can be seen from this graph that the voltage threshold of the device can be controlled in a predictable fashion by an appro- priate setting of the back-gate bias. Desirable turn- off characteristics and a proper voltage threshold of about 0.4 volts were realized with back-gate biases in the approximate range of -4 to -10 volts.

FIG. 7 is a plot of drain current and transconduct- ance as a function of gate voltage for an n-channel MOSFET having a channel thickness of 0.2 microns and bulk doping concentration of about 5xl0¹⁵cm^"3; no thresh¬ old voltage adjustment or punchthrough implants were performed. Fully functional devices were obtained with a -15 volt back-gate bias. The drain current curves, plotted against the logarithmic current scale on the left hand vertical axis, show that the device can stand off a drain voltage of 3 volts without significant current flow below threshold. The transconductance curves, plotted against the linear scale on the right hand vertical axis, show that the device operates properly to provide gain. However, even with a -15 volt back-gate bias, the threshold voltage is shifted to a negative level due to the near-intrinsic channel doping, as opposed to the positive threshold voltage normally associated with a doped n-channel MOSFET. With a conventional ultrathin n-channel device, counter-doping would normally be required to obtain this type of negative voltage threshold. FIGs. 8 and 9 illustrate the temperature dependence of a device fabricated in accordance with the invention. The particular device was an n-channel silicon MOSFET with a channel thickness of 0.18 microns, effective channel length of 0.75 microns, channel width of 20 microns, and a near-intrinsic (10¹⁵cm^'3) channel dopant concentration. Although this device demonstrated enhanced mobility, its low threshold voltage made it less than suitable for room temperature operation. However, the threshold was increased by operation at cryogenic temperatures and through the application of back-gate bias. The measured low field channel mobility as a function of gate bias was increased by a factor of about 2.5 at a cryogenic temperature of 85*K compared to operation at room temperature. The transconductance and output characteristics of the device at both room temperature and 85^#K are shown in FIGs. 8 and 9, respec¬ tively. The drain saturation current was found to improve by about 30% as the temperature was reduced.

The invention thus makes available a novel ultra- thin MOSFET that exhibits improved operating character¬ istics, yet avoids the need for a channel implant. While several illustrative embodiments of the invention have been shown and described, numerous variations and alternate embodiments will occur to those skilled in the art, without departing from the spirit and scope of the invention. For example, the techniques of the invention may be applied to JFETs other than MOSFETs. According¬ ly, it is intended that, within the scope of the append¬ ed claims, the present invention may be practiced otherwise than as specifically described.

Claims

WE CLAIM: 1. A field effect transistor (FET), comprising: a semiconductor layer having mutually spaced doped source and drain regions and a generally intrinsic channel region extending between said source and drain regions, a gate disposed on one side of the channel region for controlling the flow of current between said source and drain regions, and means for applying a back-gate bias voltage to induce an electric field and charge carriers in the channel region.

2. The FET of Claim 1, said channel region having a dopant concentration less than about 10¹⁶ cm^"3.

3. The FET of Claims 1 or 2, the ratio of the channel region's thickness to its length being less than about 1 :2.

4. The FET of Claim 3, said channel region being submicron in length.

5. The FET of any of the preceding claims, the thickness of said channel region being no greater than about 0.2 microns.

6. The FET of any of the preceding claims, the ratio of the channel region's thickness to its length being no greater than about 1 :4.

7. The FET of any of the preceding claims wherein said means for applying a back-gate bias voltage comprises: a first insulating layer on the other side of the channel from said gate, a semiconductor substrate for said insulating layer, and means on said substrate for receiving a voltage signal.

8. The FET of Claim 7, wherein said substrate and semiconductor layer are formed from silicon.

9. The FET of any of the preceding claims, and further comprising: a first insulating layer beneath said semiconductor layer, a second insulating layer on said channel region, and said means for applying said back-gate bias voltage provides an electric field in the channel region for restricting punchthrough and other short-channel effects.

10. The MOSFET structure of Claim 9, the thickness of said first insulating layer being within the approximate range of 0.3-0.5 microns.

11. The FET of any of the preceding claims wherein said FET is operated as a P-channel device by applying a negative voltage to its gate, and said back-gate bias voltage is set at a level which is progressively more negative for progressively lower desired threshold voltage levels.

12. The FET of any of the Claims 1 through 10, wherein said FET is operated as an N-channel device by applying a positive voltage to its gate, and said back-gate bias voltage is set at a level which is progressively more positive for progressively lower desired threshold

) voltage levels.