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WO1989006031A3 - Method of drawing in graphics rendering system - Google Patents

Method of drawing in graphics rendering system Download PDF

Info

Publication number
WO1989006031A3
WO1989006031A3 PCT/US1988/004417 US8804417W WO8906031A3 WO 1989006031 A3 WO1989006031 A3 WO 1989006031A3 US 8804417 W US8804417 W US 8804417W WO 8906031 A3 WO8906031 A3 WO 8906031A3
Authority
WO
WIPO (PCT)
Prior art keywords
line
pixel
site
concurrently
array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US1988/004417
Other languages
French (fr)
Other versions
WO1989006031A2 (en
Inventor
Brian Kelleher
Thomas C Furlong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of WO1989006031A2 publication Critical patent/WO1989006031A2/en
Publication of WO1989006031A3 publication Critical patent/WO1989006031A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G06T11/23—
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Image Generation (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

Method and means for drawing a convex geometric figure to framebuffer storage sequentially addressable as a plurality of update arrays of determined origins which tile the framebuffer. An array comprises pixel storage sites, each specifiable by an offset from array origin. The sites are concurrently updatable. A figure is specified as a set of directed lines; the line segments between mutual intersections comprise the figure boundary; the segments perambulate the boundary in a single sense. For an update array, concurrently for each pixel site, and concurrently for each directed line, the sidedness of the pixel is evaluated with respect to the line to derive a one-bit line discriminant signal. For each site, the line discriminant signals are ANDed to derive a result discriminant signal; a first value specifying outsidedness of the pixel with respect to the figure prevents writing to the site. The process is repeated for further arrays to tile the figure to be drawn.
PCT/US1988/004417 1987-12-18 1988-12-14 Method of drawing in graphics rendering system Ceased WO1989006031A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13477387A 1987-12-18 1987-12-18
US134,773 1987-12-18

Publications (2)

Publication Number Publication Date
WO1989006031A2 WO1989006031A2 (en) 1989-06-29
WO1989006031A3 true WO1989006031A3 (en) 1989-07-13

Family

ID=22464928

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1988/004417 Ceased WO1989006031A2 (en) 1987-12-18 1988-12-14 Method of drawing in graphics rendering system

Country Status (4)

Country Link
EP (1) EP0349630A1 (en)
JP (1) JPH02500142A (en)
CA (1) CA1312683C (en)
WO (1) WO1989006031A2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5251296A (en) * 1990-03-16 1993-10-05 Hewlett-Packard Company Methods and apparatus for generating arbitrarily addressed, arbitrarily shaped tiles in computer graphics systems
GB9009127D0 (en) * 1990-04-24 1990-06-20 Rediffusion Simulation Ltd Image generator
FR2666165B1 (en) * 1990-08-23 1995-02-03 Sextant Avionique METHOD FOR PRESENTING IMAGES ON A MATRIX SCREEN AND SYSTEM FOR IMPLEMENTING THE METHOD.
US5774133A (en) * 1991-01-09 1998-06-30 3Dlabs Ltd. Computer system with improved pixel processing capabilities
WO1992012496A1 (en) * 1991-01-09 1992-07-23 Du Pont Pixel Systems Limited Computer system with enhanced image and graphics capabilities
EP0892972A1 (en) * 1996-04-12 1999-01-27 Intergraph Corporation High-speed video frame buffer using single port memory chips where pixel intensity values for display regions are stored at consecutive addresses of memory blocks
US6278645B1 (en) 1997-04-11 2001-08-21 3Dlabs Inc., Ltd. High speed video frame buffer
JP2007535066A (en) * 2004-04-29 2007-11-29 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Image processing apparatus and method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4590465A (en) * 1982-02-18 1986-05-20 Henry Fuchs Graphics display system using logic-enhanced pixel memory cells
EP0201754A2 (en) * 1985-05-14 1986-11-20 International Business Machines Corporation Method for generating quadratic curve signals
EP0231780A2 (en) * 1986-01-20 1987-08-12 Fujitsu Limited Vector pattern processing circuit for bit map display system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4590465A (en) * 1982-02-18 1986-05-20 Henry Fuchs Graphics display system using logic-enhanced pixel memory cells
EP0201754A2 (en) * 1985-05-14 1986-11-20 International Business Machines Corporation Method for generating quadratic curve signals
EP0231780A2 (en) * 1986-01-20 1987-08-12 Fujitsu Limited Vector pattern processing circuit for bit map display system

Also Published As

Publication number Publication date
EP0349630A1 (en) 1990-01-10
CA1312683C (en) 1993-01-12
WO1989006031A2 (en) 1989-06-29
JPH02500142A (en) 1990-01-18

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