WO1983000242A1

WO1983000242A1 - High speed memory error checker

Info

Publication number: WO1983000242A1
Application number: PCT/US1982/000853
Authority: WO
Inventors: Corporation Ncr; Douglas Blair Anderson
Original assignee: NCR Corp
Current assignee: NCR Voyix Corp
Priority date: 1981-06-26
Filing date: 1982-06-23
Publication date: 1983-01-20
Anticipated expiration: 1983-12-26
Also published as: EP0082198A1; JPS58501060A

Abstract

Un système de stockage de données comprend une mémoire adressable (8), un tampon de sortie (10) couplé à la mémoire adressable (8), un dispositif de contrôle de parité (12) couplé au tampon de sortie (10) et une bascule (16) couplée à la sortie du dispositif de contrôle de parité (12). En fonctionnement, des signaux d'horloge sont appliqués à la mémoire (8), au tampon de sortie (10) et la bascule (16), l'agencement consistant en ce que le contrôle de parité des données dans le tampon de sortie (10) se poursuit tandis que commence la lecture de sortie des données suivantes adressées depuis la mémoire (8). Le temps total du cycle de la mémoire (8) est ainsi diminué.A data storage system includes an addressable memory (8), an output buffer (10) coupled to the addressable memory (8), a parity checker (12) coupled to the output buffer (10) and a latch (16) coupled to the output of the parity check device (12). In operation, clock signals are applied to the memory (8), the output buffer (10) and the flip-flop (16), the arrangement consisting in checking the parity of the data in the output buffer ( 10) continues while reading the output of the following data addressed from the memory (8) begins. The total time of the memory cycle (8) is thus reduced.

Description

HIGH SPEED MEMORY ERROR CHECKER

Technical Field

This invention relates to data storage systems of the kind including an addressable memory having data outputs, output buffer means having inputs coupled to said data outputs, parity checking means coupled to outputs of said output buffer means, and clock control means coupled to said addressable memory and adapted to cause the provision of data on said data outputs. The invention also relates to a method for decreasing the memory cycle time of a data storage system.

Background Art

A data storage system of the kind specified is known from the article by M. K. Creamer and H. G. Elmer "Controlled Retry on Storage Errors", IBM Technical Disclosure Bulletin, Vol. 11, No. 9, February 1969, pages 1100-1101. According to the known system, when the memory is read out, detection of noise or a parity error causes a retry latch to be turned on thereby controlling a predetermined number of tries of readout utilizing the same memory address. The known system has the disadvantage that it is slow to operate in view of the length of the memory cycle time needed to provide for parity checking. In this connection it should be understood that parity checker circuits have large propagation delay relative to output buffer setup requirements.

It is an object of the present invention to provide a data storage system of the kind specified which is relatively fast in operation.

Therefore, according to the present invention, there is provided a data storage system of the kind specified, characterized in that said clock control means is coupled to said output buffer means and is adapted in operation to apply data stored in said output buffer means to said parity checking means while initiating read-out of further data from said addressable memory.

It will be appreciated that in a data storage system according to the immediately preceding paragraph the parity checking cycle is effectively overlapped with the memory fetching cycle thereby enabling the total memory cycle time to be decreased.

According to another aspect of the invention, there is provided a method for decreasing the memory cycle time of a data storage system including an addressable memory, including the steps of addressing said addressable memory to cause data to be read out, applying the data read out to buffer storage means, and checking the buffered data for parity errors, characterized in that said step of addressing is repeated to cause further data to be read' out while said step of checking is in progress.

Brief Description of the Drawings Fig. 1 is a circuit diagram of the preferred embodiment of the invention; and

Fig. 2 illustrates a plurality of waveforms useful in understanding the operation of the preferred embodiment circuit of Fig. 1.

Best Mode for Carrying Out the Invention

Referring now to Fig. 1, a random access store 8 such as a (RAM) has its data output connected to the inputs of a buffer 10. Buffer 10 in the embodiment shown has data inputs labeled D₁-D₈. In addition, there is provided a clocking input labeled C_k. The outputs of the buffer are labeled Q₁-Q₈. In the preferred embodiment of the invention the buffer was a 74LS273 IC chip. The Q outputs from the buffer are directed to a parity error checking chip 12, specifically to corresponding inputs labeled A-H. In the preferred embodiment, the parity error checking chip was a 74LS280 IC chip. A D—type flip-flop 14 receives at its D input a parity signal from the random access store 8 and at its CK input a clocking signal. The output of the flip-flop 14 is taken from the Q output terminal and is coupled to the I input of the parity error checking chip 12. In the preferred embodiment a 74LS74 IC chip was utilized as the flip-flop 14. The output from the parity error checker 12 labeled EVEN is directed to the J input of a J-K type flip-flop 16. The K input of the flip-flop is biased to a +5 volt level through a IK resistor. The CK input is coupled to the clock signal received by the other circuits. The Q output is the parity error signal. In the preferred embodiment of the invention, a 74LS109 IC chip was used as the J-K flip-flop 16. Although not shown, it is understood that the data output from the random access store 8 is directed to other systems within a data processor. The circuit shown specifically in Fig. 1 is for minimizing the memory cycle time by overlapping the parity error checking cycle with the memory access cycle.

Referring now to Fig. 2 in conjunction with the circuit of Fig. 1, the clock signals are shown having a repetition rate equal to 125 nanoseconds. This rate corresponds to the time required to address the memory 8 and to have the data so addressed available at the output of the memory. Various ones of the waveforms shown in Fig. 2 have diagonal hatching marks, which marks indicate a state of the waveforms corresponding to a "don't care" state. The numerical designations corres- pond to an associated address, and data block. For example, data D, corresponds to the data that is positioned at an address A,. In the first clocking cycle, RAM address A. causes the random access store 8 to provide at its output, a delayed time later, a data output D, . The data D, is available at the Q outputs of the output buffer 10 a short time later, as indicated by the waveform labeled buffer output. Parity checking then occurs in the parity error checking circuit 12 and an acceptable error check provides a low level output signal. The parity error output on terminal Q of circuit 16 will remain low during periods of no error detection. Returning now to the next clock cycle, we will assume that this is going to correspond to a bad read or a parity error. Note that the addressing of the RAM access cycle has commenced prior to the availability of a check of parity error for the data corresponding to D₁, that is the data available at the buffer output and at the input to the parity latch 16 has not completed its cycle while the next address is being called for and operated upon within the random access store. For address A₂, data D₂ is read out. Data D₂ is in error, as indicated by the asterisk. Data D₂ is available at the buffer output but it is in error. An error check by the parity error circuit 12 causes an error signal to appear at the EVEN output which in turn causes the latch 16 to latch into a high state, indicating a parity error. The embodiment shown assumes that odd parity is appended when data is written into the random access store. Prior to the output of the parity error circuit going high, the address corresponding to address A3 is already applied to the random access store without waiting for the results of the address to parity error check circuit. Depending on the interfacing of the parity error checking circuit with the remainder of the system, a bad read could automatically cause a re-read of the data associated with that address or the error could be notated and a re-read postponed until operator intervention requests a re-read.

From the foregoing description, it is apparent that the inventive circuit provides a decrease in the total memory access time by overlapping the error checking cycle with the memory accessing cycle. Thus, it will be appreciated that a reduction in the net cycle time is achieved by clocking the output buffer as soon as the worst case delay of the memory chip has been met. Once the buffer has latched the data available at the output of the memory, the memory is addressed for the next memory access. The parity check process for the previous data read is terminated once the buffer has latched the new data. This also marks the beginning of the new check cycle. This overlapping of accessing with parity checking decreases memory cycle time.

Claims

CLAIMS :

1. A data storage system including an addressable memory (8) having data outputs, output buffer means (10) having inputs coupled to said data outputs, parity checking means (12) coupled to outputs of said output buffer means (10 ) , and clock control means coupled to said addressable memory (8) and adapted to cause the provision of data on said data outputs, characterized in that said clock control means is coupled to said output buffer means (10) and is adapted in operation to apply data stored in said output buffer means (10) to said parity checking means (12) while initiating readout of further data from said addressable memory (8).

2. A data storage system according to claim 1, characterized by latching means (16) coupled to an output of said parity checking means (12) and to said clock control means and adapted to provide a signal of a first or a second state according to whether or not an error is detected by said parity checking means (12).

3. A data storage system according to claim

2, characterized in that said clock control means is adapted to provide clock signals defining clock cycles, such that each clock signal causes said addressable memory (8) to be addressed and causes data stored in said output buffer means (10) to be applied to said parity checking means (12).

4. A data storage system according to claim

3, characterized in that each said clock pulse is applied to said latching means (16) to provide an operating signal therefor.

5. A method for decreasing the memory cycle time of a data storage system including an addressable memory, including the steps of addressing said addressable

5 . ( concluded ) memory to cause data to be read out, applying the data read out to buffer storage means, and checking the buffered data for parity errors, characterized in that said step of addressing is repeated to cause further data to be read out while said step of checking is in progress.