[go: up one dir, main page]

WO1982002274A1 - Dispositif pour effacer automatiquement le contenu d'informations dans des bases de donnees - Google Patents

Dispositif pour effacer automatiquement le contenu d'informations dans des bases de donnees Download PDF

Info

Publication number
WO1982002274A1
WO1982002274A1 PCT/SE1981/000385 SE8100385W WO8202274A1 WO 1982002274 A1 WO1982002274 A1 WO 1982002274A1 SE 8100385 W SE8100385 W SE 8100385W WO 8202274 A1 WO8202274 A1 WO 8202274A1
Authority
WO
WIPO (PCT)
Prior art keywords
memories
memory
data
group
generators
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/SE1981/000385
Other languages
English (en)
Inventor
Telefon Ab L M Ericsson
Nils Herbert Edstroem
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to NL8120486A priority Critical patent/NL8120486A/nl
Publication of WO1982002274A1 publication Critical patent/WO1982002274A1/fr
Priority to DK377782A priority patent/DK377782A/da
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B5/00—Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
    • G11B5/02—Recording, reproducing, or erasing methods; Read, write or erase circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells

Definitions

  • the invention relates to an arrangement in data bases to prevent someone from unduly access to, or misuse of, the information content in the data base.
  • the invention which is characterized in the claim, solves said probl by providing the data base with a special button a so called emergenc button which when activated provides electrical impulses to an electr nic circuit which in a first step erases all data information in the data base and then in a second step ' erases all program information- in the data base.
  • the arrangement according to the inventio is part of a data base installation comprising a data system of a known kind which for example is described in AXE 10 System Survey, LME 118708 where a computer controls writing and reading in connecte data memories and program memories- Such writing and reading is know technics and is not included in the inventive idea but is mentioned to facilitate the judgement of the arrangement.
  • data- and program memories can be for example tape memories, casette memories, disk memories, semiconductor memories etc
  • the memories can be of different types and can also contain different kind of information, i.e. they can be considered as functi units completely separated from each other.
  • a number of additional memories are also included in the data base, that is the program memories PS1-PSn. Also these memories can provide function units se ⁇ parated from each other.
  • the memories PS1-PSn- those programs are stored which control the processes in the data base. All the memorie data memories as well as program memories receive write- and read orders from a computer CPU which is connected but not shown in the figure. By dividing the memories in function units a very short access time is obtained.
  • the arrangement according to the invention contains address generators AD1-ADn and AP1-APn, respectively, separately connected to the address inputs of each data store DS1-DSn and program store PS1-PS ⁇ , respectively, for pointing o each memory position appearing in the connected memory.
  • Gate circuits GD1,.- GDn, and GP1-GPn, respectively, are connected to the data in ⁇ puts of the memories, from which gates logical zeros are written into each > position on a pointed out address in the memory when the memory receives a writing pulse on a writing input W.
  • the output from an operation point M0 is connected to the set-input on a bistable flip-flop SR1, the task of which is, when activated, to provide a signal of a determined logical level as long as no activation signal is fed to the reset-input of th flip-flop.
  • the output of the flip-flop is connected to the inputs of a number of address generators AD1-AD ⁇ made by TEXAS INSTRUMENTS type 74 LS 191.
  • Each of the address generators is separately con ⁇ nected on the outputs to the address inputs on a corresponding data memory DS1-DSn made by INTEL type 2114 L.
  • the task of the address generators when activated and when controlled by a clock CL being common to the system, is to generate all addresses vhich can appear in the connected data memory and in turn point out each address in the memory.
  • each word which is stored in the memory consists of 4 bits, of course the memories can also be designed for other word lengths, for example 8 bits. This, however, does not effect the principle for erasing.
  • the output from a gate circuit GD1..-GDn is connected to each of the data inputs on each data memory DS1-DSn.
  • the gate circuits are logical AND-circuits made b NATIONAL type 74 LS 02 provided with two inputs one of which is inver ⁇ ting.
  • the output from said flip-flop SR1 is connected to all the mentioned inverting inputs of the AND-circuits.
  • the second input on each of the AND-circuits is connected to a data bus DB which is common to the memories through which data bus the communication is maintained between the computer CPU and the memories DS1-DS ⁇ .
  • the computer can be a microprocessor made by MOTOROLA type MC 68000.
  • the output from the flip-flop SR1 is also connected to one of the inputs of an OR-circuit 0R1-0Rn, the second input_of which is fed from the computer CPU.
  • the output of said OR-circuits is connected to the write input of respective associated data memory.
  • a register RD1-RDn made by TEXAS INSTRUMENTS type 74LS174 is connected to the dat outputs on each of the data memories.
  • the registers contain as many positions as the data word, i.e. in the chosen case 4.
  • the outputs fro the registers are connected to corresponding inputs of AND-circuits 0D1-0Dn, the outputs of which are inverting and connected to inputs of a further AND-circuit 02.
  • the circuit 02 has as many inputs as the number of AND-circuits 0Dl-0Dn, which in its turn depends on the numbe of data memories.
  • the number of memories is t DS1-DSn, which implies two AND-circuits 0Dl-0Dn and consequently two inputs-on the circuit 02. As appears from the labelling of the memorie of course there can be more than two memories.
  • a counter C1 common to all data memories is also connected to the out- put of the flip-flop SR1, which counter controlled by the system clock
  • OM blocking circuits consisting of AND-circuits the one input of which inverting and connected to the output on the flip-flop SR1.
  • the seco input of the circuits B1-Bn is fed from the computer CPU, which in n mal circumstances provides a reading pulse on this input.
  • the output from the AND-circuit 02 is connected to the set-input on a second bi stable flip-flop SR2 of the same type as the flip-flop SR1 and the o put of which, in exactly the same manner as the output from the flip flop SRI, feeds an exactly identical electronic circuit which contro the work towards the data memories but this circuit is now intended for the program memories PS1-pSn, ' which.memories are of the same typ as the data memories.
  • the output" of the flip-flop SR2 is con ⁇ nected to the inputs of the.. : address generators * AP1-APn> which addres generators are of the same type as the generators ADl-ADn.
  • Each, of t address generators is connected to the address inputs of a corr ⁇ spon ing program memory PS1-PSn.
  • the task of the generators, " as previousl mentioned, is to generate all addresses which can appear in. the con ⁇ nected program memory controlled by the common system clock, and in turn point out each address in the memory.
  • the word length in the program memories is the same as in the data memories i.e. 4 bits.
  • Gate circuits GPI ⁇ -GPn of the same type as the gate circuits GD1,.- GDn, are connected to the data inputs of the program memories.
  • the output of the flip-flop SR2 is connected to the inverting input of all AND-circuits GPI ⁇ -GPn.*.
  • a second input on each of the AND-circuit is connected to a control bus CB being common to the program memories through which bus the computer CPU in the normal case exchange data . with the memories PS1-PSn.
  • the output % from an OR-circuit ORPl-ORPn is connected to the writing input on each of the program memories.
  • One input on each OR-circ ⁇ it is fed from the computer CPU providing a writing pulse at normal operation.
  • the second input of the OR-circuit is connected to the output of the flip-flop SR2, from which .write pul are obtained when erasing.
  • a register RP1-RPn of the same type as the registers RD1-RDn is connected to the data outputs on each of the memories PSI-PSn.
  • the outputs from the registers are connected to corresponding inputs " on AND-circuits 0P1-0Pn the outputs of which are inverting and connected to inputs of a further AND-circuit 03.
  • the output of the circuit 03 is connected to the set-input on a third bistable flip-flop SR3, of the same type as the flip-flops SR1-SR2, a
  • C1 which counter C2 when the last position ' in the program memory has been pointed out, reads the selected word into respective register RP RPn.
  • AND-circuits BP1-BPn are connected to the read inputs of the program memories to block reading.in the memory during erasing.
  • One o the inputs of each of the circuits BP1-BPn is inverting and fed from the output of the flip-flop SR2. Under normal. conditions the computer CPU providing read pulses to the memories by connection to the second input of the circuits BP1-BPn.
  • the operator activates a non-locking push-button a so called "emergen button” at an operation point MO. Then a positive voltage pulse is transmitted to the set-input of the bistable flip-flop SR1 which then is set to ONE, i.e. providing a logical one-signal on the output and remaining in this position if not a zero-setting-s gnal is fed to the reset input of the flip-flop.
  • the output signal from the lip-flop SR activates the address generators AD1-ADn, which controlled by signals
  • the counter C1 which contains as many steps a the number of words in the data memory is activated by the signal fro the flip-flop SR1 and is stepped ⁇ controlled by the common system cloc one step for each selected address in the data memory.
  • the count has reached the position corresponding to the last address position o the data memory it provides on the output a signal which directly activates the read input R of all dat3 memories DS1-DSn, the contents in the last address position of each data memory being fed to respec ⁇ tive register RD1-RDn.
  • the inputs of the circuit 02 are activated in parallel when the last address position of respective data memory is read.
  • the signal from the output on the circuit 02 is fed to the input of the flip-flop SR2 which then is activated and transmits an ONE-signal on the output.
  • This signal constitutes activation signal for erasing in the program memories PS1-PSn.
  • the process is exactly the same as has been described when erasing in the data memories DS1-DSn.
  • the signals from the flip-flop SR2 activate the address generators AP1-APn, which controlled by the system clock CL generates all addresses which can appear in the connected program memories PS1- PSn. In turn all addresses are pointed out.
  • the signal from the flip- flop SR2 activates the inverting inputs of the AND-circuits GP ⁇ -GPn,, and furthermore it provides writing pulse to the writing input W of the program memories by activating one input of each of the OR-circuit 0RP1-0RPn-
  • the logical ' zeros appearing on the data inputs of the memo ⁇ ries when erasing, are written into the addresses pointed out by the address generators so that finally also all program memories are fille with zeros.
  • the erasing is then finished and .the information in the la selected address position in each program memory is read to respectiv register RPl-RPn, when reading pulse is obtained from the counter C2 which is stepped syncronously with the address generators and common t the memories.
  • Blocking of reading in the rest of the memory positions is obtained by the fact that the output signal from the flip-flop SR2 activates the inverting inputs of the AND-circuits " BP1-BPn, zero signa being obtained on the reading inputs R of the memories as also the counter C2 in these address positions transmits zero signal.
  • the sig ⁇ nals from the registers RP1-RPn are fed to corresponding inputs of the AND-circuits 0P1-0Pn, the inverting outputs of which transmit signals to corresponding inputs of an AND-circuit 03.
  • this circuit transmits an output signal to the third bistabl flip-flop SR3, which then is* set to ONE and transmits activation signa to the lamp L which then is turned on and shows that the whole erasing process is ended.
  • the computer CPU controls the writing and reading in the memories- The writing is carried out by connection to the OR-circuits OR1-0Rn and ORPl-ORPn, respectively.
  • the reading is carried out by connecting the computer to the AND-circuits B1-Bn and BP1-BPn, respectively- When zero-signal is transmitted from the outputs of the flip-flop.s SR1 and SR2 to the in ⁇ verting inputs of the AND-circuits GDI ⁇ -GDn, and * GPI.-GPn,,respectivel the feeding of information to the memories from the data bus DB and th control bus CB is completely controlled by the computer CPU.

Landscapes

  • Read Only Memory (AREA)
  • Complex Calculations (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Storage Device Security (AREA)
  • Programmable Controllers (AREA)

Abstract

Dispositif permettant de detruire par effacement le contenu d'informations dans des memoires de donnees et dans des memoires de programmes inclues dans une installation de banque de donnees, sans detruire le materiel. Un dispositif de fonctionnement (MO) active un premier groupe de generateurs d'adresse travaillant en parallele (ADl-ADn), ces generateurs generant de maniere successive et selectionnant toutes les adresses dans une memoire (DSl-DSn) qui est connectee separement a chacun des generateurs et qui fait partie d'un premier groupe de memoires. Des circuits de portes (GDl1-GDn) sont connectes aux entrees de donnees sur chaque unite de memoire dans ce premier groupe de moires, par l'intermediaire desquels des bits de meme niveau logique sont enregistres dans les adresses selectionnees des memoires, independamment de ce qui est deja entre. Le dispositif d'operation (MO) active egalement un second groupe de generateurs d'adresses travaillant parallelement (ATl-ATn) ces generateurs generant et selectionnant successivement toutes les adresses dans une memoire (PSl-PSn) qui est connectee separement a chacun des generateurs, cette memoire faisant partie d'un second groupe de memoires. Des circuits de portes (GP1-GPn4) sont connectes aux entrees de donnees de chaque unite de memoires dans son second groupe de memoires, circuits par l'intermediaire desquels des bits de meme niveau logique sont entres dans les adresses selectionnees des memoires. Apres avoir termine l'effacement dans ce premier et dans ce second groupes de memoires, un signal d'activation est transmis a un dispositif de commande (L) qui indique alors que l'effacement est termine.
PCT/SE1981/000385 1980-12-23 1981-12-21 Dispositif pour effacer automatiquement le contenu d'informations dans des bases de donnees Ceased WO1982002274A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
NL8120486A NL8120486A (nl) 1980-12-23 1981-12-21 Inrichting voor het automatisch uitwissen van de informatie-inhoud in een informatiebasis.
DK377782A DK377782A (da) 1980-12-23 1982-08-23 Indretning til automatisk at slette informationsindholdet i databaser

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE8009141801223 1980-12-23
SE8009141A SE425705B (sv) 1980-12-23 1980-12-23 Anordning for att i en databasanleggning automatiskt forstora informationsinnehallet i dataminnen och programminnen

Publications (1)

Publication Number Publication Date
WO1982002274A1 true WO1982002274A1 (fr) 1982-07-08

Family

ID=20342579

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/SE1981/000385 Ceased WO1982002274A1 (fr) 1980-12-23 1981-12-21 Dispositif pour effacer automatiquement le contenu d'informations dans des bases de donnees

Country Status (7)

Country Link
ES (1) ES8302944A1 (fr)
GB (1) GB2108738B (fr)
IT (1) IT8125766A0 (fr)
NL (1) NL8120486A (fr)
NO (1) NO822813L (fr)
SE (1) SE425705B (fr)
WO (1) WO1982002274A1 (fr)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4593384A (en) * 1984-12-21 1986-06-03 Ncr Corporation Security device for the secure storage of sensitive data
US4698750A (en) * 1984-12-27 1987-10-06 Motorola, Inc. Security for integrated circuit microcomputer with EEPROM
EP0149043A3 (en) * 1983-12-30 1987-12-09 International Business Machines Corporation Random access memory
US4783801A (en) * 1983-12-29 1988-11-08 Gao Gesellschaft Fur Automation Und Organisation Mbh Apparatus for protecting secret information
US4860351A (en) * 1986-11-05 1989-08-22 Ibm Corporation Tamper-resistant packaging for protection of information stored in electronic circuitry
US4890263A (en) * 1988-05-31 1989-12-26 Dallas Semiconductor Corporation RAM with capability for rapid clearing of data from memory by simultaneously selecting all row lines
US5036488A (en) * 1989-03-24 1991-07-30 David Motarjemi Automatic programming and erasing device for electrically erasable programmable read-only memories
US5515328A (en) * 1990-03-05 1996-05-07 Sgs-Thomson Microelectronics, S.A. Memory circuit with element for the memorizing of word line selection for an erasure of a block of information
WO1997037353A1 (fr) * 1996-03-28 1997-10-09 Siemens Aktiengesellschaft Montage comportant une pluralite de composants de circuit electroniques
GB2321123A (en) * 1997-01-11 1998-07-15 Motorola Ltd Circuit for erasing a memory and method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1486386A (en) * 1975-03-17 1977-09-21 Ibm Bias/erase oscillator circuits for magnetic recording apparatus
US4172291A (en) * 1978-08-07 1979-10-23 Fairchild Camera And Instrument Corp. Preset circuit for information storage devices

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1486386A (en) * 1975-03-17 1977-09-21 Ibm Bias/erase oscillator circuits for magnetic recording apparatus
US4172291A (en) * 1978-08-07 1979-10-23 Fairchild Camera And Instrument Corp. Preset circuit for information storage devices

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4783801A (en) * 1983-12-29 1988-11-08 Gao Gesellschaft Fur Automation Und Organisation Mbh Apparatus for protecting secret information
EP0149043A3 (en) * 1983-12-30 1987-12-09 International Business Machines Corporation Random access memory
US4593384A (en) * 1984-12-21 1986-06-03 Ncr Corporation Security device for the secure storage of sensitive data
US4698750A (en) * 1984-12-27 1987-10-06 Motorola, Inc. Security for integrated circuit microcomputer with EEPROM
US4860351A (en) * 1986-11-05 1989-08-22 Ibm Corporation Tamper-resistant packaging for protection of information stored in electronic circuitry
US4890263A (en) * 1988-05-31 1989-12-26 Dallas Semiconductor Corporation RAM with capability for rapid clearing of data from memory by simultaneously selecting all row lines
US5036488A (en) * 1989-03-24 1991-07-30 David Motarjemi Automatic programming and erasing device for electrically erasable programmable read-only memories
US5515328A (en) * 1990-03-05 1996-05-07 Sgs-Thomson Microelectronics, S.A. Memory circuit with element for the memorizing of word line selection for an erasure of a block of information
WO1997037353A1 (fr) * 1996-03-28 1997-10-09 Siemens Aktiengesellschaft Montage comportant une pluralite de composants de circuit electroniques
RU2189082C2 (ru) * 1996-03-28 2002-09-10 Сименс Акциенгезелльшафт Схемное устройство с некоторым числом электронных схемных компонентов
GB2321123A (en) * 1997-01-11 1998-07-15 Motorola Ltd Circuit for erasing a memory and method thereof
GB2321123B (en) * 1997-01-11 2001-01-03 Motorola Ltd Circuit for erasing a memory and a method thereof

Also Published As

Publication number Publication date
NO822813L (no) 1982-08-18
SE425705B (sv) 1982-10-25
GB2108738B (en) 1985-04-24
NL8120486A (nl) 1983-04-05
IT8125766A0 (it) 1981-12-22
ES508252A0 (es) 1982-12-01
ES8302944A1 (es) 1982-12-01
GB2108738A (en) 1983-05-18
SE8009141L (sv) 1982-06-24

Similar Documents

Publication Publication Date Title
US4120030A (en) Computer software security system
US5148534A (en) Hardware cartridge representing verifiable, use-once authorization
US3422401A (en) Electric data handling apparatus
US4814982A (en) Reconfigurable, multiprocessor system with protected, multiple, memories
US4332009A (en) Memory protection system
US4295041A (en) Device for the protection of access to a permanent memory of a portable data carrier
EP0118446A1 (fr) Configuration de memoire a systeme premier entre, premier sorti (fifo) pour un stockage en file d'attente.
WO1982002274A1 (fr) Dispositif pour effacer automatiquement le contenu d'informations dans des bases de donnees
EP0412251A2 (fr) Validation sans pile de jeton de type écriture et lecture unique
US4424573A (en) System for entering a postage meter serial number into a nonvolatile memory from an external channel after assembly of the meter
GB2232281A (en) IC card memory protection
GB1069480A (en) Memory system
US3755788A (en) Data recirculator
US3197742A (en) Search apparatus
US3686640A (en) Variable organization memory system
US5553019A (en) Write-once read-many memory using EEPROM cells
US20020188858A1 (en) Method and device for making information contents of a volatile semiconductor memory irretrievable
US3376555A (en) Two-dimensional associative memory system
US4712177A (en) Circuit for a cord carrier having a memory and an access control unit for secure data access
EP0200198B1 (fr) Dispositif d'extension de la capacité de mémoire
US3753239A (en) Data flow in a machine log system
US3286237A (en) Tabulator
US3387272A (en) Content addressable memory system using address transformation circuits
EP0049113B1 (fr) Suppression de fichiers dans une mémoire à cassettes à bulles, et appareil de commande pour une mémoire à cassette à bulles
US5101374A (en) Secure, fast storage and retrieval without interactive checking

Legal Events

Date Code Title Description
AK Designated states

Designated state(s): DK FI GB NL NO