WO1980000275A1 - Searched information display system - Google Patents

Abstract

One unit of searched information is read out from a main memory (81) to display as a single display line in a sequential order, and the read-out information is converted in a color conversion circuit (177) which supplies converted color signals to a CRT color display unit (82). The display screen of the CRT display unit (82) is divided into a plurality of regions, each of which is allocated to the searched information obtained from a plurality of different apparatus to be monitored. There is provided means (206) for varying the frequency of write-in of the information into corresponding memory locations of the main memory (81), whereby which the moving velocity of the picture in each region may be made different so as to increase resolution of the picture. There are also provided means (362, 363) for differentiating the color characteristics representing the relation between the level of the searched information and its hue among the regions of the picture, thereby reducing the differences in hue between the regions which are caused by the level differences of received information from the different devices.

Description

 Specification

Title of invention Detection information display device

Technical field

 The present invention relates to an ultrasonic detection display device such as a fish finder or a radio wave detection display device such as a radar, in which each portion of the detection information is displayed in a different color according to the level. The present invention relates to a detection information display device that displays as color display lines, and the display lines are sequentially arranged in the order of detection information and displayed as one raster scanning image.

Indication technique

 Conventionally, the detection information display device divides the screen into, for example, the upper and lower screens, and the upper part displays a normal display in which the display line moves sequentially each time new information is input. It has been proposed to display an enlarged image of a certain portion in the length direction of the book display line, that is, a depth direction in a fish finder, or in general, a certain portion in the distance direction in the lower display area. However, this only enlarges the display in the distance direction, that is, only in the depth direction.

 When a fish finder is installed on a fishing boat to detect the state directly below the fishing boat, and when the fishing boat is drawing a bottom seine, the distance from the fishing boat to the bottom seine is 1000 m to 2000 m. In this case, it is desirable to display the detection information near the position of the fishing boat and the detection information near the position of the net. In this way, all detection information between 1000 m and 2000 m is displayed on the same image.

ΟΜΡΙ

Λ, WIPO If the speed of a fishing boat is 1.5 mZ seconds, the detection information for 10 to 20 minutes needs to be displayed on one screen. In such a display, the resolution of the detection image is poor, and even if a school of fish is present just below the current fishing boat, this is a single point image, and this fish school is displayed as a single point image. It cannot be found from the displayed image.

 Also, the display screen is divided into, for example, the upper and lower areas, and one side displays the detection information from the fish finder, and the other side shows the fishing net equipped with the fish finder.) It has also been proposed to display detection information from a so-called net monitor that monitors the vicinity of the opening.

 In this way, the two types of detection information displayed on the same screen are different devices. ?? If it is obtained, the sensitivity of the two devices is different. Even the same level of detection information is displayed in different colors, giving incorrect information to those who observe this screen.

 The present invention provides an apparatus in which the disadvantages of such a conventional detection information display apparatus are improved.

 An object of the present invention is to divide a display screen into a plurality of regions in a detection information display device that displays detection information as a raster scan image, and to vary the moving speed of the image in these regions. To be able to do it.

 Another object of the present invention is to show a relationship between a display information level and a display color from, for example, a fish finder and a net monitor.

WIPO By making the color characteristics different in the plurality of regions, even if the receiving sensitivities match, the color display of information can be made the same.

Disclosure of the invention

 According to the present invention, in a plurality of areas of the display image, the image is transmitted. In the same way, if the image is enlarged in the direction perpendicular to the distance direction as well, the image in the upper normal display can be enlarged in any direction, and the analysis of the displayed image becomes easier.

 Furthermore, if the image transmission speed of one of the two areas of the display screen is made different from the image transmission speed of the other in this way, an image for a relatively long time or an image for a long moving distance is generated on one of them. On the other hand, only the part currently being detected can be enlarged in the time axis direction so that a high-resolution display is performed.

 Therefore, when the detection information from the fish finder and the net monitor is displayed in multiple areas, the whole information is displayed from the position of the net to the position immediately below the fishing boat. For this detection information, it is possible to increase the speed of image transmission so that the school of fish is displayed as a large image.

Alternatively, the so-called net monitor that detects and displays the opening of the net of the bottom seine operates completely independently of the fish finder mounted on the fishing boat]), and in general, the repetition frequency is fish finder. It's fast!) In this way, the detection information of the fish finder and the detection information of the net monitor are divided, for example, up and down on the display screen. When the detection information is displayed separately, it is also possible to display the detection information at the speed at which the information can be obtained without adjusting the speed.

 According to the present invention, the detection information is displayed as one display line, and the display lines are arranged in order from the oldest detection information and displayed so as to be displayed as a raster scan image. The information is stored in the main memory, and the main memory is repeatedly read out and supplied to the raster scan display. Each time new detection information is written to the main memory, new information is written to the main memory so that the oldest information is erased. Information is written into the main memory so that completely different or mutually related information is displayed as a raster image in a plurality of areas of the screen. In this case, a means is provided to vary the frequency of writing the information depending on the area. Therefore, the moving speed of the image differs depending on the plurality of regions. As described above, the information currently being detected in one area is moved at a high speed every time new information is obtained and displayed at high resolution, and in the other area, The writing frequency is reduced so that relatively long information is also displayed continuously, and the image of the detection information over a long time is displayed from the force of moving at a low speed.

 This discovery is based on a detection information display device that displays the detection information as a color corresponding to the level on a raster scanning display. Divide and then

OMPI Within the divided area, the color characteristics indicating the relationship between the detection information level and the display color are made different. In this way, for example, when the detection information from the fish finder and the detection information from the net monitor are displayed in different areas, the reception sensitivity between the fish finder and the net monitor Even if they do not match, by appropriately selecting the color characteristics in both display areas, if the level of both detection information is the same, the display will be in the same color. It can be Therefore, it is possible to give information to the observer by mistake. In this case, it may be relatively difficult to make the reception sensitivity uniform, but it is easy to make the same color display of information from different devices at the same level.

 In addition to displaying the different detection information in different display areas, for example, the same information is displayed in different display areas, and the color characteristics are made different from each other, for example, display in one area. Can increase the reception sensitivity equivalently. In addition, many effects can be obtained as described in the following embodiments.

BRIEF DESCRIPTION OF THE FIGURES

 FIG. 1 is a block diagram schematically showing an ultrasonic detection and display device according to the present invention, FIG. 2 is a waveform diagram for explaining the operation of FIG. 1, and FIGS. The block diagram of the concrete embodiment of the ultrasonic detection device according to the present invention divided into these three figures, and FIG. 6 shows the operation of the embodiment shown in FIG. 3 to FIG. Waveform diagram for explanation, Fig. 7 shows fishing boat

O PI FIG. 8 is a circuit diagram showing a specific example of a synchronous selection circuit 87, FIG. 9 is a diagram showing an example of a selection circuit 99, and FIG. 10 is a reading means. FIG. 11 is a waveform diagram for explaining the operation of the gate control circuit for the main memory, and FIG. 12 is an example of conversion in a color conversion circuit. Fig. 13, Fig. 13 is a waveform diagram showing an example of the received signal of the net monitor, Fig. 14 and Fig. 15 are diagrams showing examples of the display screen, Fig. 16 is a low-speed transmission] 9 FIG. 17 is a block diagram showing an example of a thinning-out correction circuit, FIG. 18 is a diagram showing various display examples according to the present invention, and FIG. 19 is a waveform diagram showing an example of the output of the decision circuit. Block diagram showing an example of writing the same data at the same speed on the input side of memory, and Fig. 20 shows the same data on the output side of main memory. Fig. 5 shows the part corresponding to Fig. 5 of the example in which data can be displayed on the display screen at the same speed. Fig. 21 shows the same data on the output side of the main memory. FIG. 22 is a waveform diagram illustrating an example of the control circuit 207 of FIG. 20, and FIG. 23 is a diagram illustrating the operation thereof. 24 and 25 are block diagrams showing other examples corresponding to FIG. 5, respectively. FIG. 26 is an example of a color characteristic conversion unit which is a main part of the present invention. FIG. 27 is a block diagram showing the input / output characteristics of the code conversion circuit 361, FIG. 28 and FIG. 29 are ffi diagrams showing the input / output characteristics of the code conversion circuit 361, FIG. 30 is a block diagram for switching the correlation display and the like, and FIG. 31 is a block diagram for displaying the STC and the normal display. OMPI BEST MODE FOR CARRYING OUT THE INVENTION

 Next, an example in which the detection information display device according to the present invention is applied to a fish finder will be described with reference to the drawings. First, refer to FIG. The transmitter / receiver 23 is excited at a constant period from the transmitter / receiver 1 in the transmitter / receiver 11 of the fish finder through the transmission / reception shared circuit 2. As a result, the ultrasonic pulse from the transducer 23 is radiated toward the seabed 3. The reflected wave is received by the transmitter / receiver 23 and received by the receiver 4 through the transmission / reception shared circuit 2. As shown in Fig. 2A, this received signal consists of an oscillation pulse 25, a reflected signal 26 from a school of fish 5, and a reflected signal 27 from the seabed 3. The received signal is converted into a digital signal of a bit in the AD conversion circuit 28, for example, and the digital signal is written into the data fetch memory 34. The data fetch memory 34 is, for example, a shift register, and can simultaneously write digital signals of the number of output parallel bits output from the AD conversion circuit 28. In this writing, the write pulse (FIG. 2B) generated in the write pulse generation circuit 6 from the signal of the oscillator (not shown) in the transmission unit 1 passes through the OR circuit 56 to acquire data. It is supplied to the memory 34 and performed.

On the other hand, a color cathode ray tube display 82 is provided, and the display surface of the display 82 is controlled by an electron beam by a line synchronization signal or a plane synchronization signal from the cathode ray tube control circuit 7 to perform surface scanning. (The readout signal from the main memory 81 is supplied to the display 82 through the power error conversion circuit 177. The main memory 81 may be a shift register, for example. ¾ jp Stores one screen information of the display surface of the display unit 82 Capacity there, understand line scan lines 1 to definitive on the display surface of the Ni indicator 82 Let 's easy, 2, _n and corresponding sheet oice re g data section Fi, F _2, F _n there] 9 These register units are sequentially and cascaded. Re g data unit Fi at some point, F _2, ... de di data le information in F _n is displayed on each scanning line 1, 2, on the II. Subsequent stage output oice re g data portion Fi is Ca La - is fed back to the first stage Hatsushi oice re g data unit F _n through the gate circuit 8 is supplied to the converter circuit 1 7 7, this The shift speed is selected so that one cycle of the cycle is the same as the surface scanning cycle of the cathode ray tube display 82. In this state, the contents of the main memory 81 are displayed on the display 82 as a still image. Sheet oice re g data unit Fi～; each stage of the F _n is Ru can and this for storing the digital signals of the parallel four bits Bok respectively. In response to the input digital signal, the color conversion circuit 1 7 7 performs signal conversion for causing the display unit 82 to emit a predetermined color corresponding to the signal level. The red, green, and blue electron guns of the color cathode ray tube display 82 are controlled by the output, and O

In the transmission / reception section 11, a reception signal for one transmission pulse is taken into the data acquisition memory 34, and the signal in the memory 34 is stored in the main memory 81 with information of one display line. Is transferred. This new signal is displayed at a predetermined position on the display. For example, in the figure, the newest signal is read out from the register unit 5 \ and displayed on the first scanning line at the beginning of the surface scanning. The second scanning line ₂ has a There are data that was in the register F ₂ is read and displayed. The following Similarly the n-th line scan line _n oldest data lies at the beginning of the surface scanned re g data unit F _n are displayed. Data capture Note Li 34 are each sheet oice re g data portion identical to one volume of P \ ~ F _n of Shume mode Li 81. When the writing to the memory 34 is completed, a signal indicating this is supplied to the read pulse generation circuit 9. The circuit 9 is supplied with the plane synchronization signal _Pv and the line synchronization signal P shown in FIG. 2C from the cathode ray tube control circuit 7. The surface synchronization signal next to the above-mentioned write end]) A read pulse is generated for one line synchronization signal period as shown in Fig. 2D. This read pulse is synchronized with the shift pulse of the main memory 81, and is the same as the number of write pulses. Read and Pulse will read the data capture Note Li 34 through its OR circuits 56 and is supplied through its gate circuit 8 to the first stage of sheet oice re g data F _n . The output of the main memory 81 is also always supplied to the delay circuit 124 for one scanning line. Therefore, when the transfer from the data acquisition memory 34 to the main memory 81 is completed, the newest data stored in the register unit Fi up to that time is stored in the delay circuit 124] 9, the output of Shume mode Li 81 in this state is returned to the first stage sheet oice re g data unit F _n through a delay circuit 1 2 4. The feedback through the delay circuit 124 is the period from the end of the reading of the data acquisition memory 34 until the next plane synchronization signal as shown in FIG. 2E. Immediately before this plane synchronization signal, the newest data written from the data acquisition memory 34 this time is located in the shift register section, and the oldest data up to that time is stored. Are located in the delay circuits 124. The output of the main Note Shume during and re read mode Li 81 from the next surface synchronizing signal gate circuit 8 is controlled in earthenware pots by being fed back to the sheet oice re g data unit F _n. Thus, the new data is written to the main memory 81, and the oldest data is removed from the main memory 81 until it is moved to the delay circuit 124.

 In this way, each time data is moved from the data acquisition memory 34 to the main memory 81, the newest data is displayed on the scanning line 1, and the oldest data is displayed on the main scanning line 1. The line is removed from the memory 81, and the display line moves one by one in the direction perpendicular to the line on the display surface, and the second new data is displayed on the line scan line. As a result, the oscillating line 15 5 corresponding to the oscillation pulse 25 is displayed on the seafloor 3 and the display 15 3 is displayed on the fish school 5 and the display 15 4 is displayed on the cathode ray tube display 82. Appear on the surface. The display is similar to the record on the recording paper of a conventional fish finder, and the display moves from right to left as in Fig. 1 when the recording paper is shifted from right to left. . In Fig. 1, when the speed of the data received from the transmitting / receiving unit 11 and the scanning speed of the cathode ray tube display 82 are properly selected, the data acquisition memory 34 is omitted and the AD conversion circuit is omitted. It is also possible to write the data from 28 directly to the main memory 81.

 Next, the fish finder according to the present invention will be described in more detail with reference to the drawings in FIG. Figs. 3 to 5 show the parts that should be shown as a single drawing.

O PI

'' WIPO The symbol inside the circle attached to the end of the lead line indicates that the same things are connected to each other. In FIG. 3, the transmitting / receiving unit 11 is almost the same as that of the conventional fish finder. That is, the reference signal from the reference oscillator 12 is frequency-divided in the range divider 13, and the division ratio is changed by selection of the range switch 14. That is, the frequency division ratio of the frequency divider 13 can be changed by setting the detection range to, for example, 0 to 100 m, 0 to 200 m, 0 to 400 m, or 0 to 800 m. However, the deeper it is detected, the greater its frequency division ratio and the lower its output frequency.

 The output divided in this way is selected in the display time switching circuit 15 by, for example, one of three division ratios, a standard one, a multiple thereof, and a standard one-half. This circuit is peculiar to a fish finder using this cathode ray tube, and when it is in one of the switching positions by selecting the three-point switching switch 16, it is displayed normally and the other one is switched. When it is at, fast-forward J9 is displayed, the output frequency is doubled, and when it is at another switching position, it is delayed! ) This is a display, and the output frequency is 1 to 2 of the normal display. ]) The rewriting time of the information in the main memory 81, which stores the display information for the color cathode ray tube display 82 described later, has been shortened]), it has been delayed]? Can be switched by the switching switch 16.

 The output of the display time switching circuit 15 is further frequency-divided by the repetitive periodic counter 17 to form a trigger oscillation cycle. The output of this repetition cycle counter 17 is shown in, for example, FIG.

ΟΜΡΙ IPO II 1

As shown in A, this output is differentiated by the differentiating circuit 18, and for example, its rise] 9 pulse (Fig. 6B) is extracted. This rise] 5 pulses, for example, from a monostable multivibrator V) 吃 Draft correction 0 Ultrasound at a depth equal to the water surface where the transducer 23 is attached at the path 19 This is converted to a pulse of time Ti shown in Fig. 6C, which is the time corresponding to the pulse propagation time. The converted output is supplied to a transmission trigger generating circuit 21 to obtain a trigger signal delayed by a differential pulse (FIG. 6B) as shown in FIG. 6D).

 The transmitter 22 is driven by the trigger signal, and its output] 9 excites the transducer 23, and the ultrasonic pulse is emitted toward the sea floor. Based on the transmission of the ultrasonic pulse, the reflected signal is received by the transmitter / receiver 23] and received by the receiver 24. For example, as shown in FIG. A school of fish! ) And the seafloor reflected signal 27 are received. The output of the receiver 24 is converted by the AD conversion circuit 28 into, for example, a parallel 4-bit digital signal. ) Supplied to a plurality of data acquisition units.

 When a normal display data capture unit 31, a partially enlarged display data capture unit 32, and a seabed enlarged display data capture unit 33 are provided, these data capture units 31,

The output of the A / D conversion circuit 28 is supplied to the data acquisition memories 34, 35, 36 of 32, 33, respectively.

In this embodiment, the information of the net height gauge can be further displayed, and as shown in FIG. A fish finder transmitter / receiver 23 is attached to the bottom, and this transmits and receives ultrasonic waves as described above. At the same time, the fish net 39 is pulled by the rope 38, and the net height meter 41 is attached to the upper part near the opening of this fish net. Ultrasonic waves are transmitted to the upper and lower sides of the net height gauge 41, and the reflected waves are received, and the received signal is transmitted to the receiver of the fishing boat 37 using the ultrasonic waves as carrier waves. Transmitted to 42.

 That is, in FIG. 3 to FIG. 5, the net height meter 41 is received by the receiver 43 of the receiver 42. The upper detection signal portion and the lower detection signal portion in the received signal are separated by data acquisition sections 44 and 45, respectively. The signals received by the receiver 42 and j? Are converted into digital signals by the AD conversion circuit 48 and supplied to the data fetch memories 46 and 47, respectively.

In the normal display data capturing section 31, the gate signal generating circuit 50 is driven by the pulse from the differentiating circuit 18 as shown in FIG. 6F to generate a gate signal, and this gate signal is generated. 9) The shift pulse power counter 49 is controlled to start counting operation, and the counter 49 starts counting.)) The output pulse of the range divider 13 Is counted. The count value of the shift pulse counter 49 is decoded by the decoder 51, and the output terminal of the decoder at an appropriate interval is selected by the shift selection switch 52. I do. Sheet oice selected scan I Tsu switch 52 Deco over da 51 side of the selected fixed terminal is pulse P _s which is shifted sequentially phase by 50 in terms of the detection distance of the ultrasonic eg Remind as in FIG. 6 G Obtained in the

OMPI

NO WIPO '' One of ls e P _s shea be selected at oice selected scan I Tsu switch 52 gates one preparative signal generating circuit 53 is driven, the sixth Ni gate signal Let 's are shown in FIG H Kitareyo occurs . For example, with the range switch 14 set to 0 to 100, the second pulse is selected by the shift selection switch 52]). This is the case when the depth range between m is detected. The shift pulse power counter 49 counts a predetermined number, and the time from when this power counter 49 becomes full force until the next trigger pulse occurs. At least one shift distance in between, in this example 100 minutes, is allowed to occur. The output of the gate signal from the gate signal generating circuit 50 is stopped by this full power output, and the output is shifted to a low level as shown in FIG. 6F. The counting operation of the top pulse counter 49 stops. The gate signal generation circuit 50 is, for example, a flip-flop circuit, and is set in accordance with the output of the differentiating circuit 18. The output of Luscounter 49! ) Reset. Other gate signal generation circuits are configured in the same manner as the gate signal generation circuit 50.

 When the output of the gate signal generation circuit 53 becomes a high level, the frequency dividing circuit 54 and the data acquisition power center 55 are activated! ), The frequency divider 54 further divides the output of the range divider 13, and the divided output is counted by the data capture counter 55. The output of the frequency dividing circuit 54 is supplied to the data acquisition memory 34 via the OR circuit 56, and the output of the AD conversion circuit 28 is acquired via the OR circuit 57 for each pulse.

(OMPI Written to memory 34. The counter 55 has the number of pixels of one display line in the color cathode-ray tube display 82, for example, 256 pixels does not make a full count]? The signal generation circuit 53 is controlled, and its output is at a low level. Therefore, the operation of the frequency dividing circuit 54 and the data acquisition counter 55 stops. That is, the data acquisition pulse is generated from the frequency dividing circuit 54 as shown in FIG. 6I, and the data acquisition memory 34 is, for example, a shift register and the data acquisition is performed. Data for 256 pulses is captured.

 In the partially magnified display data acquisition section 32, while the data acquisition counter 55 is operating, pinch! ) Normal display data The counting content of the counter 55 is supplied to the decoder 58 in order to enlarge and display an arbitrary section while the data is being captured in the data capture section 31. One of the output terminals of the decoder 58 is selected by the enlargement position selection switch 59. For example, the interval of the output gate signal of the gate signal generation circuit 53 is divided into five equal parts, and the pulses whose phases are sequentially shifted corresponding to each one of the five equal parts are the five positions of the enlargement position selection switch 59. The fixed terminal is obtained as shown in Fig. 6J, and one of its pulses is selected by switch 59. The output of the gate signal generating circuit 61 is at a high level as shown in Fig. 6K.], And the output of the dividing circuit 62 and the data acquisition The counter 63 is brought into the operating state. The output pulse from the reference oscillator 12 is supplied to the frequency dividing circuit 62, and the frequency dividing circuit 62 uses the expansion width selection switch 64.]

O PI And the enlarged width is big, pinch! ) When the enlargement factor is increased, the frequency division ratio is small, so that a high-frequency output can be obtained. This pulse is counted by the data acquisition counter 63 and drives the data acquisition memory 35 through the OR circuit 65. The output of the AD conversion circuit 28 passes through the OR circuit 67. The data is read into the memory 35.

 The data acquisition counter 63 is the same as the counter 55 in the form of a full count at, for example, 256 bits]), depending on the output of the full count]? G The signal generation circuit 61 is controlled, and the output is low.], The frequency divider 62 and the data capture counter 63 are both inoperative. In this way, while the output of the gate signal generation circuit 61 (FIG. 6K) is at a high level, the AD-converted output of the received signal corresponds to 256 sample information. The information is read into the data acquisition memory 35 as pixel information for one display line.

In the seafloor enlarged display data acquiring section 33, the gate signal generating circuit 68 is driven by the differential pulse shown in FIG. 6B from the differential circuit 18 and the output signal (FIG. 6L) is output. The frequency dividing circuit 69 is set to the operating state. The frequency dividing circuit 69 divides the frequency of the reference signal from the reference oscillator 12, and the frequency dividing ratio is changed in accordance with the magnification set by the magnification selecting switch 71. When the frequency is to be greatly expanded similarly to the frequency dividing circuit 62, a pulse having a small frequency dividing ratio and a high speed is output. The output of the divider circuit 69 drives the data acquisition memory 36 through the OR circuit 72, and the output of the AD converter circuit 28 is read for each pulse. Be received. The capacity of the data acquisition memory 36 is the same as that of the memories 34 and 35, so that the memory is full of 256 pulses. Every time new data is written, the oldest data is lost sequentially.

 On the other hand, the output of the receiver 24 is also supplied to a submarine signal detection circuit 73, and this circuit 73 can be of a known type (for example, a conventional one). A signal larger than a predetermined level before sending the oscillation pulse is detected as a seafloor signal. This submarine signal is a pulse as shown in FIG. 6M, whereby the gate signal generating circuit 68 is controlled to output a low level signal! ), The operation of the frequency dividing circuit 69 stops, and the data fetching operation of the data fetching memory 36 also stops. The data acquired at this time is the one with the newest reflection signal on the sea floor. In order to always capture such data, the sea floor is always in a fixed position on the display line.], The sea bottom line is displayed as a straight line, and the part above the sea bottom is divided by the frequency divider 69. The display is enlarged according to the circumference ratio.

 As described above, the data fetched into the data fetching memories 34, 35, 36, 46, 47 of the data fetching section are selectively read means 74 to 78 provided corresponding thereto. The data is taken into the common buffer memory 79 according to the selected state in. The data stored in the memory 79 is transferred to the main memory 81, and the main memory 81 is repeatedly read out and supplied to the cathode ray tube display 82 to generate an image. Is displayed. Cathode ray tube display

O PI

, — Wi n Control of the container 82 is performed as follows. The output signal of 5 is divided by the frequency dividing circuit 84 up to the line (horizontal) scanning cycle of the cathode ray tube display 82, and the output is supplied to the line (flat) synchronization signal generating circuit 85. Is supplied to display 82. Further, the output of the frequency dividing circuit 84 is supplied to the same (vertical) signal generating circuit 86, which generates a synchronous signal by dividing the frequency. The synchronous signal is supplied to the display 82. Information corresponding to one display line of the indicator 82 is stored in the buffer memory 79, and the information of the one display line is transferred to the main memory 81 as described above.

 The data from the data acquisition unit is transferred to the buffer memory 79 on the basis of the click of the display 82. Therefore, the output of the data acquisition counter 55 and the output pulse of the surface synchronization signal generation circuit 86 are supplied to the synchronization selection circuit 87. The surface synchronization pulse signal of FIG. 6 is, for example, N in FIG. 6], and the full count output of the data-in-conversion counter 55, that is, the signal next to the trailing edge of the signal of FIG. The surface synchronization pulse is selected as shown in Fig.6.

The synchronous selection circuit 87 is a JK flip-flop as shown in Fig. 8), and the write completion signal from the data acquisition counter 55 is a JK flip-flop. . FFi the Q terminal of the supply of full Clip off Lock Bed FFi to J terminals Ru high bets]), this is re supplied to the JK full Clip off port Tsu Bed FF ₂ clauses Li Ryo terminal CL The flip-flop FF ₂ is in an operable state. The flip-flop FF ₂ has a surface synchronization signal generation circuit connected to the J terminal of the flip-flop FF _2.

O

'' WIP Since the plane synchronization pulse is supplied from the above, the plane synchronization pulse following the above write end pulse is used.]?

FF ₂ is set and the output of the Q terminal is set to a high level.]], And the output is supplied to the clear terminal CL of the flip-flop FF _{3 and} the flip-flop is connected to the flip-flop. The flop is operational. Unfavorable Tsu Bed off Lock blanking plane to J terminals of the FF ₃ synchronization ls e inversion. Given ls e mosquitoes in your] ?, the rising wife]? Is off Li Tsu Pufu Lock-flops FF ₃ Gase Tsu door at the trailing edge of the surface synchronous Pulse, due to the output 1) off Li Tsu Pufu Lock-flops FFi and F F2 is re-cell Tsu door, by the this]? off Clip off Lock-flops FF ₂ of the Q terminal is in the low-les-bell] 9, off Li Tsu blanking off opening Tsu Breakfast to the Q terminal of the FF ₃ is low Les bell, Pulse of the trailing edge position of the surface synchronous Pulse immediately following this Q terminal by writing end signal ing in and give Raretako.

 The gate signal generation circuit 88 is driven by the selected surface synchronization pulse, and a signal as shown in FIG. 6P is generated. Then, the data read counter 91 is activated. The signal of the line scanning frequency from the frequency dividing circuit 84 is supplied to the frequency dividing circuit 89, and the frequency dividing ratio of the frequency dividing circuit 89 is changed by selecting the display width selection switch 92.

 The four fixed terminals of the switch 92 are, for example, four from a to d. When the b is connected to a, the dividing ratio of the dividing circuit 89 is 1Z8, and when it is connected to b, the dividing ratio is 1Z8. The ratio is 14; when it is connected to c, the division ratio is 1/2, and when it is connected to d, it is not connected to the frequency divider 89.

OMPI This is the case when it is selected. Each negative output of the fixed terminals a to c is supplied to the gate circuit 93, and the gate signal generation circuit 88 is cleared by the output. The output of the gate signal generation circuit 88 is held at a low level. When terminal a is selected on the display width selection switch 92, one selected data is displayed as one display line of the color cathode ray tube display 82, that is, the ?? When the terminal b is selected, it is displayed in the width of 12; when the terminal c is selected, it is displayed in the width of 1Z4.

 The divided output of the divider circuit 89 is counted by the data readout counter 91, and this counter 91 is full of 256 in the same way as the data acquisition counter 55 etc. It is a count. As described above, the display width selection switch 92 also serves as a switch for selecting whether or not to select and read the selection means. When this switch 92 is located at the terminal d. In the case where this selective reading means is not selected, the output of the gate signal generating circuit 88 does not become high. However, when the selective reading means is selected, the switch 92 is connected to one of the terminals a to c, a frequency-divided output is obtained from the frequency-divider circuit 89, and the output pulse Not only the data read counter 91 counts, but also the pulse drives the selective read means 74 and the corresponding data acquisition memory 34, and the data is read. The read data is supplied to a buffer memory 79 through an OR circuit 94.

Writing to the buffer memory 79 is the output of the frequency divider 89. Synchronized with the slowest panel in the pulse. That is, the pulse from the frequency dividing circuit 84 is frequency-divided by 1 in the frequency dividing circuit 95, and is supplied to the buffer memory 79 through the frequency dividing output kao end circuit 96. Control?]? Data from OR circuit 94 is written to buffer memory 79. In order to control this writing, the output of the synchronous selection circuit 87 is also supplied to the gate signal generation circuit 97, and this is the case! A gate signal is generated as shown in FIG. 6Q, and this gate signal is output.]? The frequency divider 95 and the counter 98 are in the operating state! ? The counter 98 counts the output of the frequency dividing circuit 95, and when this counts a predetermined number, in this example, 256, the output of the counter 98 controls the i? The level is low.

 The selective reading means 75, 76, 77, and 78 have almost the same configuration as the selective reading means 74.] Therefore, the gate signal generating circuit 88, the frequency dividing circuit 89, and the data reading counter respectively. 91, a display width selection switch 92, and an OR circuit 93, and these are similarly connected. A selection circuit 99 is provided for each of the synchronous selection circuits 87]). The selection circuits 99 of the selection reading means 75 to 78 are sequentially connected in cascade, and a synchronization selection circuit 87 is connected to the preceding stage. The output of the OR circuit 93 is supplied to the selection circuit 99 of the next stage via the inverter 101, and further, the output and gate of the data read counter 91 indicating that reading has been completed. The output of the signal generation circuit 88 is also supplied to the selection circuit 99 in the next stage.

 As shown in Fig. 9, the selection circuit 99 is an inverter in the previous stage.

OMPI WIPO When loi's output is low level, it's boring! When the display width selection switch 92 in the previous stage is connected to any of the terminals a to c, the gate 102 is closed, and therefore the synchronization detection circuit 87 of the preceding stage selection reading means or The output of the selection circuit 99 cannot pass through the gate 102. Then, the display width selection switch is selected for the terminal d, that is, the output of the inverter 101 of the selective reading means when the selective reading means is hardly selected. The gate 102 is opened and the start signal from the synchronous selection circuit 87 in the case of the selection circuit 99 or the selection reading means 75 in the preceding stage is passed through the gate 102, and Output from selection circuit 99 through OR gate 103

 On the other hand, when the display width selection switch 92 is selected to any of the terminals a to c, the gate 102 is closed as described above, and the gate 102 is closed by the output of the gate signal generation circuit 88 in the preceding stage. ]? Gate 104 is opened. End of data reading counter 91! ) Is output through a gate 104 and further through an OR gate 103. In other words, if the selective reading means is not selected, the start signal from the previous stage is sent to the next stage through gates 102 and 103 as the start signal, and the display width selection switch 92 is connected to the terminal a. When any one of the following is selected, the full count output of the data read counter 91 is supplied to the next stage as a start signal.

 For example, the start signal is given as shown in FIG. 10A, and the output of the 9-gate signal generating circuit 88 is as shown in FIG. 10B.

O PI When the high level and the display width selection switch 92 are connected to the terminal a, the frequency division ratio of the frequency dividing circuit 89 is large, and the data reading is performed. If the gate signal from the gate signal generation circuit 88 is completed as shown in Fig. 10B, the display width is selected. When the switch 92 is connected to the terminal b, the frequency division ratio of the frequency dividing circuit 89 is 1/4, so that the output frequency is set to the display width selection switch -92 to the terminal a. The output of the counter 91 becomes full count at twice the speed when connected, and the output width of the gate signal generation circuit 88 is as shown in Fig. 10C. As shown in Fig. 10B, it is 1-No.2.

Now, assuming that the selection switch 92 is set to the terminal b in the selection reading means 74 and the selection switch 92 is connected to the terminal c in the selection reading means 75, The full-count output of the preceding data read counter 91 passes through the gate 104 of the selection circuit 99 of the selection read means 75 and the output of the gate signal generation circuit 88 of the previous stage. Since the frequency division ratio of the frequency dividing circuit 89 is set to 1 Z2, the data reading power of the selective reading means 74 at this time is set to 91. The counter 91 of the selective reading means 75 becomes a full count at twice the counting speed of the gate, and the output signal of the gate signal generation circuit 88 becomes low as shown in FIG. 10D. Be a bell. At the end of this signal], the selective reading means 76 is driven, and if the display width selecting switch 92 is set to the terminal c, the gate signal generating circuit 88 similarly operates at the 10th level. Outputs a signal as shown in Figure E. O

 As described above, the frequency dividing circuit 95 is selected to be the same as the case where the frequency dividing ratio in the frequency dividing circuit 89 is greater, and the full count of the counter 98 is the data read count. The write time to the buffer memory 79 is set to the full width terminal a in the display width selection switch 92 shown in FIG. It is the same as the length of the gate signal in the case. Therefore, when the display width selection switch 92 of the selective reading means 74, 75, 76 is set to the terminals b, c, c, respectively, the gate signals of the selective reading means 74, 75, 76 are generated. The outputs shown in FIGS. 10C, 10D and 10E are generated from the circuit 88, and during these periods, all the data of the corresponding data acquisition memories 34, 35 and 36 are read out and buffered. Written to memory 79. As shown in FIG. 10F, the contents of the data acquisition memory 34 are written in the buffer memory 79 as 105 in the 1Z2 portion as shown in FIG. 10F, and the contents of the memories 35 and 36 are written. Each content is written as 1Z4 parts 106 and 107, respectively. Actually, since the capacities of the data fetch memory 34 to 36 and the buffer memory 79 are the same, depending on the compression ratio when writing to the buffer memory 79, The data is skipped over and written to the buffer memory 79.

In this way, the information of one display line of the indicator 82 moved to the buffer memory 79 is moved to the main memory 81. The main memory 81 is, for example, a shift register having a capacity of one screen of the CRT display 82. Output of reference oscillator 83 Is supplied to the clock generation circuit 111, and this is the clock of 9). The main memory 81 is shifted, and the output thereof is supplied to the cathode ray tube display 82. At the same time, it is returned to the main memory 81 through the gate 112 and further through the gate 113. In this example, the one-line scanning line of the cathode ray tube display 82 is used as one display line, and the data from the data acquisition unit is stored in the buffer memory 79. When the transfer is completed, the counter has 98 power;

 The output (FIG. 11A :) is also given to the gate signal generating circuit 114, and a gate signal is obtained as shown in FIG. 11B. This signal is provided to gate 115 through gate 309, which is opened and the output of buffer memory 79 is passed through gates 311, 312, 115, 113. The main memory 81 can be supplied first. Gate signal generation circuit 114] The frequency divider circuit 116 and the power counter 117 are activated by the gate signal of j9. The output of the reference oscillator 83 is divided by the frequency divider circuit 116. After that, a clock signal having the same speed as the clock signal of the clock generation circuit .111 is obtained. The clock signal is sequentially passed through an OR circuit 96 and given as a read clock of the buffer memory 79. Therefore, the read clock from the buffer memory 79 and the write clock of the main memory 81 are synchronized.

When the power counter 117 counts pixels for one scanning line, in this example, 256 pixels, it becomes a full count, and the gate signal generation circuit 114 is controlled and controlled. When the output is at a low level, the operation of the divider circuit 116 and the counter 117 stops. Cau The output of the counter 98 is also supplied to a gate signal generating circuit 118, which outputs a high level as shown in FIG. The signal of the line scanning frequency from the frequency divider 8 is measured by the power counter 119. When the power counter 119 counts the number of scanning lines in one screen of the display unit 82, it counts as a full count, and as a result, the output of the gate signal generating circuit 118 becomes low. j ?, the operation of the counter 119 also stops. Therefore, a high level output of one screen length as shown in Fig. 11C can be obtained from the gate signal generation circuit 1: L8. A logical product of this and an output obtained by inverting the output shown in FIG. 11B of the gate signal generation circuit 114 by the inverter 121 is obtained by the gate circuit 122, and this is the same. The signal shown in Fig. 11D is obtained. The gate 123 is opened by this signal, and the output of the main memory 81 is fed back to the main memory 81 through the delay circuit 124 corresponding to one line, and further through the gates 123 and 113. .

 In this way, when new information is input to the main memory 81, the new information in the main memory 81 is delayed. The signal is returned to the main memory 81 with a delay of one scanning line by the circuit 124. The gate time 123 is closed after the pixel scanning period after the transfer of information from the buffer buffer 79 to the main memory starts after the gate circuit 115 is opened. You. Therefore, when the information of the buffer memory 79 is transferred to the main memory 81, the information of the old one is transferred to the delay circuit 124, and the information of the main memory 8 is transferred to the delay circuit 124.

O PI When deleted from For the gate 112, the signal shown in FIG. 11E obtained by inverting the output of the gate signal generation circuit 118 by the inverter 125 is given through the gate 313, and the buffer Only the gate 112 is open except for the surface scanning period in which information is transferred from the memory 79 to the main memory 81.

 The plane synchronizing signal and the line synchronizing signal are supplied to the power generation circuit 111, and the generation of the power generation signal is stopped in the return section of the electronic beam of the display 82.

As described above, the cathode ray tube display 82 is a power color display, and the output of the main memory 81 is supplied to the color conversion circuit 177. The color conversion circuit 177 outputs a color signal corresponding to the level of the digital information input thereto, and the amplitude (for controlling the electron gun for controlling the red color of the display 82) Intensity) 1 terminal Ri, amplitude 2 terminal R ₂ , furthermore, amplitude 1 terminal Gi controlling the green color, amplitude 2 terminal G ₂ , and blue controlling the amplitude 1 terminal, 2 amplitude terminal have a B _2, depending on the de-di data le information input of the main Note Li 81 or al, which like the six outputs any one or two of the terminals arise. In order to further increase the number of types of colors, control is performed for a bright case and a dark case even for the same color. That is, the least significant bit of the input digital information is supplied to the luminance control terminal of the display 82. Output four bits Bok information Bd main Note Li 81, Be, Bb, the relationship between the output terminal of B _a and force La chromatography converter 177 is in a relationship Ru Remind as in Figure 12. Such a color conversion circuit 177 receives the digital input from the main memory in the relation shown in FIG.

OMPI

WIPO For example, by forming a die matrix circuit so that the output of the shifter is generated, it is easily achieved. The least significant bit B _a is the rather dark of 0 to varying luminance brighter cathode ray tube when the 1. As a result, in this example, the reflection signal 1111 of a strong level such as from the sea floor is displayed in red, the non-reflection state 0000 is actually displayed, and the reflection signal 1010 of an intermediate level such as from a school of fish is yellow. Is displayed on the screen and the display becomes relatively conspicuous.

Next, the acquisition of data from the net height meter is described. As described with reference to Fig. 7, the altimeter is detected near the opening of the fishnet 39 in the upper and lower parts of the altimeter 41 in a time sharing manner. For example, as shown in Fig. 13, the upper detection section _Tu and the lower detection section T appear alternately, and the lower terminal section T is longer so that these sections can be distinguished. The information of this net height meter] 9 is given as the above-mentioned pulses Psu and Ps indicating the transmission trigger as negative pulses, whereas the reflected signals 128 of the school of fish and the sea floor are obtained. The reflected signal 129 etc. is given as a positive pulse.

 The upper synchronization pulse Psu is detected by the upper synchronization detection circuit 130 in FIG. 4, and the lower synchronization pulse Ps is detected by the lower synchronization detection circuit 131. Since the detection distance of the net height meter is relatively short, the transmission trigger period is also short, so if the data acquisition to this net height meter is completed after the data acquisition to the fish finder has been completed. Before the data is fetched to the main memory 81, the contents of the data fetch memory for the net altimeter are in the middle.

(O PI It may be rewritten. Therefore, when the output of the counter 98 indicating that the data has been transferred to the buffer memory 79 is obtained, the synchronization pulses Psu and Pst immediately after that are detected. The subsequent data is loaded into the data loading memories 46 and 47, respectively.

 That is, in the upper data acquisition section 44, the upper synchronizing pulse Psu immediately after the output pulse of the D power counter 98 is detected by the synchronizing selection circuit 132, and the gate signal generation time is determined by the output. The output of road 133 is set to high level. Depending on the output]), the frequency divider circuit 134 and the power counter 135 are brought into the operating state. The frequency division ratio of the frequency dividing circuit 134 is changed by the write width setting switch 136, and the signal from the reference oscillator 12 is divided and supplied to the counter 135. When the counter 135 counts the number of pixels of one display line, that is, 256, the output of the counter 135 controls the output of the gate signal generation circuit .133 to a low level. The operation of the frequency divider circuit 134 and the counter 135 is stopped.

The output of the divider circuit 134 is supplied to an up-counter 137 and up-counted, and the contents of the up-counter 137 are deleted. As an address, the output of the AD conversion circuit 48 for digitally converting the output of the receiver 42 to the net height meter is written to the data acquisition memory 46. The data capture memory 46 is a so-called random access memory. When taking out the data from the memory 46, j is selected. When the selection reading means 77 is selected, the output of the frequency dividing circuit 89 is sent to the up / down counter 137. Down-counting and depending on its content Read the output of memory 46. Tsuma! ) The data written in this way is read from the most recent data, and the data order is reversed. This is because the detection signal for the upper side of the altimeter is a reflection signal from an object that is closer to the sea surface when the oscillation trigger is later and the received information is slower, so that it is displayed accordingly. .

 Similarly, for the lower detection data acquisition unit 45 of the net height meter, the upper synchronization pulse when the information following the upper synchronization pulse Psu is stored in the data acquisition memory 46 The sync pulse Ps immediately after the pulse Psu is detected by the sync detection circuit 138, and the output of the gate signal generation circuit 139 is set to a high level by the power of the sync detection circuit 138, and the frequency is divided by the frequency divider circuit 141 and 'The counter 142 is set to the operating state, and the frequency of the signal from the reference oscillator 12 is divided by the frequency dividing circuit 141 and supplied to the counter 142. The frequency division ratio is changed by the setting of the switch 143, and the frequency division output drives the data acquisition memory 47 via the OR circuit 144, and the output of the AD conversion circuit 48 is written into this. .

 In this way, the lower detection information is written into the data acquisition memory 47, and the counter 142 becomes a full count when the number of pixels for one display line is obtained. Thus, the gate signal generation circuit 139 is controlled, and its output is set to a low level to stop the operation. The data of the data fetch memory 47 is read out by the selective reading means 78.

Next, the operation of the various types of display by the above-described fish finder will be described with reference to FIG. Figure 14 The line scanning direction of the cathode ray tube display 82 is up and down, and the rightmost position 1 51 is the newest information display position. ??, and the oldest information display is the leftmost position. It is an example displayed so that it becomes 1 52. In contrast to the rightmost display on this display screen, the oldest display on the leftmost is the information 30 minutes ago, and in this 30 minutes ago, the range switch 14 is set to 800, When only 74 is selected as the selective reading means, a seafloor display 153, a school of fish display 154, and an oscillation line 155 appear. Depth scales 156 are displayed every 100 in the figure. Further, at the bottom of the display screen, a time scale 157 is displayed as a dot, for example, every minute.

 The display in Fig. 14 shows the case where the display of the detection information in the range of 0 to 800 and the enlarged display of the 400 to 500 parts of the display are displayed in parallel 19 minutes before the present. To select the enlargement range of 400 to 500, select the output of the decoder 58 with the enlargement position selection switch 59, and select the enlargement width, that is, 100, by using the enlargement width selection switch 64. I do. The selection reading means 74 and 75 are selected, and the display width selection switches are selected by the selection reading means 74 and 75 so that these displays are displayed on the upper half and the lower half of the display surface, respectively. The switch 92 is connected to the terminal b.

 In this case, information 0 to 800 is captured as one display line segment in the data capture memory 34 as in the previous case, and the data capture memory 35 stores the information. The part of 400 to 500 m inside is taken in as one display line segment. Selective read

 OMPI

L Lightning ^Q The contents of the data acquisition memory 34 are compressed by the storage means 74 and written into the first half of the buffer memory 79, the right half in the figure, and the data acquisition memory 35 After that, the content is compressed and taken in half. Therefore, as shown in FIG. 14, the seabed is displayed as 161 and the fish school power 162, and the enlarged view is shown as the seabed 163 and the school of fish 164 in an enlarged manner. The depth scale 156 is represented by being compressed as the depth scale 160.

 Further, the output of the gate signal generation circuit 61 indicating this enlarged position is supplied to the enlarged mark generator 170, and the position corresponding to the rise of the gate signal of the gate signal generation circuit 61 and the fall])) Then, a digital signal corresponding to the display color (for example, white) is taken into the data taking-in memory 34 through the check circuit 57. [9] An enlarged position display line 165 indicating the 9 enlarged position is displayed, indicating that this portion is enlarged and displayed below. Also, according to the output of the gate signal generation circuit 61]) The enlarged depth mark generator 166 operates, and the enlarged depth mark generator 166 divides the output of the range frequency divider 13 and enlarges the display. A depth mark of the part is generated, and the output is written to the data acquisition memory 35 via the OR circuit 67 as a digital signal indicating a level corresponding to the display color. As a result, the enlargement-depth mark 167 is displayed on the display.

In addition, the output of the data reading counter 91 of the selective reading means 74 is an OR circuit to form a boundary 168 indicating the boundary between the normal display of the upper half of the octopus and the enlarged display of the lower half. Update via 169 Then, the data is written to the buffer memory 79 via the OR circuit 94. Similarly, when the selective readout means 74 to 76 is selected, the signal indicating the boundary of the display is the data readout power of the selective readout means. The output of the counter 91 is supplied to the OR circuit 169. This is written to buffer memory 79 as a boundary signal.

 Furthermore, in this example, the normal display is displayed 11 minutes before the current time, and the enlargement ratio selection switch 64 is selected as it is, and the enlargement ratio is further increased, the width is enlarged 50 times, and the enlargement position is selected. This is the case when switch 59 is selected and the display between 550 m and 600 »z is enlarged.

 As a display example, as shown in Fig. 15, the normal display of 0 to 600 m is selected by the range switch 14 20 minutes before the current time, and then displayed by the range switch 14. The part is selected by the enlargement position selection switch 59, and it can be selected and displayed by selecting and reading means 74. and 75.)), the submarine display 161 and the fish school display 162 are displayed in the enlarged display. They are displayed as a seafloor display 163 and a fish school display 164, respectively. The selection reading means 74 and the selection reading means 76 for the seafloor expansion, and the selection reading means 77 and 78 for the net height meter information are selected, and the display width selection switches 92 are respectively connected to the terminals c. Set to.

 In this case, the operation described above is performed.] The buffer memory 79 stores 1/4 of the information of the data acquisition memory 34 and the data acquisition memories 36, 46, and 47, respectively. Each file is compressed and written. Therefore, it is normally displayed on the display screen in the upper part of 14

OMPI The seabed display 171 and the fish school display 172 are displayed, and the display from the seafloor enlarged data acquisition unit is displayed as a straight line 173 indicating the seafloor in the next 1Z4 area. A display 174 corresponding to the fish display 172 appears thereon. In addition, the upper part of the net gauge is displayed in the upper half of the lower half of the display screen, a display 175 indicating the position of the net gauge and a school of fish 176 are displayed thereon, and the lower part is further displayed. Is displayed according to the lower information of the net height meter.] 3 The seabed display 179 and the fish school display 178 are displayed.

 Next, the rewriting speed is displayed at the upper portion of the screen at a normal speed, that is, every time a detection signal is obtained and data is written to the buffer memory 79, the data is written to the main memory 81. Data is written to the buffer memory 79 multiple times at the bottom of the screen, and the last data is moved to the main memory. The normal display state where the image moves quickly will be shown, but the specific example for displaying the lower part of the screen so that the moving speed is extremely slow will be explained.o

Displaying the moving speed of the display image differently depending on the area of the screen in this way is referred to as different speed display. Displaying all screens at the same speed is called normal display. A different speed switching switch 206 for switching between the normal display and the different speed display is provided as shown in Fig. 5. When this switch is on, the normal display is provided. And, through the switch 206, the AND gate 322 Input side is grounded. Therefore, the output of AND gate 322 is at low level]), and its output is inverted at inverter 324. It is supplied as high level to gates 122 and 309, and these gates Is opened.

 In this state, as described above, when no new data is written to the buffer memory 79, the data is output through the gate 313 by the output of the inverter 125. The output of the main memory 81 is circulated through the main memory 81, and a still image appears on the display screen. Each time the writing of new data to the buffer memory 79 is completed, the output of the gate 309 is output.]? The gate 115 is opened, and the section buffer memory 79 of the one-line scanning line is opened. The output of the gate signal generator 118 is written to the main memory 81, and the output of the gate signal generation circuit 118 is connected to the gate 123 immediately after that until the end of the surface scan. The information is opened by the output of step 122, the return to the main memory 81 is performed during that time, new information is taken in, and the oldest information is deleted. Normal display is performed in this way.

 To perform the different speed display, turn off the different speed switch 206. In this state, the gate 322 is given a high level through the switch 206. The output of the clock generating circuit 111 is supplied to the frequency dividing circuit 325, and a pulse having a half pulse width is obtained from the output of the frequency dividing circuit 325 with the line scanning line as a cycle. The frequency dividing circuit 325 is activated by the output of the gate signal generating circuit 118, and operates from the front green of the output, that is, in synchronization with the rise of the output in FIG. G

OMPI The output shown in Fig. 7 is obtained.

 Its output is provided to AND gate 322. Accordingly, the signal shown in FIG. 11C rises based on the completion of the writing to the buffer end memory 79] 9, and from that point on, the output of the frequency divider 325 is low. Therefore, the output of the gate 322 is also at a low level, which means that during the half of the three-line scanning period, and in this embodiment, during the half of the 256 picture elements, the normal display is performed as described above. The new information from buffer memory 79 is input during the half period of the line scan line, that is, during the period corresponding to the upper half of the display line. After that, the output of the frequency divider 325 is at a high level.

 In addition, if the explanation goes back and forth, if the display screen is divided into upper and lower parts and the upper part is displayed as normal, and the lower part is made as low-speed transmission, the output of the low-speed transmission that determines the low-speed transmission))? When writing to buffer memory 79 is completed at a high level, only the first half of the data is transferred to main memory 81, and only the upper half in the display line diagram. Is rewritten. That is, the data for the upper half of the display screen is rewritten each time data is written to the buffer memory 79.

 [Low-speed transmission]) The decision circuit 326 is a circuit for dividing the output of the gate signal generation circuit 118, and its division ratio is changed by the selection of the selection switch 327. For example, as shown in FIG. 16, a low-level output is obtained once every four times of the output of the gate signal generation circuit 118.

O PI WIPO Therefore, when the writing to the buffer memory 79 is completed four times, one of them is sent at a low speed.] Since the output of the decision circuit 326 is at a low level, the gate 322 Is also low during the image scanning period. At that time, the same state as when the different speed switching switch 206 is turned on is set, and all the data in the buffer memory 79 is written to the main memory 81, and one data is stored in the main memory 81. All display lines are new] ?, that is, the contents at the bottom of the display screen are also rewritten. In this way, the lower part of the display screen is rewritten once every four times compared to the upper part, for example, ¾j9, and its transmission] 5 The speed is 1/4 ₀

 When the buffer memory 79 is rewritten, the writing is completed and the writing to the main memory 81 is performed during the first low level of the output of the frequency divider 325, and the high level immediately thereafter is written. Since data is supplied to the gate 112 through the bell gate 322 and further through the gate 313, data for the lower side of the display screen is transferred from the main memory 81 to the main memory through the gate 112. It is returned to the library and is preserved without loss.

 In this way, even if the buffer memory 79 is rewritten several times, only one data is supplied to the main memory 81 for the display. Therefore, for example, an image that appears on only one or two of the display lines may be removed from the screen of [Slow feed] ?.

 Therefore, it is preferable to provide the thinning-out correction circuit 328 so as to avoid this. That is, in FIG. 5, the output of the frequency dividing circuit 325 and the output of the different speed switching switch 206 are completed.

OMPI WIPO The output is supplied to gate 331, the output of which is supplied directly to gate 333 and to gate 311 through inverter 332. When the switching switch 206 is off and the output of the frequency divider 325 is high, the output of the gate 331 is high and the gate 311 is closed through the inverter 332. Therefore, the output of buffer memory 79 cannot pass through gate 311. On the other hand, the gate 333 is opened by the output of the gate 331; the output of the OR circuit 94 is decimation-corrected by the decimation circuit 328, and the gate 333 and the gate 312 are output through the gate 312. Supplied to When the display is not performed, the gate 311 is always opened, and the output of the puffing memory 79 is transmitted through the gates 311 and 312 as described above. To 115. In the case where the thinning correction is not performed, the output of the buffer memory 79 is supplied to the gate 115 through the gates 311 and 312 by omitting the thinning correction circuit 328 and the gate 333. The output of the buffer memory 79 is supplied to the gate 115 through the gates 311 and 312 even when the low-speed screen is rewritten.

 As shown in FIG. 17, for example, as shown in FIG. 17, the comparator 334 operates while the output of the low-speed transmission decision circuit 326 is at a high level, and the comparator 334 includes an OR circuit 94. And the output of the delay circuit 335 is supplied. The magnitudes of these two input signals are compared, and if the input from the OR circuit 94 is large, the output of the comparator 334 becomes a high level and the gate 635 force is opened; 94 output gate 635

(O PI In addition, the signal is further supplied to the delay circuit 336 through the expiration gate 636.

 The delay circuits 335 and 336 are, for example, shift registers, which can store picture elements for one display line, and have a capacity of 256 picture elements in this example. The output of the delay circuit 336 is supplied to the gate 333 and is also supplied to the delay circuit 335. In other words, the previous write data is stored in the delay circuit 335. These delay circuits 335 and 336 are synchronously shifted by the output of the frequency dividing circuit 116.

 Comparator 334 compares the new data with the previous data. If the level of the new data is large, the new data is supplied to delay circuit 336, and further The writing to the main memory 81 is performed through the block 333. If the new data is at a lower level than the previous data, the level of the comparator 334 is low and the gate 635 force is closed; the output of the comparator 334 is the inverter 337. 9] is inverted and given to gate 338, which is opened. Therefore, the output of the delay circuit 335 is supplied to the delay circuit 336 through the gates 338 and 636.

Low-speed transmission to delay circuit 336! Multiple times of data is given to the buffer memory 79 until the writing to the side is performed, and the corresponding data portions of the multiple times of data are sequentially compared, and the largest data is obtained. Is stored. The comparator 334 sends at a low speed.]? When the output of the decision circuit 326 is at a low level, it does not operate; at that time, the output of the comparator 334 is at a high level. Only these new data are supplied to the delay circuit 336. The thinning-out correction circuit related to the low-speed transmission]? Display described above can be used regardless of the division of the display screen.

 As described above, according to the device of the present invention, different speeds can be displayed at the upper side and the lower side of the display screen. For example, as shown on the left side of FIG. For example, if the selective reading means is selected so that the display near the sea bottom is displayed at the bottom of the screen, the sending of the display at the top of the screen is delayed. As shown in Fig. 18A, on the display screen of "Slow feed on the upper side" ?, the image of the fish school 162 near the bottom is enlarged not only in the vertical direction but also in the image transfer direction. Image 1 6 2 is displayed at the bottom of the screen.

O o

 In this case, the data is stored in the buffer memory 79 so that the upper side of the screen is a normal display in the depth direction and the lower side is an enlarged display. In this case, the upper side of the screen should be sent at low speed]) and the lower side should be sent at normal speed. In this way, the image is enlarged not only in the depth direction but also in the image transmission direction, so that the image itself can be viewed in the vertical and horizontal directions.

 Similarly, as shown in Fig. 18B, the upper part of the screen is normally displayed in the depth direction, and in the direction of the time axis, that is, in the direction of image transfer] 9, it is sufficiently compressed for a long time! )) The obtained data is displayed, and the lower part is used for normal transmission]), and expanded in the depth direction as necessary.

OMPI Display. For example, in the case of a bottomed fishing boat, the image from the vicinity where the net is passing to the vicinity currently being detected is displayed on the upper part, the detection image immediately below the ship is displayed on the lower side, and The fish school of the detection image can be enlarged and displayed. The lower part of the display is small enough to read the type of fish school, etc., but the upper part is like that. It is possible to display, for example, the detection information obtained over a range of 1000 m to 20000.

 Further, the difference in the moving speed of the image between the upper side and the lower side of the display screen means that the rewriting cycle is different, so for example, the display of the net monitor When the display of the fish finder is displayed, the display of the net monitor enlarges the vicinity of the opening of the net, and the detection period is faster than that of the fish finder. ) The data is updated quickly, but it can be displayed at that high speed. For example, as shown in Fig. 18C, the lower part of the display screen is the display of the net monitor, which updates its data at the net monitor's detection period and updates the time axis. The display is enlarged in the direction. The upper part of the screen is the display of the fish finder, and the screen is rewritten in the detection cycle, and the position of the net monitor is set to the vertical display line 341 as necessary. Can also be displayed.

 In the above description, a normal display is displayed on the upper and lower sides of the screen, and a part of the display is enlarged in the depth direction.

OMPI When displaying the machine and the net monitor, the image sending speed was different between the top and bottom. For exactly the same detection information, normal transmission 1? And low-speed transmission]? Can be displayed at the top and bottom of the screen. For example, as shown in FIG. 19, in each of the data capturing sections 31, 32, 33, 44, and 45, a write pulse is supplied to the data capturing memories 34 to 36 and 46, 47. Selection between the output side of the divider circuits 54, 62, 69, 134 and 141 and the input side of the OR circuits 56, 65, 72, the down-counter 137 and the expiration circuit 144 Switches 342 to 346 are inserted.

 Depending on the switching connection of these switches 342 to 346], each of the frequency dividing circuits 54, 62, 69, 134, and 141 has an OR circuit 56, 65, 72, 144 up-down. Counter 137 can be connected. In the normal operation state, the switching switches 342 to 346 are connected to the frequency dividing circuits 54, 62, 69, 134 and 141, respectively.

The normal speed display and the low speed display are the same; when performing data, for example, to perform normal display, the data selection switching switch 342 of the normal display data acquisition unit is divided by a frequency divider circuit The other data acquisition unit, for example, the data selection switch 343 of the partially enlarged display data acquisition unit 32, is connected to the 54 side and the frequency division circuit of the normal display data acquisition unit Connect to 54 output side. Therefore, if the display width selection switch 92 of the selection reading means 74, 75 is connected to the half-width display position terminal b, the data capture memories 34, 35 are both connected to the frequency dividing circuit 54. jif. WIPO-ichi With the output, the output of the AD conversion circuit 28 is written through the respective talent circuits 57 and 67, respectively, and the contents of the data acquisition memories 34 and 35 are stored in the buffer memory 79 At that time, the same data is stored in the first half and the second half of the buffer memory 79 at that time. Therefore, the same data is displayed on the upper half and the lower half on one display line. Therefore, if the different speed switching switch 206 is turned off, the update of the lower data is delayed as described above, and the upper data is stored in the buffer memory 79 as described above. Every time it is written, it is updated and a fast image transfer.

 In FIG. 19, when new data is written to the main memory 81, the same data is written to the upper and lower sides of the screen. The main memory 81 is rewritten so that the data stored in the display screen is fully displayed at the top and bottom of the display screen, and then both data are displayed. It is also possible to make the feeding speed different.

 For this purpose, for example, as shown in FIG. 20, the output of the frequency dividing circuit 116 is not directly supplied to the OR circuit 96, but is output through the AND gate 301 and the OR gate 302. Supplied to circuit 96. A dividing circuit 211 having a dividing ratio that is twice as fast as the output of the dividing circuit 116, and therefore the dividing ratio is smaller than that of the dividing circuit 116] by 1/2 The same clock as that given to the divider circuit 116 is divided by the divider circuit 211, and the divided output is supplied to the OR gate 302 via the AND gate 208. The frequency divider 211 outputs the output of the gate signal generator 114.

ΟΜΡΙ WT n It is only activated during high levels.

 The output of the terminal 1 K of the control circuit 207 is supplied to the gate 208 and also to the gate 301 through the inverter 209. The output of the delay circuit 124 is supplied to the gate 123 through the gate 303 and the gate 304. Further, in this example, shift registers 212 to 215 for 128 picture elements are provided, which are 1/2 of the number of bits of the delay circuit 124, and the main memory is also provided for these shift registers. Output of branch 81 is branched and supplied. The outputs of these shift registers are applied to gates 123 through AND gates 216-219, respectively, and further through a common OR gate 304.

 The gates 216 to 219 and 303 are controlled to open and close by the outputs of terminals 1A to 1E of the control circuit 207, and the outputs of the terminals 1F to LJ are shifted by the J? The registers 212 to 215 and the delay circuit 124 are shift-controlled. The output of terminal 1K is input to AND gate 331. Further, the output of terminal 1M is provided to AND gate 322.

 When the different speed switching switch 206 is turned off, the level of the terminal 1 K of the control circuit 207 becomes high at the end of the surface synchronization signal immediately after that. However, the terminal 1M is at a low level, and the high level of the terminal 1K is supplied to the gate 301 through the inverter 209 while the high level of the terminal 1K is supplied to the gate 208. Therefore, when the information in the buffer memory 79 is read and supplied to the main memory 81, the read clock is not the output of the frequency divider 116, but the frequency of this circuit. The dividing ratio is one half of the ratio] ?, the dividing circuit

 ΟΜΡΙ

WIPO. The buffer from the divider circuit 211, which outputs a port twice as fast as the output port of 116, is passed through the ports 208, 302, and 96 in succession to the buffer memory. Given to 79. Therefore, during the first half of the line scanning period, the buffer memory 79 is read out, and the information is stored in the main memory 81 at the speed of the clock generation circuit 111, that is, the cathode ray tube display. It is read at the speed of container 82.

In Figure 21 of the Vs is the surface scanning section der after which have established a different speed switching scan I pitch 206 and Off] ?, H _s linear synchronous signal? The line scan period between the V _s of the immediately after Tsu in this scan I Tsu switch 206 is off sequentially Hi, ¾, Ita'3, and the named, is your line scan period Hi control circuit 207 As shown in FIGS. 21F and G, the shift α of the lock cycle α of the lock cycle of the lock generation circuit 111 from the terminals 1F and 1G of The shift pulses are given to the registers 212 and 213, respectively. Therefore, when writing new information from the buffer memory 79 to the main memory 81, the most recent data read from the main memory 81 until then is one bit. The power is stored in the shift registers 212 and 213, respectively. The number of shift stages of these shift registers 212 to 215 is selected to be 128, which is a half of the number of shift stages of the delay circuit 124, or 256.

The Te next line scanning period H ₂ Odor supplied to the terminal 1 H, 1 1 month comfortably Lock sheet oice les Soo data 214 to click "is Remind as in FIG. 21 11, I, 215 of the control circuit 207 Then, the new data read from the main memory 81 is simultaneously written into them. Click in the first half of the period H ₂ to the terminal IF lock generating circuit 111

OMPI A clock having the same speed as that of the clock is given as shown in FIG. 21F, and at the same time, by the gate signal shown in FIG. 21A from terminal 1A. 1) Gate 216 is opened, and the data of the shift register 212 is returned to the main memory 81 through the gates 216, 304, 123, and 113 in order. In the _second half of the period H2, the clock is supplied from the terminal 1G to the shift register 213, and the gate signal shown in FIG. 21B from the terminal 1B is supplied to the gate 217. The contents of the shift register 213 are returned to the main memory 81 through the gate 217. Is at the next line scanning period H ₃ terminal 1 F, 1 G I click lock "occurs, click locks the terminal 1 H Te half smell, FIG. 21 for the gate 218 to the terminal 1 C The gate signal of C generates a clock at terminal II in the latter half, the gate signal of Fig. 21D corresponding to gate 219 at terminal 1D, and the shift register 214 , 215 are returned to the main memory 81 via gates 218, 219. Similarly, the data of one display line is replaced by the display line. The main memory 81 is rewritten so as to be displayed the same in the first half and the second half of the control circuit 207. An example of the control circuit 207 is shown in Fig. 22. The different speed switching switch 206 is a JK flip-flop. The J terminal and the inverted signal of the flip-flop 231 are supplied to the K terminal, respectively. The signal is read at the leading edge of the synchronization signal from the gate signal generation circuit 118 in Fig. 5. Therefore, when the switch 206 is turned off at the time point as shown in Fig. 23A, the Immediately after the counter 98 in Fig. 5

OMPI According to the output (FIG. 23B), the output of the flip-flop 231 is at a high level, which is applied to the gate 234 as well as to the gate 234. The gate 234 is provided with the output power of the flip-flop 233, and the gate 355 is provided with the Q output.

 The Q output force of the flip-flop 231 becomes high as shown in FIG. 23C by the image synchronizing signal immediately after the different-speed switching switch 206 is turned on. This is the output of terminal 1K of control circuit 207. Since this output is inverted and given to the clear terminal of the flip-flop 233, the flip-flop 233 is in the operating state. The signal is supplied from the plane synchronization signal generating circuit 86 in FIG. 3 to the clock terminal of the plane synchronization pulse flip-flop 233 shown in FIG. 23D. Therefore, the Q output of flip-flop 231 is high. * The Q output of flip-flop 233 is high due to the next high-level plane synchronization signal. The output of gate 355 is at a high level as shown in Figure 23E. This is the output of terminal 1M of the control circuit.

As shown in Figure 23F, the output of gate 234 is at a high level as shown in Figure 23F for only one scanning period until terminal 1K is at a high level and ¾j terminal 1M is at a high level. You. The flip-flops 235 to 238 are brought into operation by the output. During this operating state, terminal 1E is low and gate 303 in FIG. 20 is closed, so that the feedback to main memory 81 through delay circuit 124 is one of them. Stopped during the surface scan period The output synchronizing signal of the line synchronizing signal generating circuit 85 shown in FIG. 3 is supplied to the flip-flop 235 shown in FIG. 22 and is divided by 1 to 2 so that the clock from the terminal 242 is The frequency is divided by 12 in the flip-flop 236. This clock is divided by the counter 239 into 1/128, and the divided output is divided by the flip-flop 238 into 1 に 2. The AND output of the Q output of the flip-flop 235 and the line synchronization signal is supplied to the flip-flop 237 and is divided into 1Z2. By combining the outputs of these flip-flops 235 to 238, the waveforms shown in Fig. 21 can be obtained at terminals 1A to lJ.

 Therefore, during the period when the output of the gate 234 is at a high level (Fig. 23F), the image displayed on the entire display screen is compressed vertically and the same image is displayed at the top and bottom of the screen as described above. Will be done.

 Immediately after that, the output of the gate 355, that is, the output of the U terminal 1M is at a high level as shown in Fig. 23E, but this is when the different-speed switching switch 206 is not in use. If this is the case, the state is maintained at a high level. In addition, since the output of the gate 234 is at a low level, the gates 216 to 219 in FIG. 20 are all in a closed state, and the output of the terminal 1M is at a high level. Since this is given to the gate 322, the gate 322 has been described earlier because the output of the gate 322 is low only when the output of the frequency divider 325 is low. Thus, new data is written to the main memory 81. In this case, the output of terminal 1K is at a high level.

 O OMMPPII

Thunder ⁰ Since the writing speed to be written is performed by the output of the frequency divider 211 and the writing to the main memory 81 is performed at half the speed, the information of the buffer memory 79 is displayed on the display screen. Writing to the main memory is performed so that it is compressed and displayed in the upper half of the display line. The display for the lower half of the display line corresponding to the newly written data is held by the switching of the gates 115 and 123 as described above, and the previous data force is retained.

 When the output of the decision circuit 326 goes low, the buffer memory 79 is also read at a high speed at that time-compression is performed on the upper half of the display line. The data is written so that it is displayed, and the data obtained by performing the decimation correction corresponding to the lower half of the display line and corresponding to the upper half of the main memory is read out at a high speed. Is given to the main memory 81, and its data is written in the latter half of the display line. In this way, the image is displayed at the top of the screen. ), Slower image transmission on the lower side]? Speed and ¾] 9, and the same data is displayed with the same compression ratio in the depth direction.

 In the above description, the display line direction of the display screen was divided into upper and lower parts, and the image transmission speeds of the upper part and the lower part were different, but the display screen was, for example, as shown in Fig. 18D. Divide the image into the left and right areas 356 and 357. ) The speed can also be made different. For this purpose, for example, as shown in Fig. 24 showing the parts corresponding to Fig. 5, the first half and the second half of the counting stage of the counter 119 that counts the vertical synchronization signal

OMPI , A low-level output and a high-level output are obtained from a terminal 358, and the signal of this terminal 358 is supplied to a gate 322.

 When the switch 206 is turned off, a low level is applied from the terminal 358 to the gate 322 in the first half of the surface scanning period immediately after the writing to the new buffer memory 79 is completed. If given, its output is low and the data in buffer memory 79 is provided to the main memory as described above. At the end of the first half of the surface scanning period, the terminal 358 goes high, so that the gate 112 is opened by the output of the gate 322, and the transmission to the left half of the screen is stopped. Only the data update for the right half area 357 is performed. However, after the update is performed a plurality of times, the output of the low-speed transmission decision circuit 326 is at a low level, and in this case, the output of the gate 322 is low throughout the one-surface scanning period. Bell. Therefore, new data is written in the right and left areas of the screen, the old data is moved to the old area by one display line, and the data is written in the left area 356. Will also be performed. In this way, the area 356 displays data for a long period of time, and the area 357 is written with new data every time data arrives, so that fast image transmission is performed.

 As shown in Fig. 25, the output of the frequency divider 325, the output of the terminal 358, and the low-speed transmission for Gout 322! When the output of the decision circuit 326 and the output of the different speed switch 206 are supplied, for example, as shown in FIG. 18E, the upper half area 359 and the lower half area 352 of the display screen are respectively Normal image transfer]) speed and

O PI WIPO Thus, the area 351 on the left side of the lower half can be displayed so as to slow down the image feeding speed.

 As described above, the display screen is divided into a plurality of areas, for example, the upper and lower areas, and the display images in these two areas are different from each other, and the moving speed is changed. A description will be given of an apparatus for making the characteristics of the relationship between the detection information level and the detection information level different depending on the divided area. For example, as shown in FIG. 26, the read 4-bit output of the main memory 81 is supplied to a code conversion circuit 361, and the output of the code conversion circuit 361 is converted into a 3-bit code. It is added to the upper 3 bits of the color conversion circuit 177, and the display color is "8 bright and dark". On the other hand, color characteristic selection switching switches 362 and 363 are provided, and these switches have, for example, switching fixed contacts ① to ⑧, and the switching position set by the switching switches is an encoder. Signs 364 and 365 are applied. The encoded output is supplied to a code conversion circuit 361 as a 3-bit code in this example through a switching circuit 366.

 The switching circuit 366 is supplied with a switching signal having a pulse width of half the period of the period of the |) —line scanning period, which is the output of the frequency dividing circuit 84 in FIG. Therefore, the outputs of the encoders 364 and 365 are alternately extracted from the switching circuit 366 in the first half and the second half of the one-line scanning period, and are supplied to the code conversion circuit 361.

 The code conversion circuit 361 is composed of, for example, a read-only memory j), which is composed of four bits of the output of the main memory 81 and three bits of the switching circuit 366]. Given as 3

OMPI WIPO It produces the output of That is, as shown in Fig. 27, the output of the main memory 81 can take the level of 0 to 15, and the output of the encoders 364 and 365 can be any of 1 to 8 If j is selected in switches 362 and 363, linear conversion is performed, and conversion as shown in line 28 in Fig. 28 is performed. It corresponds linearly to 0 ^ 7. Switch 362, 363 Force When connected to S contact ②, the characteristic changes relatively large while the level is low, as shown by curve の in Fig. 28, and the change decreases when the level is high. When it is connected to the fixed contact ③, on the contrary, as shown by the curve ③, when the level is low, it gradually changes and is compressed, and when the level becomes large, it changes suddenly. As shown in Fig. 29, when the signal is extended and connected to the contact で あ, the level is set to twice the resolution of the contact ①, as shown in Fig. 29. The upper part can be displayed. In that case, it is saturated to the maximum level above that level. In the case of the contact ④, the level 7 or more of the input from the main memory is output as the zero level on the curve ④. When it is connected to the contact 示 す, as shown by the line 第 in Fig. 29, the low level is 0 level, and the high level is a constant value of high level, and the resolution of the middle level is increased. ing. In the case of contact に お い て, in the case of contact ⑥, the level of 7 or more is set to the 0 level. In the case of contact point で, the high-level resolution is increased.

 Depending on the area, do not change the color characteristics. To make the characteristics the same, set switches 362 and 363 to the fixed contacts of the same number.

OMPI WIPO It should be set. As described above, the output of the main memory 81 and the output of the switching circuit 366 are used as the address, and the code conversion circuit 361 responds to the position of the fixed contact set by the switches 362 and 363. As shown in FIG. 27, the four bits of the output of the main memory 81 are converted into a three-bit code and output. This converted output is supplied to the color conversion circuit 177 in FIG. 1 and supplied to the cathode ray tube. For example, as described above, when the lower side of the display screen is enlarged both in the depth direction and the time axis direction, the dynamic range of this level is enlarged and the portion displayed For example, characteristics such as that shown in the line in Fig. 29 were used to magnify and display only the intermediate level], or increasing the resolution at a low level as shown in the line in Fig. 28 You can do it.

 As described above, when the detection signal from the fish finder and the detection signal from the net monitor are displayed at the top and bottom of the screen, the fish finder and the net monitor are displayed. It is difficult to make the gain control circuits for the detection signals of and have the same characteristics. The switching switches 362 and 363 can be selected according to the difference in the characteristics so that the display is performed with the same color characteristics.

 Even if the displayed color characteristics are changed in various ways, the original data remains in the main memory 81. Therefore, if the switches 362 and 363 are returned to the contact point 再 び again, the original data becomes the standard color. It can be displayed by characteristics.

 When changing the color characteristics according to the area of the screen, the moving speed of the screen varies depending on the area.

OMPI

To \ It is not necessary to remove them, and they can be the same. By changing the color characteristics in this way, the same effect can be obtained by changing the input / output characteristics and the gain of the receiver. You can return to the state again. That is, since the original data remains in the main memory 81, it is possible to display various color characteristics for the same data simply by changing the selection of the switching switches 36 2 and 36 3. This is possible not only in the case of the above-mentioned change in the color characteristics, but also when searching for fish schools near the seabed and detecting small fish in the Bracton layer. It is easy to set the characteristics according to each purpose such as detection of fish school on the sea floor. '

It has been considered that in a fish finder, so-called correlation is obtained by adding and averaging multiple pieces of detection information in order to improve the SN ratio. In such a configuration, for example, an image that exists as a small unit disappears.In other words, an image that is displayed as a point of j? L display lines is, for example, five images. When the averaging of the detection information is performed, the level is reduced to 1-5. Therefore, it is possible to perform a display in which the SN ratio is improved by taking such a correlation, and to display the information obtained by one detection signal without leaving the display. Is expected. In the prior art, this was not possible because the received data was lost one after another, but in the present invention, the data was received by the main memory 81 before. Multiple data as needed It is also possible to output the average or the sum of the detected signals of the two, and then to display the original data without such averaging or addition again.

 That is, for example, as shown in FIG. 30, the read output of the main memory 81 is supplied to the cascade connection of shift registers 367, 368, and 369 having the capacity of one display line. You. At the same time, the output of the main memory 81 is supplied to the fixed contact a of the switching switch 371. The movable contact output of the switch 371 is supplied to a color conversion circuit 177.

 When the switch 371 is set to the contact a, the output of the main memory 81 is supplied to the power conversion circuit 177 as it is, and the display described so far is performed. The output of the main memory 81 and the output of the first-stage shift register 367 are supplied to the addition circuit 372, and the average output of both inputs from the output terminal 373 of the addition circuit 372 is output to the terminal 374. From this, the addition output is obtained. The average output is obtained by removing the least significant bit of the added output and shifting all bits one bit at a time.

 The signals at these terminals 373 and 374 are supplied to gates 375 and 376. On the other hand, the signals on the input side and output side of the shift register 367 are supplied to the 0 detection circuit 377, and the output of the 0 detection circuit 377 is low when any of the inputs is 0 level. It is made to become. This output is supplied to gates 375 and 376. Therefore, when 0 is detected, the outputs of gates 375 and 376 are also at the 0 level. If so, the current read detection information from gates 375 and 376 and one of them

OMPI WIPO An output obtained by adding the average of the previous detection information to the gate 375 is obtained at the gate 376, respectively. These gate outputs are supplied to the contacts b and c of the switching switch 371. Therefore, if the switch 371 is connected to the contact point b, the average output of two adjacent pieces of detection information, that is, the correlation output, is displayed on one display line. When the switch 371 is connected to the contact c, the addition output of the adjacent detection information is displayed on one display line.

 Further, the signals on the input and output sides of the shift register 369 are added by an adder circuit 378, the added output and the output of the gate 376 are added by an adder circuit 379, and the average value is output. That is, the added value is output as 14. This is supplied to the contact d of the switch 371. Accordingly, when the switch 371 is set to the contact point d, the correlation signal which is reduced to 1/4 after the four adjacent detection signals are added is displayed on one display line.

 By switching the switch 371 in this way, the detection information can be displayed as a correlation, a correlation, or an addition. it can. In addition, if necessary, the correlation is taken and the S / N ratio is improved and displayed, and then the switch 371 is returned to the contact point a again, so that the previous information data remains in the main memory 81. In addition, correlation data can be displayed for the same data.

 The switching switch 371 is switched between, for example, one contact by the output of the frequency dividing circuit 84, and is switched to two areas of the display screen.

 O PI

WIPO If one data area is displayed, one of the areas will display the raw data without any change to the output of the main memory 81, for example, and the other area will display the detection signal. It is also possible to display the correlation of two or more of them.

 Also in this case, the display speed of the divided area may or may not be changed. Although the output of the main memory is processed in FIG. 30, the output of the code conversion circuit 361 shown in FIG. 26 may be processed in the same manner.

 The longer the time from the transmission of the ultrasonic pulse, the higher the sensitivity and the further the distance.] The pulse is transmitted so that the signal of the reduced level of 3 can be received at the same level. From then on, the so-called STC method is used to increase the sensitivity of the receiver over time. The data with and without the STC is displayed at the same time].

That is, for example, as shown in FIG. 31, the main memory 81 Q output is supplied to the code conversion circuit 381, and in synchronism with the line synchronizing signal from the line synchronizing signal generating circuit 85, the sawtooth wave generating circuit 382 Is driven. The output of the sawtooth wave generation circuit 382 is converted into a 4-bit digital signal by the AD conversion circuit 383, and the converted output is also supplied to the sign conversion circuit 381. The code conversion circuit 381 is composed of, for example, a read-only memory, like the code conversion circuit 361 of FIG. The output of the main memory 81 and the output of the AD conversion circuit 383 are used as an address, and a 3-bit output is read. This is, for example, low sensitivity at the beginning of a line scan, Therefore, the characteristics are as shown by the line (1) in Fig. 29, and the sensitivity increases as the level of the received signal decreases as time passes, as shown by the lines (1) and (2). Is written in advance so that

 In this way, the output of the main memory 81 and the output of the code conversion circuit 381 are switched over by the switching circuit 384. 3) The switching is performed when the STC is applied and when the STC is not applied. Even if the STC is displayed with the STC, the original data remains in the main memory 81, so the STC can be displayed as needed, and the data can be displayed. it can. If the switching circuit 384 is supplied as a control signal via the output of the frequency dividing circuit 84 via the switch 385, the one with the STC automatically applied and the other without the STC are alternated. Appears in In this case, the same image is displayed on the upper and lower sides of the screen, so that the same image is sent and the same image is sent.)) The STC speed and the original speed are displayed at the same time. You can also do that. It is desirable that the switching circuit 384 be able to be manually switched.

The time scale 157 shown in FIGS. 14 and 15, for example, is obtained by dividing the output of the reference oscillator 83 in the time scale generator 159 in FIG. 3 and displaying white each time the time elapses 1 minute. The digital signal is supplied to a buffer memory 79 via an OR circuit 386 and further via an acknowledgment circuit 94. For example, a white dot-like time scale 157 is obtained at regular intervals at the bottom of the display line. If the speed is very slow, the time scales will touch each other and extend along a single line in the time axis. In such a case, a part of the time scale generator 159 is branched and input to the slower time scale generator 387 so that the time scale can be displayed. At the same time, a red signal is generated and the signal is written to the buffer memory 79 via the OR circuits 386 and 94. In this way, even when the time scale 159 is continuous white, the red scales appear on the white line.

Claims

The scope of the claims  1. The above-mentioned operation information is the main message so that the detection information is displayed as one display line, and the display lines are arranged in the order of the detection information in the oldest order and displayed as raster-scanning lines. The main memory (81) stored in the memory (81) is repeatedly read out and converted to a color signal corresponding to the level by a power conversion circuit (177). It is supplied to the color cathode ray display (82) and displayed. Every time new detection information is written to the main memory (81), the old detection information is erased and the display image is moved. In the detection information display device adapted to perform such operations, the display screen is divided into a plurality of areas, and new information for the information in the main memory (81) corresponding to the plurality of areas is provided. Means for varying the writing frequency of the image are provided, and the moving speed of the image in the plurality of areas is varied. Detection information display device according to Toku徵.  2. The detection information display device according to claim 1, further comprising means for changing a color characteristic indicating a relationship between a detection signal level and a display color among a plurality of areas of the display screen. A detection information display device featuring an octopus.  3. In the detection information display device according to claim 1, a different speed switching switch (206) for switching between a normal display and a different speed display as means for changing the writing frequency of information. ), And a gate signal generation circuit (118) for supplying a signal to a clock generation circuit (111), a frequency division circuit (325), and a frequency division circuit (325). Included with gate circuit (309) -OMPI funding. , (115), (112) and (113), and a main memory (81) for storing information from the buffer memory (79)].  4. The detection information display device according to claim 1, wherein one of the areas is transmitted to another area as means for varying the moving speed of the image in the plurality of areas! ) Slow speed compared to speed] 3! ) The decision circuit (326) and this transmission! ) Select switch to select speed (327)! The low-speed transmission decision circuit (326) is a frequency dividing circuit that divides the output of the gate signal generating circuit (118).] According to the selection switch (327) 9. This division ratio is changed.  5. In the detection information display device described in claim 4, in the case of [low-speed transmission] ?, even if the buffer memory (79) is rewritten a plurality of times, one information is mainly used. Images that are supplied to the memory (81) and appear on only one or two of the five display lines are culled from the display screen to prevent this information leakage. And a decimation correction circuit (328).  ^ 6. In the detection information display device as set forth in claim 5, the thinning-out correction circuit (328) is configured to calculate a new 0 data of 0 and a previous data from the buffer memory (79). Comparing comparator  (334) and a gate circuit (635), (638), (636) for controlling the signal of the buffer memory (79) according to the output level of the comparator (334); The delay circuit (335) for the previous data and the five delay circuits (336) for supplying signals to the main memory (81)]). Ο ΡΙ / ,, WIPO ― Ku η "— ' 7. In the detection information display device according to claim 6, the thinning-out correction circuit (328) can be used even when the display screen is difficult to be divided into a plurality of screens.  8. In the detection information display device according to claim 2, the means for making the color characteristics different is when the information is read from the main memory (81) corresponding to one or more regions of the display screen. Do this.  9. The detection information display device according to claim 8, wherein the means for making the color characteristics different comprises: n bits from the main memory (81) supplied to the code conversion circuit (361). Select the color information selection switches (362) and (363)], and select multiple areas from the encoders (364) and (365) and the frequency divider (84). Means for controlling the code conversion circuit (361) with the output through the selection switching circuit (366) and converting the code conversion circuit into m-bit information. Note that n> m.  10. The detection information display device according to claim 9, wherein the code conversion circuit (361) is a read-only memory. 11. In the detection information display device according to claim 8, in the step of reading information from the main memory (81) and supplying the read information to the color conversion circuit (177), a plurality of pieces of adjacent information are read. Means for adding and averaging, so-called correlation are provided.  12. The detection information display device according to claim 11, wherein the means for adding and averaging the plurality of pieces of information to obtain a so-called correlation is a cascade-connected shift register (367), (368), (369), addition circuit (372), (378), and 0 detection circuit (377) (O PI VV WIPO. And the addition and average switching gates (375) and (367) and the switching switch (371)! )It is configured.  13. The detection information display device according to claim 2, wherein the means for changing the color characteristics reads information from the main memory (81) corresponding to one or a plurality of areas of the display screen, In the process of supplying the color to the conversion circuit (177), a means for gradually converting the n-bit information into other m-bit information from the reference point force of the oscillation line to make the color characteristics different is provided. To have.  14. In the detection information display device according to claim 13, the means for making the color characteristics different includes: a code conversion circuit (381), a line synchronization signal generation circuit (85), and the circuit (85). Thus, the sawtooth wave generating circuit (382) driven, the AD conversion circuit (383) for converting this output to m-bit information, and the color characteristics of only one part of a plurality of regions on the display screen are different. Switch (385) and switching circuit (384), and the frequency dividing circuit (84), which is the switching signal for switching! ) It is composed.  15. In the detection information display device according to claim 14, the code conversion circuit (381) is a read-only memory.