USRE35221E - Schottky enhanced CMOS output circuit - Google Patents
Schottky enhanced CMOS output circuit Download PDFInfo
- Publication number
- USRE35221E USRE35221E US08/061,628 US6162893A USRE35221E US RE35221 E USRE35221 E US RE35221E US 6162893 A US6162893 A US 6162893A US RE35221 E USRE35221 E US RE35221E
- Authority
- US
- United States
- Prior art keywords
- channel transistor
- output circuit
- schottky diode
- voltage potential
- iaddend
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/09425—Multistate logic
- H03K19/09429—Multistate logic one of the states being the high impedance or floating state
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
- H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
Definitions
- This invention relates generally to semiconductor integrated circuits, and more particularly the invention relates to CMOS output circuit.
- the standard CMOS output circuit as used in interfacing one of a plurality of devices to a common bus has an input signal applied to both gates of the CMOS transistor pair, and an inverted output is taken at the common terminal of the two serially-connected transistors.
- the output circuit can assume a high impedance state (i.e., tri-state) by taking the gate of the P-channel transistor high and the gate of the N-channel transistor low.
- an output circuit can have a voltage applied to its output terminal which is greater in magnitude than the supply voltages for that output circuit. In this circumstance, the substrate/source-drain diodes of the transistors can forward bias thus loading the common bus and causing potential latchup problems.
- An object of the invention is a CMOS output circuit having an enhanced high impedance state.
- a future of the invention is a provision of Schottky diodes in series with the transistors of a CMOS output circuit to prevent forward bias of the substrate/source-drain diodes when the circuit is in a high impedance state.
- FIG. 1 is a schematic of a conventional CMOS output circuit.
- FIG. 2 is a schematic of a CMOS output circuit in accordance with one embodiment of the invention.
- FIG. 3 is a section view of a semiconductor circuit illustrating the CMOS output circuit of FIG. 2.
- FIG. 1 is a schematic of a conventional CMOS output circuit.
- a P-channel transistor 10 is serially connected with an N-channel transistor 12 between a positive voltage potential (V+) and ground.
- the input signals to the circuit (PEN and NEN) are applied to the gates of the transistors 10, 12, and the output of the circuit is taken at the common terminal of the two transistors.
- the CMOS output circuit can be employed to connect a device to a bus shared with other devices.
- the circuit can isolate the device from the bus through the application of a high voltage potential to the gate of the P-channel transistor 10 and a low voltage to the gate of the N-channel transistor 12. In this mode both transistors are turned off thus isolating the output terminal.
- various devices connected to a common bus can have different operating voltages. Thus, the voltage level on the bus can be beyond the voltage levels For the output circuit.
- the substrate/source-drain diodes of the transistor devices can forward bias and inject current into the substrate thereby causing latchup problems and undesirably loading the common bus.
- Schottky diodes 14 and 16 are serially connected with the transistors 10 and 12 as illustrated in the schematic of FIG. 2.
- the presence of the Schottky diode 14 prevents the drain-substrate diode of the P-channel transistor from forward biasing even though the output voltage exceeds V+.
- Schottky diode 16 prevents the substrate-drain diode of N-channel transistor 12 from forward biasing even though the output voltage is below ground potential. Because the Schottky diodes will not forward bias and inject current into the substrate, the circuit will be free from latchup problems.
- the Schottky diodes can be formed in a semiconductor device structure from a normal metal (e.g. aluminum) to N -well junction in a standard N-well CMOS process. Such a structure is illustrated in the cross-sectional view of a CMOS device of FIG. 3.
- the device is fabricated in a P-substrate 20 with the P-channel transistor 10 formed in an N-well 22 and the N-channel of transistor 12 formed directly in the P-substrate 20.
- Schottky diode 14 is formed by an aluminum contact directly contacting the N-well 22, while the Schottky diode 16 is formed by a metal contacting N-well 24.
- An N+diffusion 26 is provided in N-well 22 to facilitate contact to the well.
- N+diffusion 28 is formed in N-well 22 to facilitate the contact to the N-well.
- the source 32 of the N-channel transistor is connected to ground, while the drain 34 of the P-channel transistor 10 is connected to the output terminal and to Schottky diode 16.
- the Schottky diodes are readily fabricated using conventional processing technology and conventional cell structures as described above.
- the Schottky diode 14 must be placed between V+ and the transistor 10 because of the N-well configuration including the Schottky diode, the transistor, and the output connection.
- the diode could be placed between transistor 10 and the output terminal if the N-well could be isolated from the substrate.
- Schottky diode 16 could between transistor 12 and ground if the N-well could be isolated from the substrate.
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The high impedance state of a tri-state CMOS transistor output circuit is enhanced by serially connecting first and second Schottky diodes with the P-channel transistor and the N-channel transistor whereby in the high impedance state reverse bias of the substrate/source-drain diodes of the two transistors is prevented when the output of the circuit is taken beyond the supply voltage potentials of the output circuit.
Description
This invention relates generally to semiconductor integrated circuits, and more particularly the invention relates to CMOS output circuit.
The standard CMOS output circuit as used in interfacing one of a plurality of devices to a common bus, for example, has an input signal applied to both gates of the CMOS transistor pair, and an inverted output is taken at the common terminal of the two serially-connected transistors. The output circuit can assume a high impedance state (i.e., tri-state) by taking the gate of the P-channel transistor high and the gate of the N-channel transistor low. However, since different peripheral devices tied to common bus can have different operating voltage levels, which are selectively applied to the bus, an output circuit can have a voltage applied to its output terminal which is greater in magnitude than the supply voltages for that output circuit. In this circumstance, the substrate/source-drain diodes of the transistors can forward bias thus loading the common bus and causing potential latchup problems.
An object of the invention is a CMOS output circuit having an enhanced high impedance state.
A future of the invention is a provision of Schottky diodes in series with the transistors of a CMOS output circuit to prevent forward bias of the substrate/source-drain diodes when the circuit is in a high impedance state.
The invention and objects and the futures thereof will be more readily apparent from the following detailed description and the appended claims when taken with the drawings.
FIG. 1 is a schematic of a conventional CMOS output circuit.
FIG. 2 is a schematic of a CMOS output circuit in accordance with one embodiment of the invention.
FIG. 3 is a section view of a semiconductor circuit illustrating the CMOS output circuit of FIG. 2.
FIG. 1 is a schematic of a conventional CMOS output circuit. A P-channel transistor 10 is serially connected with an N-channel transistor 12 between a positive voltage potential (V+) and ground. The input signals to the circuit (PEN and NEN) are applied to the gates of the transistors 10, 12, and the output of the circuit is taken at the common terminal of the two transistors.
As noted above, the CMOS output circuit can be employed to connect a device to a bus shared with other devices. The circuit can isolate the device from the bus through the application of a high voltage potential to the gate of the P-channel transistor 10 and a low voltage to the gate of the N-channel transistor 12. In this mode both transistors are turned off thus isolating the output terminal. However, as noted above, various devices connected to a common bus can have different operating voltages. Thus, the voltage level on the bus can be beyond the voltage levels For the output circuit.
In this condition, the substrate/source-drain diodes of the transistor devices can forward bias and inject current into the substrate thereby causing latchup problems and undesirably loading the common bus.
In accordance with the present invention, Schottky diodes 14 and 16 are serially connected with the transistors 10 and 12 as illustrated in the schematic of FIG. 2. The presence of the Schottky diode 14 prevents the drain-substrate diode of the P-channel transistor from forward biasing even though the output voltage exceeds V+. Similarly, Schottky diode 16 prevents the substrate-drain diode of N-channel transistor 12 from forward biasing even though the output voltage is below ground potential. Because the Schottky diodes will not forward bias and inject current into the substrate, the circuit will be free from latchup problems.
The Schottky diodes can be formed in a semiconductor device structure from a normal metal (e.g. aluminum) to N -well junction in a standard N-well CMOS process. Such a structure is illustrated in the cross-sectional view of a CMOS device of FIG. 3. The device is fabricated in a P-substrate 20 with the P-channel transistor 10 formed in an N-well 22 and the N-channel of transistor 12 formed directly in the P-substrate 20. Schottky diode 14 is formed by an aluminum contact directly contacting the N-well 22, while the Schottky diode 16 is formed by a metal contacting N-well 24. An N+diffusion 26 is provided in N-well 22 to facilitate contact to the well. Similarly, an N+diffusion 28 is formed in N-well 22 to facilitate the contact to the N-well. The source 32 of the N-channel transistor is connected to ground, while the drain 34 of the P-channel transistor 10 is connected to the output terminal and to Schottky diode 16.
The provision of Schottky diodes in a CMOS output stage circuit facilitates the high impedance state of the output circuit without forward biasing of the substrate/source-drain diodes of the transistor structures.
The Schottky diodes are readily fabricated using conventional processing technology and conventional cell structures as described above. In the described embodiment the Schottky diode 14 must be placed between V+ and the transistor 10 because of the N-well configuration including the Schottky diode, the transistor, and the output connection. The diode could be placed between transistor 10 and the output terminal if the N-well could be isolated from the substrate. Similarly, Schottky diode 16 could between transistor 12 and ground if the N-well could be isolated from the substrate.
Thus, while the invention has been described with reference to a specific embodiment, the description is illustrative of the invention and not to be construed as limiting the invention. Various modifications and applications may occur to those skilled in the art without departing from the true spirit and scope of the invention as defined by the appended claims.
Claims (7)
1. A CMOS output circuit comprising:
first and second voltage potentials;
a P-channel transistor having source, drain, and gate electrodes and an N-channel transistor having source, drain, and gate electrodes;
first input terminal means for applying a first input signal to said gate of said P-channel transistor;
second input terminal means for applying a second input signal to said gate electrode of said N-channel transistor;
a first Schottky diode connecting said source electrode of said P-channel transistor to said first voltage potential;
means connecting said source electrode of said N-channel transistor to said second voltage potential;
an output terminal connected to said drain electrode of said P-channel transistor; and
a second Schottky diode connecting said output terminal to said drain electrode of said N-channel transistor.
2. The CMOS output circuit as defined by claim 1 wherein said first voltage potential is more positive than said second voltage potential, said first Schottky diode being forward biased for current flow from said first voltage potential to said source electrode of said P-channel transistor, and said second Schottky diode being forward biased between said output terminal and said drain electrode of said N-channel transistor.
3. The CMOS output circuit as defined by claim 2 wherein said transistors are fabricated in a P-conductivity silicon substrate, said first and second Schottky diodes comprising N-doped wells in a surface of said substrate with respective metal contacts on the surfaces of the N-wells.
4. The CMOS output circuit of claim 3 wherein said first and second Schottky diodes further include respective N+ regions to facilitate contact with said respective metal contacts.
5. A CMOS output circuit comprising:
first and second voltage potentials;
a P-channel transistor;
an N-channel transistor;
first input terminal means for applying a first input signal to a gate electrode of said P-channel transistor;
second input terminal means for applying a second input signal to a gate electrode of said N-channel transistor;
a first Schottky diode serially connected with said P-channel transistor between said first voltage potential and an output terminal; and
a second Schottky diode serially connected with said N-channel transistor between said output terminal and said second voltage potential. .Iadd.
6. In an output circuit having an output terminal and first and second transistors which respectively couple first and second voltage potentials to said output terminal responsive to input signals applied to control electrodes of said first and second transistors, wherein at least one of said first and second transistors is an MOS transistor, an improvement comprising:
a Schottky diode in series with said MOS transistor between said output terminal and one of said first and second voltage potentials. .Iaddend..Iadd.7. The output circuit of claim 6, wherein said MOS transistor is a P-channel transistor. .Iaddend..Iadd.8. The output circuit of claim 7, wherein said first voltage potential is more positive than said second voltage potential, said Schottky diode being forward biased for current flow from said first voltage potential to a source electrode of said P-channel transistor. .Iaddend..Iadd.9. The output circuit of claim 8, wherein said Schottky diode connects said source electrode of said P-channel transistor to said first voltage potential, and a drain electrode of said P-channel transistor is connected to said output terminal. .Iaddend..Iadd.10. The output circuit of claim 6, wherein said MOS transistor is an N-channel transistor. .Iaddend..Iadd.11. The output circuit of claim 10, wherein said first voltage potential is more positive than said second voltage potential, said Schottky diode being forward biased for current flow from said output terminal to a drain electrode of
said N-channel transistor. .Iaddend..Iadd.12. The output circuit of claim 11, wherein said Schottky diode connects said drain electrode of said N-channel transistor to said output terminal, and a source electrode of said N-channel transistor is connected to said second voltage potential. .Iaddend..Iadd.13. The output circuit as defined by claims 6, 7, 8, 9, 10, 11 or 12 wherein said Schottky diode comprises an N-doped well in a surface of a P-conductivity silicon substrate, with a metal contact on the surface of said N-well. .Iaddend..Iadd.14. The output circuit of claim 13 wherein said Schottky diode further includes an N+ region to facilitate contact with said metal contact. .Iaddend.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/061,628 USRE35221E (en) | 1989-02-23 | 1993-05-13 | Schottky enhanced CMOS output circuit |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/314,378 US5015889A (en) | 1989-02-23 | 1989-02-23 | Schottky enhanced CMOS output circuit |
| US08/061,628 USRE35221E (en) | 1989-02-23 | 1993-05-13 | Schottky enhanced CMOS output circuit |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US07/314,378 Reissue US5015889A (en) | 1989-02-23 | 1989-02-23 | Schottky enhanced CMOS output circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| USRE35221E true USRE35221E (en) | 1996-04-30 |
Family
ID=23219719
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US07/314,378 Ceased US5015889A (en) | 1989-02-23 | 1989-02-23 | Schottky enhanced CMOS output circuit |
| US08/061,628 Expired - Lifetime USRE35221E (en) | 1989-02-23 | 1993-05-13 | Schottky enhanced CMOS output circuit |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US07/314,378 Ceased US5015889A (en) | 1989-02-23 | 1989-02-23 | Schottky enhanced CMOS output circuit |
Country Status (1)
| Country | Link |
|---|---|
| US (2) | US5015889A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6262460B1 (en) * | 2000-01-07 | 2001-07-17 | National Semiconductor Corporation | Long channel MOS transistor that utilizes a schottky diode to increase the threshold voltage of the transistor |
| US20050148126A1 (en) * | 2004-01-06 | 2005-07-07 | Yaowen Chang | Low voltage CMOS structure with dynamic threshold voltage |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5274284A (en) * | 1991-01-24 | 1993-12-28 | Texas Instruments Incorporated | Output buffer circuits with controlled Miller effect capacitance |
| US5149991A (en) * | 1991-06-06 | 1992-09-22 | National Semiconductor Corporation | Ground bounce blocking output buffer circuit |
| JPH05198755A (en) * | 1991-08-29 | 1993-08-06 | Mitsubishi Electric Corp | Semiconductor logic circuit |
| JP2707954B2 (en) * | 1993-09-01 | 1998-02-04 | 日本電気株式会社 | Code setting circuit |
| US5451889A (en) * | 1994-03-14 | 1995-09-19 | Motorola, Inc. | CMOS output driver which can tolerate an output voltage greater than the supply voltage without latchup or increased leakage current |
| ITTO20010530A1 (en) * | 2001-06-01 | 2002-12-01 | St Microelectronics Srl | OUTPUT BUFFER FOR A NON-VOLATILE MEMORY WITH SWITCHING NOISE REDUCTION ON THE OUTPUT SIGNAL AND NON-VOLATILE MEMORY INCLUDED |
| US6963214B2 (en) * | 2003-10-06 | 2005-11-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | OBIRCH dual power circuit |
| JP2015015643A (en) * | 2013-07-05 | 2015-01-22 | ローム株式会社 | Signal transmission circuit |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4023122A (en) * | 1975-01-28 | 1977-05-10 | Nippon Electric Company, Ltd. | Signal generating circuit |
| JPS5864828A (en) * | 1981-10-14 | 1983-04-18 | Toshiba Corp | Cmos logical circuit device |
| US4578600A (en) * | 1982-01-26 | 1986-03-25 | Itt Industries, Inc. | CMOS buffer circuit |
| JPS62260426A (en) * | 1986-05-06 | 1987-11-12 | Nec Corp | Cmos output buffer circuit |
| US4740713A (en) * | 1985-01-26 | 1988-04-26 | Kabushiki Kaisha Toshiba | MOS semiconductor integrated circuit in which the production of hot carriers near the drain of a short n channel conductivity type MOS transistor is decreased |
| US4791321A (en) * | 1985-12-27 | 1988-12-13 | Kabushiki Kaisha Toshiba | CMOS output circuit device |
| US4801983A (en) * | 1985-08-30 | 1989-01-31 | Hitachi, Ltd. | Schottky diode formed on MOSFET drain |
| US4996449A (en) * | 1988-07-19 | 1991-02-26 | Kabushiki Kaisha Toshiba | Output circuit having high speed operation and low power dissipation |
| US5097153A (en) * | 1989-05-11 | 1992-03-17 | Texas Instruments Incorporated | TTL compatible BICMOS input circuit |
| US5233237A (en) * | 1991-12-06 | 1993-08-03 | National Semiconductor Corporation | Bicmos output buffer noise reduction circuit |
-
1989
- 1989-02-23 US US07/314,378 patent/US5015889A/en not_active Ceased
-
1993
- 1993-05-13 US US08/061,628 patent/USRE35221E/en not_active Expired - Lifetime
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4023122A (en) * | 1975-01-28 | 1977-05-10 | Nippon Electric Company, Ltd. | Signal generating circuit |
| JPS5864828A (en) * | 1981-10-14 | 1983-04-18 | Toshiba Corp | Cmos logical circuit device |
| US4578600A (en) * | 1982-01-26 | 1986-03-25 | Itt Industries, Inc. | CMOS buffer circuit |
| US4740713A (en) * | 1985-01-26 | 1988-04-26 | Kabushiki Kaisha Toshiba | MOS semiconductor integrated circuit in which the production of hot carriers near the drain of a short n channel conductivity type MOS transistor is decreased |
| US4801983A (en) * | 1985-08-30 | 1989-01-31 | Hitachi, Ltd. | Schottky diode formed on MOSFET drain |
| US4791321A (en) * | 1985-12-27 | 1988-12-13 | Kabushiki Kaisha Toshiba | CMOS output circuit device |
| JPS62260426A (en) * | 1986-05-06 | 1987-11-12 | Nec Corp | Cmos output buffer circuit |
| US4996449A (en) * | 1988-07-19 | 1991-02-26 | Kabushiki Kaisha Toshiba | Output circuit having high speed operation and low power dissipation |
| US5097153A (en) * | 1989-05-11 | 1992-03-17 | Texas Instruments Incorporated | TTL compatible BICMOS input circuit |
| US5233237A (en) * | 1991-12-06 | 1993-08-03 | National Semiconductor Corporation | Bicmos output buffer noise reduction circuit |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6262460B1 (en) * | 2000-01-07 | 2001-07-17 | National Semiconductor Corporation | Long channel MOS transistor that utilizes a schottky diode to increase the threshold voltage of the transistor |
| US20050148126A1 (en) * | 2004-01-06 | 2005-07-07 | Yaowen Chang | Low voltage CMOS structure with dynamic threshold voltage |
| US7141470B2 (en) * | 2004-01-06 | 2006-11-28 | Macronix International Co., Ltd. | Low voltage CMOS structure with dynamic threshold voltage |
Also Published As
| Publication number | Publication date |
|---|---|
| US5015889A (en) | 1991-05-14 |
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