[go: up one dir, main page]

US8987015B2 - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

Info

Publication number
US8987015B2
US8987015B2 US13/172,403 US201113172403A US8987015B2 US 8987015 B2 US8987015 B2 US 8987015B2 US 201113172403 A US201113172403 A US 201113172403A US 8987015 B2 US8987015 B2 US 8987015B2
Authority
US
United States
Prior art keywords
aln layer
source
ratio
layer
flow
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US13/172,403
Other languages
English (en)
Other versions
US20120003821A1 (en
Inventor
Keiichi YUI
Akira Furuya
Ken Nakata
Takamitsu Kitamura
Isao MAKABE
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Assigned to SUMITOMO ELECTRIC INDUSTRIES, LTD. reassignment SUMITOMO ELECTRIC INDUSTRIES, LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FURUYA, AKIRA, KITAMURA, TAKAMITSU, MAKABE, ISAO, NAKATA, KEN, YUI, KEIICHI
Publication of US20120003821A1 publication Critical patent/US20120003821A1/en
Application granted granted Critical
Publication of US8987015B2 publication Critical patent/US8987015B2/en
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • H10P14/24—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/14—Feed and outlet means for the gases; Modifying the flow of the reactive gases
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/18—Epitaxial-layer growth characterised by the substrate
    • C30B25/186—Epitaxial-layer growth characterised by the substrate being specially pre-treated by, e.g. chemical or physical means
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02502—Layer structure consisting of two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H01L21/02661—In-situ cleaning
    • H10P14/2905—
    • H10P14/3216—
    • H10P14/3248—
    • H10P14/3416—
    • H10P14/3602—

Definitions

  • a certain aspect of the embodiments discussed herein is related to a method for fabricating a semiconductor device.
  • Another aspect of the embodiments is related to a method for fabricating a semiconductor device in which a GaN-based semiconductor layer is formed on a silicon substrate.
  • GaN gallium nitride
  • Semiconductor devices using a gallium nitride (GaN) based semiconductor are used as a power device operating at high frequencies and outputting high power, and a light emitting diode or a laser diode emitting light of short wavelengths.
  • a high-frequency or RF (radio Frequency) band such as a microwave band, a quasi-millimeter band or a millimeter band.
  • Examples of those semiconductor devices are an FET such as a high electron mobility transistor (HEMT) and light emitting devices such as a laser diode (LD) and a light emitting diode (LED).
  • HEMT high electron mobility transistor
  • LED light emitting devices
  • a sapphire substrate or a silicon carbide (SiC) substrate is used as a substrate on which the GaN-based semiconductor layer is grown. Since the sapphire substrate and the SiC substrate are expensive, there has been developed an art of growing the GaN-based semiconductor layer on the silicon (Si) substrate. As Si and Ga react easily, an AlN layer is interposed between the Si substrate and the GaN-based semiconductor layer as a barrier layer (see Japanese Patent Application Publication No. 2008-166349).
  • a pit-like defect may occur on the surface of the AlN on the Si substrate.
  • the GaN-based semiconductor layer is formed on the AlN layer on which many pit-like defects occur in order to form a HEMT, for example, a process for fabricating the transistor may be affected. For example, electrodes may not be formed reliably.
  • Another problem is a deterioration of the crystal quality of the GaN-based semiconductor layer, which leads to a degradation of the transistor characteristics.
  • a method for fabricating a semiconductor device including: performing thermal cleaning for a surface of a silicon substrate in an atmosphere including hydrogen under a condition that a thermal cleaning temperature is higher than or equal to 700° C. and is lower than or equal to 1060° C., and a thermal cleaning time is longer than or equal to 5 minutes and is shorter than or equal to 15 minutes; forming a first AlN layer on the silicon substrate with a first V/III source ratio, the forming of the first AlN layer including supplying an Al source to the surface of the silicon substrate without supplying a N source thereto after the thermal cleaning, and supplying both the Al source and the N source after the supplying of the Al source; forming a second AlN layer on the first AlN layer with a second V/III source ratio that is greater than the first V/III source ratio; and forming a GaN-based semiconductor layer on the second AlN layer.
  • FIGS. 1A through 1D are cross-sectional views that illustrate a method for fabricating a semiconductor device in accordance with a first embodiment
  • FIGS. 2A and 2B are cross-sectional views of steps following the step illustrated in FIG. 1D ;
  • FIG. 3 is a picture of a SEM image of a surface of sample A
  • FIG. 4 is a diagram that illustrates the number of cracks associated with FWHM
  • FIG. 5A is a diagram that illustrates a relationship between the total quantity of pre-flow of TMA and FWHM
  • FIG. 5B is a diagram that illustrates a relationship between the total quantity of pre-flow of TMA and sheet resistance;
  • FIG. 6 is a picture of a SEM image of a surface of sample B
  • FIG. 7 is a schematic cross-sectional view of pit-like defects
  • FIG. 8 is a diagram that illustrates a pit density associated with an NH 3 flow ratio
  • FIG. 9 is a picture of a SEM image of a surface of sample C.
  • FIGS. 1A through 2B are cross-sectional views that illustrate the method for fabricating the semiconductor device in accordance with the first embodiment.
  • the steps in FIGS. 1A through 2A are carried out in a reactor of a MOCVD (Metal Organic Chemical Vapor Deposition) chamber without taking a wafer out of the reactor.
  • MOCVD Metal Organic Chemical Vapor Deposition
  • a surface of a Si substrate 10 having a principal plane that is a (111) plane is treated by thermal cleaning within the reactor of the MOCVD chamber.
  • the condition for the thermal cleaning is such that the thermal cleaning temperature is higher than or equal to 700° C. and is lower than or equal to 1060° C., the thermal cleaning time is longer than or equal to 5 minutes and is shorter than or equal to 15 minutes, and an atmosphere including hydrogen (an atmosphere in which hydrogen is included in a carrier gas) is used.
  • an Al source is supplied to the surface of the Si substrate 10 while a N source is not supplied. This is called a pre-flow of the Al source.
  • the Al source and the N source are supplied to grow a first AlN layer 11 on the Si substrate 10 with a first V/III ratio.
  • a second AlN layer 12 is grown on the first AlN layer 11 with a second V/III ratio greater than the first V/III ratio.
  • the first AlN layer 11 and the second AlN layer 12 form an AlN layer 13 .
  • a step illustrated in FIG. 2A is to grow a GaN-based semiconductor layer 21 on the second AlN layer 12 .
  • the GaN-based semiconductor layer 21 may be composed of an AlGaN buffer layer 14 , an undoped GaN layer 16 , an n-type AlGaN electron supply layer 18 , and an n-type GaN cap layer 20 .
  • the AlGaN buffer layer 14 may have a thickness of 100 nm, and an Al composition ratio of 0.5.
  • the undoped GaN layer 16 may have a thickness of, for example, 1000 nm.
  • the n-type AlGaN layer 18 may have a thickness of 20 nm, and an Al composition ratio of 0.2, for example.
  • the n-type GaN cap layer 20 has a thickness of, for example, 2 nm.
  • a source electrode 24 , a drain electrode 26 and a gate electrode 28 are formed on the GaN layer 20 .
  • Each of eh source electrode 24 and the drain electrode 26 is an ohmic electrode, which may be formed by stacking Ti and Au on the GaN layer 20 in this order.
  • the gate electrode 28 may be formed by stacking Ni and Au on the GaN layer 20 in this order.
  • the HEMT of the first embodiment is fabricated through the above steps.
  • a sample A was fabricated as a first comparative example.
  • the principal plane of the Si substrate 10 is the (111) plane, and the surface of the AlN layer on which layers are grown is the (0001) plane.
  • TMA trimethylaluminium
  • Annealing temperature 1050° C.
  • AlN layer 13 forming condition (the growing condition for the first AlN layer 11 and that for
  • the second AlN layer 12 are the same as each other):
  • N source NH 3 (ammonia)
  • FIG. 3 is a picture of an image of the surface of the sample A by SEM (Scanning Electron Microscope). As shown in FIG. 3 , many pit-like defects 34 are observed on the surface of the sample A. In a case where the thermal process temperature is higher than 1060° C., many pit-like defects 34 are observed on the surface of the AlN layer 13 . In contrast, in a case where the terminal process temperature is lower than 700° C., it is difficult to remove impurities on the surface of the Si substrate 10 . Thus, it is preferable that the thermal process temperature is higher than or equal to 750° C. and is lower than or equal to 1000° C.
  • the thermal process time is longer than or equal to 15 minutes, there are many pits on the surface of the Si substrate 10 . In contrast, in a case where the thermal process time is longer than or equal to 5 minutes, it is difficult to remove impurities on the surface of the Si substrate 10 . It is preferable that the thermal process time is longer than or equal to 6 minutes and is shorter than or equal to 10 minutes.
  • a gas that does not include hydrogen is used as the thermal process atmosphere, much more pit-like defects are observed on the surface of the AlN layer 13 . For example, much more pits are observed in a thermal process in an atmosphere that does not include hydrogen but includes nitrogen. It is considered that a reducing gas atmosphere is suitable for the thermal cleaning. As described, it is preferable to use an atmosphere including hydrogen for the thermal cleaning and is more preferably use a hydrogen atmosphere.
  • a sample B was fabricated as a second comparative example.
  • the principal plane of the Si substrate 10 is the (111) plane, and the surface of the AlN layer on which layers are grown is the (0001) plane.
  • Annealing temperature 1050° C.
  • AlN layer 13 forming condition (the growing condition for the first AlN layer 11 and that for the second AlN layer 12 are the same as each other):
  • the crystal quality of the AlN layer 13 was measured by using an FWHM (Full Width at Half Maximum) of a rocking curve of a (002) plane of AlN by x-ray diffraction in the state of FIG. 1C after the AlN layer 13 is grown. Further, a sample grown under the same condition (the growth condition for the first AlN layer 11 and that for the second AlN layer 12 are the same as each other) was used to form the structure illustrated in FIG. 2A , and the number of cracks on the GaN-based semiconductor layer 21 within a 4-inch wafer was measured.
  • FWHM Full Width at Half Maximum
  • FIG. 4 is a graph of the number of cracks associated with the FWHM. As illustrated in FIG. 4 , the number of cracks reduces when the FWHM is not greater than 1500 seconds. An improvement in the crystal quality of the AlN layer 13 reduces the number of cracks that occur in the GaN-based semiconductor layer 21 .
  • FIG. 5A is a graph of a relationship between the total quantity of pre-flow of TMA and FWHM
  • FIG. 5B is a graph of a relationship between the total quality of the pre-flow of TMA and the sheet resistance.
  • the measurement of the x-ray diffraction and the sheet resistance was carried out for a sample that was the semiconductor substrate illustrated in FIG. 1C .
  • the horizontal axis of the graph indicates the total quantity of pre-flow of TMA, and the vertical axis thereof indicates the FWHM of the AlN layer 13 .
  • the FWHM decreases. That is, as the total quantity of pre-flow of TMA increases, the crystal quality of the AlN layer 13 is improved.
  • the FWHM becomes less than 1500 seconds when the total quality of the pre-flow of TMA becomes greater than 3.5 ⁇ mol.
  • the number of cracks in the GaN-based semiconductor layer 21 is almost zero.
  • the graph of FIG. 5B is described below.
  • the horizontal axis of the graph indicates the total quality of the pre-flow of TMA, and the vertical axis thereof indicates the sheet resistance of the semiconductor substrate in the state illustrated in FIG. 1C .
  • Triangles in FIG. 5B indicate the sheet resistance due to the resistance of the Si substrate.
  • the sheet resistance is 100 kQ/ ⁇ when the total quality of the pre-flow of TMA is in the range of about 2 ⁇ mol to about 8 ⁇ mol.
  • the sheet resistance of only the Si substrate 10 is 100 kQ/ ⁇ . It was observed that the pre-flow of TMA hardly affected the sheet resistance of the Si substrate 10 when the total quality of the pre-flow of TMA is in the range of about 2 ⁇ mol to about 8 ⁇ mol. In contrast, as indicated by a dotted line in FIG. 5B , when the total quantity of pre-flow of TMA is greater than 8.8 ⁇ mol, the sheet resistance becomes smaller than 100 kQ/ ⁇ .
  • the above facts may result from a phenomenon in which Al supplied by the pre-flow of TMA diffuses into the Si substrate 10 and a resultant low-resistance layer is formed in the Si substrate 10 .
  • the low-resistance layer in the Si substrate 10 may lead to leakage after the semiconductor device is completed.
  • the FET which is an exemplary semiconductor device fabricated by the present process may have a degraded RF characteristic. Even if the growth temperature is changed to 1040° C., the sheet resistance decreases when the quantity of pre-flow of TMA becomes greater than 8.8 ⁇ mol.
  • the total quantity of pre-flow of the Al source is preferably not less than 3.5 ⁇ mol, and is more preferably not less than 4 ⁇ mol. Further, the total quantity of pre-flow of the Al source is preferably not greater than 8.8 ⁇ mol, and is more preferably not greater than 7 ⁇ mol.
  • FIG. 6 is a picture of a SEM image of the surface of the AlN layer 13 of the sample B.
  • the total quantity of pre-flow of TMA is 8 ⁇ mol.
  • a black dot indicated by a reference numeral 34 is a pit-like defect. As illustrated, pit-like defects 34 are observed on the whole surface of the AlN layer 13 , although a small number of pit-like defects 34 is observed, as compared with FIG. 3 .
  • FIG. 7 is a schematic cross-sectional view of pit-like defects. As illustrated in FIG. 7 , concave pit-like defects 34 are formed on the surface of the AlN layer 13 .
  • the thermal cleaning is performed and the pre-flow of the Al source is further performed, nevertheless, pit-like defects are observed on the surface of the AlN layer 13 .
  • the N source flow ratio is set to 50% in order to improve the crystal quality of the AlN layer 13 . Since the crystal quality of the AlN layer 13 is affected by the number of cracks, it is required to prevent the crystal quality of the AlN layer 13 from being degraded.
  • the inventors divided the AlN layer 13 into two layers of the first AlN layer 11 and the second AlN layer 12 and set the N source flow ratio for the first AlN layer 11 to a comparatively high level in order to improve the crystal quality of the AlN layer.
  • the inventors set the N source for the second AlN layer 12 that forms the surface of the AlN layer 13 to a comparatively low level. The inventors found out that the above division and setting reduce the number of pits on the surface of the AlN layer 13 .
  • the ratio (Al source flow ratio)/(N source flow ratio) is defined as a V/III source ratio.
  • a sample C was fabricated as the first embodiment.
  • the principal plane of he Si substrate 10 is the (111) plane, and the growth plane of the AlN layer is (0001) plane.
  • Annealing temperature 1050° C.
  • FIG. 8 is a graph of the pit density associated with the NH 3 flow ratio.
  • the NH 3 flow ratio is the ratio of the quantity of flow of NH 3 that is the N source to the total quantity of flow of the source gases (total quantity of flow of the N source and the Al source).
  • the pit density is the density of pits on the surface of the second AlN layer 12 in FIG. 1D .
  • the pit density was obtained by counting pits on the SEM image and dividing the number of pits by the area. As illustrated in FIG. 8 , the pit density starts to decrease when the NH 3 flow ratio becomes lower than 50%, and further decreases when the NH 3 flow ratio becomes lower than 25%. The pit density is very low when the NH 3 flow ratio is lower that 5%.
  • FIG. 9 is a picture of a SEM image of the surface of the second AlN layer 12 of the sample C when the NH 3 flow ratio for the second AlN layer 12 is set equal to 3%. As illustrated in FIG. 9 , pit-like defects are little observed. A white and back pattern results from the same reason as has been described with reference to FIG. 6 .
  • the crystal quality of the AlN layer 13 can be secured and the bit density can be reduced by growing the second AlN layer 12 by using the second V/III source ratio that is greater than the first V/III source ratio used for growing the first AlN layer 11 .
  • the ratio (the first V/III source flow ratio)/(the second V/III source flow ratio) is preferably greater than or equal to 2 (the NH 3 flow ratio is less than or equal to 25% in FIG. 8 ), and is more preferably greater than or equal to 10 (the NH 3 flow ratio is less than or equal to 5% in FIG. 8 ).
  • the AlN layer 13 may be formed by preferably setting the ratio (the first V/III source flow ratio)/(the second V/III source flow ratio) to not greater than 4000 and by more preferably setting the ratio to not greater than 1000.
  • the thermal cleaning is carried out in a hydrogen atmosphere under the condition that the thermal cleaning temperature is higher than or equal to 700° C. and is lower than or equal to 1060° C., and the thermal cleaning time is longer than or equal to 5 minutes and is shorter than or equal to 15 minutes.
  • the Al source is supplied while the N source is not supplied, and then both the Al source and the N source are supplied.
  • the first AlN layer 11 is grown on the Si substrate 10 with the first V/III source ratio.
  • the second AlN layer 12 is formed on the first AlN layer 11 with the second V/III source ratio that is greater than the first V/III source ratio. It is thus possible to suppress the occurrence of pit-like defects on the surface of the AlN layer 13 . This makes it possible to suppress the adverse effects on the process for fabricating the transistor due to the pit-like defects and to suppress the degradation of the transistor characteristics.
  • the total quantity of pre-flow of the Al source is preferably not less than 3.5 ⁇ mol in order to improve the AlN layer 13 .
  • the Al source is not limited to TMA but may be another material such as triethylaluminium (TEA).
  • TMA triethylaluminium
  • the N source is not limited to NH 3 but may be dimethylhydrazine.
  • the sheet resistance is preferably not less than 100 kQ/ ⁇ , and is more preferably not less than 150 kQ/ ⁇ , and much more preferably not less than 200 kQ/ ⁇ .
  • the AlN layer 13 may not function as the buffer layer sufficiently.
  • impurities such as Ga that diffuse into the Si substrate 10 serve as dopants, which may cause a leakage current.
  • the semiconductor device may have a warp due to stress.
  • the thickness of the AlN layer 13 is not less than 200 nm and is not greater than 400 nm.
  • the thickness of the AlN layer 13 may be not less than 250 nm and may be not greater than 350 nm.
  • the first AlN layer 11 is preferably thinner than the second AlN layer 12 .
  • the thickness of the second AlN 12 is preferably not less than 100 nm and is not greater than 400 nm in terms of suppression of the pit density. More preferably, the thickness of the second AlN layer is not less than 200 nm and is not greater than 350 nm.
  • the GaN-based semiconductor is a semiconductor including GaN, and includes, besides GaN and AlGaN, InGaN that is a mixed crystal of GaN and InN (indium nitride) and AlInGaN that is a mixed crystal of GaN, AlN and InN.
  • the GaN-based semiconductor layer 21 may include any of the above-described GaN-based semiconductor besides the above-described structures.
  • the present invention is not limited to HEMT but may include transistors such as FETs besides HEMT.
  • the present invention may include laser diodes and photodiodes.

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Organic Chemistry (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Metallurgy (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Chemical Vapour Deposition (AREA)
US13/172,403 2010-06-30 2011-06-29 Method for fabricating semiconductor device Active 2032-02-08 US8987015B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010150060A JP5668339B2 (ja) 2010-06-30 2010-06-30 半導体装置の製造方法
JP2010-150060 2010-06-30

Publications (2)

Publication Number Publication Date
US20120003821A1 US20120003821A1 (en) 2012-01-05
US8987015B2 true US8987015B2 (en) 2015-03-24

Family

ID=45400030

Family Applications (1)

Application Number Title Priority Date Filing Date
US13/172,403 Active 2032-02-08 US8987015B2 (en) 2010-06-30 2011-06-29 Method for fabricating semiconductor device

Country Status (2)

Country Link
US (1) US8987015B2 (ja)
JP (1) JP5668339B2 (ja)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5127978B1 (ja) * 2011-09-08 2013-01-23 株式会社東芝 窒化物半導体素子、窒化物半導体ウェーハ及び窒化物半導体層の製造方法
JP5829152B2 (ja) * 2012-03-08 2015-12-09 株式会社サイオクス 窒化ガリウムテンプレート基板の製造方法及び窒化ガリウムテンプレート基板
WO2013138016A2 (en) * 2012-03-15 2013-09-19 Dow Corning Corporation Method of quantitatively characterizing adulterants of silanes and coated susceptor
JP6015053B2 (ja) * 2012-03-26 2016-10-26 富士通株式会社 半導体装置の製造方法及び窒化物半導体結晶の製造方法
JP5733258B2 (ja) * 2012-03-30 2015-06-10 日立金属株式会社 窒化物半導体エピタキシャルウェハの製造方法
US10622468B2 (en) * 2017-02-21 2020-04-14 QROMIS, Inc. RF device integrated on an engineered substrate
EP3731260A4 (en) * 2017-12-19 2021-12-22 Sumco Corporation METHOD OF MANUFACTURING GROUP III NITRIDE SEMICONDUCTOR SUBSTRATE
EP3751023A4 (en) * 2018-02-08 2021-10-27 Sumitomo Chemical Company Limited SEMICONDUCTOR WAFER
JP6962463B2 (ja) 2018-05-23 2021-11-05 株式会社Sumco Ｉｉｉ族窒化物半導体基板の製造方法
DE102020003801A1 (de) 2019-07-18 2021-01-21 Sew-Eurodrive Gmbh & Co Kg Verfahren und System zum Betreiben eines Systems mit Energiespeicher und Widerstand
CN111354629B (zh) * 2020-04-26 2023-04-07 江西力特康光学有限公司 一种用于紫外LED的AlN缓冲层结构及其制作方法
EP4345922B8 (en) * 2022-09-30 2025-06-11 ALLOS Semiconductors GmbH Gan-on-si epiwafer comprising a strain-decoupling sub-stack

Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6303473B1 (en) * 1997-12-18 2001-10-16 Sharp Kabushiki Kaisha Method of growing group III or group III-V nitride layer
US6391748B1 (en) * 2000-10-03 2002-05-21 Texas Tech University Method of epitaxial growth of high quality nitride layers on silicon substrates
US6869702B2 (en) * 2002-12-18 2005-03-22 Ngk Insulators, Ltd. Substrate for epitaxial growth
US20060094145A1 (en) * 2003-06-06 2006-05-04 Sanken Electric Co., Ltd. Nitride-based semiconductor device and method of fabrication
US20060261370A1 (en) * 2005-05-19 2006-11-23 Raytheon Company Gallium nitride high electron mobility transistor structure
US20070045662A1 (en) * 2005-08-26 2007-03-01 Dowa Mining Co., Ltd. Substrate for film growth of group iii nitrides, method of manufacturing the same, and semiconductor device using the same
US20070238315A1 (en) 2006-04-06 2007-10-11 Interuniversitair Microelektronica Centrum (Imec) Method for forming a group iii nitride material on a silicon substrate
JP2008166349A (ja) 2006-12-27 2008-07-17 Eudyna Devices Inc 半導体基板および半導体装置
US20090008647A1 (en) * 2007-07-06 2009-01-08 Sharp Laboratories Of America Inc. Gallium nitride-on-silicon interface using multiple aluminum compound buffer layers
WO2009020235A1 (ja) 2007-08-09 2009-02-12 Showa Denko K.K. Ｉｉｉ族窒化物半導体エピタキシャル基板
US7566580B2 (en) * 2006-11-15 2009-07-28 The Regents Of The University Of California Method for heteroepitaxial growth of high-quality N-face GaN, InN, and AIN and their alloys by metal organic chemical vapor deposition
JP2009231550A (ja) 2008-03-24 2009-10-08 Oki Electric Ind Co Ltd 半導体装置の製造方法
US20100090244A1 (en) * 2005-03-14 2010-04-15 Yasuo Ohba Light emitting device
US20100240198A1 (en) * 2009-03-23 2010-09-23 Sumitomo Electric Device Innovations, Inc. Method for fabricating semiconductor device
US20120025252A1 (en) * 2009-03-03 2012-02-02 Riken Composite substrate for formation of light-emitting device, light-emitting diode device and manufacturing method thereof
US8264006B2 (en) * 2007-03-30 2012-09-11 Fujitsu Limited Compound semiconductor device including AIN layer of controlled skewness
US8324005B2 (en) * 2007-03-09 2012-12-04 Cree, Inc. Methods of fabricating nitride semiconductor structures with interlayer structures

Patent Citations (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6303473B1 (en) * 1997-12-18 2001-10-16 Sharp Kabushiki Kaisha Method of growing group III or group III-V nitride layer
US6391748B1 (en) * 2000-10-03 2002-05-21 Texas Tech University Method of epitaxial growth of high quality nitride layers on silicon substrates
US6869702B2 (en) * 2002-12-18 2005-03-22 Ngk Insulators, Ltd. Substrate for epitaxial growth
US20060094145A1 (en) * 2003-06-06 2006-05-04 Sanken Electric Co., Ltd. Nitride-based semiconductor device and method of fabrication
US20100090244A1 (en) * 2005-03-14 2010-04-15 Yasuo Ohba Light emitting device
US20060261370A1 (en) * 2005-05-19 2006-11-23 Raytheon Company Gallium nitride high electron mobility transistor structure
US20070045662A1 (en) * 2005-08-26 2007-03-01 Dowa Mining Co., Ltd. Substrate for film growth of group iii nitrides, method of manufacturing the same, and semiconductor device using the same
JP2007059850A (ja) 2005-08-26 2007-03-08 Ngk Insulators Ltd Ｉｉｉ族窒化物成膜用基板及びその製造方法並びにそれを用いた半導体装置
JP2007281478A (ja) 2006-04-06 2007-10-25 Interuniv Micro Electronica Centrum Vzw シリコン基板上にｉｉｉ族窒化物材料を積層するための方法
US20070238315A1 (en) 2006-04-06 2007-10-11 Interuniversitair Microelektronica Centrum (Imec) Method for forming a group iii nitride material on a silicon substrate
US7566580B2 (en) * 2006-11-15 2009-07-28 The Regents Of The University Of California Method for heteroepitaxial growth of high-quality N-face GaN, InN, and AIN and their alloys by metal organic chemical vapor deposition
US20080210949A1 (en) * 2006-12-27 2008-09-04 Eudyna Devices Inc. Semiconductor substrate and semiconductor device using the same
JP2008166349A (ja) 2006-12-27 2008-07-17 Eudyna Devices Inc 半導体基板および半導体装置
US8324005B2 (en) * 2007-03-09 2012-12-04 Cree, Inc. Methods of fabricating nitride semiconductor structures with interlayer structures
US8264006B2 (en) * 2007-03-30 2012-09-11 Fujitsu Limited Compound semiconductor device including AIN layer of controlled skewness
US20090008647A1 (en) * 2007-07-06 2009-01-08 Sharp Laboratories Of America Inc. Gallium nitride-on-silicon interface using multiple aluminum compound buffer layers
WO2009020235A1 (ja) 2007-08-09 2009-02-12 Showa Denko K.K. Ｉｉｉ族窒化物半導体エピタキシャル基板
US20110254048A1 (en) 2007-08-09 2011-10-20 Showa Denko K.K. Group iii nitride semiconductor epitaxial substrate
JP2009231550A (ja) 2008-03-24 2009-10-08 Oki Electric Ind Co Ltd 半導体装置の製造方法
US20120025252A1 (en) * 2009-03-03 2012-02-02 Riken Composite substrate for formation of light-emitting device, light-emitting diode device and manufacturing method thereof
US20100240198A1 (en) * 2009-03-23 2010-09-23 Sumitomo Electric Device Innovations, Inc. Method for fabricating semiconductor device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Japanese Office Action dated Mar. 4, 2014, issued in corresponding Japanese Patent Application No. 2010-150060, w/English translation (6 pages).

Also Published As

Publication number Publication date
JP2012015305A (ja) 2012-01-19
JP5668339B2 (ja) 2015-02-12
US20120003821A1 (en) 2012-01-05

Similar Documents

Publication Publication Date Title
US8987015B2 (en) Method for fabricating semiconductor device
US8173464B2 (en) Method for fabricating semiconductor device
US9548376B2 (en) Method of manufacturing a semiconductor device including a barrier structure
JP5099008B2 (ja) ＳｉＣ基板を用いた化合物半導体装置とその製造方法
US8754419B2 (en) Semiconductor device
JP6024075B2 (ja) 半導体装置およびその製造方法
US20120313145A1 (en) Semiconductor device with spacer layer between carrier traveling layer and carrier supplying layer
US8546813B2 (en) Semiconductor substrate and semiconductor device
US20160079370A1 (en) Semiconductor device, semiconductor wafer, and semiconductor device manufacturing method
US7947578B2 (en) Method for fabricating semiconductor device
Umeno et al. GaN-based optoelectronic devices on sapphire and Si substrates
JP2006114652A (ja) 半導体エピタキシャルウェハ及び電界効果トランジスタ
US8524550B2 (en) Method of manufacturing semiconductor device and semiconductor device
US9437725B2 (en) Semiconductor device and semiconductor substrate
JP5248743B2 (ja) 半導体装置および半導体装置の製造方法
JP2006114655A (ja) 半導体エピタキシャルウェハ及び電界効果トランジスタ
JP2011228442A (ja) 窒化物系半導体ウエハ及び窒化物系半導体デバイス
US8410524B2 (en) Group III nitride semiconductor device and epitaxial substrate
US12334340B2 (en) Epitaxial wafer, semiconductor device, and method for manufacturing epitaxial wafer
JP2007123824A (ja) Ｉｉｉ族窒化物系化合物半導体を用いた電子装置
JP6819009B2 (ja) 半導体基板の製造方法
US20200194580A1 (en) Nitride semiconductor substrate and nitride semiconductor device
US8283240B2 (en) Method for fabricating semiconductor device
JP2006196557A (ja) 半導体エピタキシャルウェハ及び電界効果トランジスタ
JP2006114653A (ja) 半導体エピタキシャルウェハ及び電界効果トランジスタ

Legal Events

Date Code Title Description
AS Assignment

Owner name: SUMITOMO ELECTRIC INDUSTRIES, LTD., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YUI, KEIICHI;FURUYA, AKIRA;NAKATA, KEN;AND OTHERS;REEL/FRAME:026576/0689

Effective date: 20110623

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 8