[go: up one dir, main page]

US7627071B2 - Timing synchronization module and method for synchronously playing a media signal - Google Patents

Timing synchronization module and method for synchronously playing a media signal Download PDF

Info

Publication number
US7627071B2
US7627071B2 US11/366,427 US36642706A US7627071B2 US 7627071 B2 US7627071 B2 US 7627071B2 US 36642706 A US36642706 A US 36642706A US 7627071 B2 US7627071 B2 US 7627071B2
Authority
US
United States
Prior art keywords
clock signal
signal
end clock
reception
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related, expires
Application number
US11/366,427
Other versions
US20060215741A1 (en
Inventor
Yi-Lon Chin
Chang-Hung Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qisda Corp
Original Assignee
Qisda Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qisda Corp filed Critical Qisda Corp
Assigned to BENQ CORPORATION reassignment BENQ CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHIN, YI-LON, LEE, CHANG-HUNG
Publication of US20060215741A1 publication Critical patent/US20060215741A1/en
Assigned to QISDA CORPORATION reassignment QISDA CORPORATION CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: BENQ CORPORATION
Application granted granted Critical
Publication of US7627071B2 publication Critical patent/US7627071B2/en
Expired - Fee Related legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/60—Network structure or processes for video distribution between server and client or between remote clients; Control signalling between clients, server and network components; Transmission of management data between server and client, e.g. sending from server to client commands for recording incoming content stream; Communication details between server and client 
    • H04N21/61—Network physical structure; Signal processing
    • H04N21/6106—Network physical structure; Signal processing specially adapted to the downstream path of the transmission network
    • H04N21/6131—Network physical structure; Signal processing specially adapted to the downstream path of the transmission network involving transmission via a mobile phone network
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/4302—Content synchronisation processes, e.g. decoder synchronisation
    • H04N21/4305—Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets

Definitions

  • the invention relates in general to a timing module and method for playing a media signal, and more particularly to a timing synchronization module and method for synchronously playing a media signal.
  • Wireless broadband network has stepped into a widespread stage, and is applied in international airports, hotels, restaurants, coffee chains for instance.
  • the users can just roam leisurely in network world by inserting wireless local area network (LAN) cards into their notebook computers or personal digital assistants (PDAs).
  • LAN local area network
  • PDAs personal digital assistants
  • the output module In addition to outputting data such as images and sounds to the reception module, the output module outputs clock signals to the reception module as a signal synchronization reference for the reception module.
  • the clock signals outputted by the output module may be incomplete at the beginning, or become incomplete as received by the reception module due to network delay, interference, or other factors in transmission. As a result, the media signals cannot be synchronized and played successfully.
  • the Media signal is played synchronously based on the difference between the output-end clock signal and the reception-end clock signal.
  • the invention achieves the above-identified object by providing a timing synchronization module for control the playing of a media signal.
  • the timing synchronization module includes a phase locked loop (PLL) and a synchronization processing unit.
  • the PLL is for receiving an output-end clock signal.
  • the PLL receives the output-end clock signal for the first time, the PLL generates a reception-end clock signal according to the output-end clock signal.
  • the synchronization processing unit is for receiving a procedure clock signal and the reception-end clock signal.
  • the output-end clock signal has M clocks after the reception-end clock signal is generated, the reception-end clock signal has N clocks as generated, and when a difference value of M and N is larger than a preset value, the synchronization processing unit removes the media signal corresponding to the procedure clock signal and generates the reception-end clock signal again.
  • the difference value is smaller than the preset value, the PLL outputs the reception-end clock signal, and the synchronization processing unit controls the playing of the media signal according to the reception-end clock signal and the procedure clock signal.
  • the invention achieves the above-identified object by providing a method for synchronously playing a media signal.
  • the method includes receiving an output-end clock signal; determining whether the output-end clock signal is received for the first time, and if yes, generating a reception-end clock signal according to the output-end clock signal, wherein the output-end clock signal has M clocks after the reception-end clock signal is generated and the reception-end clock signal has N clocks as generated; determining whether a difference value of M and N is larger than a preset value; if yes, removing the media signal corresponding to a procedure clock signal, generating again the reception-end clock signal and returning to the step of receiving an output-end clock signal; and if not, controlling the playing of the media signal according to the reception-end clock signal and the procedure clock signal and repeating the step of determining whether a difference between M and N is larger than a preset value.
  • FIG. 1 is a block diagram of a reception module according to the first embodiment of the invention.
  • FIG. 2 is a block diagram of a reception module according to the second embodiment of the invention.
  • FIG. 3 is a flow chart of the method for synchronously playing media signals used in a reception module according to the first embodiment of the invention.
  • FIG. 4 is a flow chart of the method for synchronously playing media signals used in the reception module according to the second embodiment of the invention.
  • the reception module 100 includes a timing synchronization module 110 and a signal processing module 120 .
  • the timing synchronization module 110 for controlling the playing of media signals S 3 , includes a phase locked loop (PLL) and a synchronization processing unit 112 .
  • the PLL 111 is for receiving output-end clock signals Ctx. When the PLL 111 receives the output-end clock signal Ctx for the first time, the PLL 111 generates a reception-end clock signal Crx according to the output-end clock signal Ctx.
  • the synchronization processing unit 112 is for receiving a procedure clock signal C 1 and the reception-end clock signal Crx.
  • the signal processing module 120 includes a depacketizer 121 and a decoder 122 .
  • the depacketizer 121 receives a packet signal S 1 and outputs a depacketized signal S 2 .
  • the decoder 122 receives and decodes the depacketized signal S 2 , and then outputs the media signal S 3 and the procedure clock signal C 1 .
  • the packet signal S 1 and the output-end clock signal Ctx are transmitted through wireless network.
  • the output-end signal Ctx has M clocks after the reception-end signal Crx is generated and the reception-end signal Crx has N clocks as generated. Synchronization is determined according to the comparison of the difference value K of M and N, and a preset value Th.
  • the synchronization processing unit 112 controls the decoder 122 by a control signal S 4 to remove the media signal S 3 corresponding to the procedure clock signal C 1 , and the PLL 111 generates a reception-end clock signal Crx again according to the output-end clock signal Ctx.
  • the PLL 111 When the difference value K is smaller than the preset Th, the PLL 111 outputs the reception-end clock signal Crx, and the synchronization processing unit 112 controls the playing of the media signal S 3 by the control signal S 4 according to the reception-end clock signal Crx and the procedure clock signal C 1 .
  • the reception module 200 includes a timing synchronization module 210 and the signal processing module 120 .
  • the signal processing module 120 the same as that in the first embodiment, is not necessary to be described again.
  • the timing synchronization module 210 for controlling the playing of the media signal S 3 , includes a PLL 211 , a synchronization processing unit 212 , and a decoder buffer 213 .
  • the PLL 211 is for receiving an output-end clock signal Ctx.
  • the PLL 211 When the PLL 211 receives the output-end clock signal Ctx for the first time, the PLL 211 generates a reception-end clock signal according to the output-end clock signal Ctx.
  • the synchronization processing unit 212 receives a procedure clock signal C 1 and the reception-end clock signal Crx.
  • the output-end clock signal Ctx is transmitted through wireless network.
  • the output-end clock signal Ctx has M pulses after the reception-end clock signal Crx is generated while the reception-end clock signal Crx has N pulses as generated. Synchronization is determined according to the comparison of the difference value K of M and N with a first preset value Th 1 and a second preset value Th 2 , wherein the first preset value Th 1 is larger than the second preset value Th 2 .
  • the synchronization processing unit 212 removes the media signal S 3 corresponding to the procedure clock signal C 1 , and the PLL 211 generates a reception-end clock signal Crx again according to the output-end clock signal Ctx.
  • the PLL 211 When the difference value K is smaller than the second preset value Th 2 , the PLL 211 outputs the reception-end clock signal Crx while the synchronization processing unit 212 controls the playing of the media signal S 3 according to the reception-end clock signal Crx and the procedure clock signal C 1 .
  • the synchronization processing unit 212 adjusts the capacity value BT of the decoder buffer 213 such that the media signal S 3 corresponding to the procedure clock signal C 1 is temporarily stored in the decoder buffer 213 , and adjusts the speed of playing the media signal S 3 .
  • the capacity value BT of the decoder buffer 213 is adjusted according to whether the reception-end clock signal Crx falls behind the output-end clock signal Ctx, that is, whether N is smaller than M. If N is smaller than M, the capacity value BT of the decoder buffer 213 is reduced while if N is larger than M, the capacity value BT of the decoder buffer 213 is increased.
  • the media signal S 3 is an audio signal
  • the original playing speed of 44100 Hz is reduced to 16000 Hz for instance
  • the media signal S 3 is a video signal
  • the original playing speed of 30 fps is reduced to 24 fps for instance.
  • step 31 receive an output-end clock signal Ctx.
  • step 32 determine whether the output-end clock signal is received for the first time. If yes, go to the step 33 to generate a reception-end clock signal Crx according to the output-end clock signal Ctx. If not, go to the step 34 to determine whether the difference value K between M and N is larger than a preset value Th.
  • the output-end clock signal Ctx has M clocks after the reception-end clock signal Crx is generated while the reception-end clock signal Crx has N clocks as generated.
  • step 35 If K is larger than Th, go to step 35 to remove the media signal S 3 corresponding to the procedure clock signal C 1 , and return to the step 33 . If K is smaller than Th, go to step 36 to control the playing of the media signal S 3 according to the reception-end clock signal Crx and the procedure clock signal C 1 , and repeat the step 34 .
  • step 41 receive an output-end clock signal Ctx.
  • step 42 determine whether the output-end clock signal Ctx is received for the first time. If yes, go to step 43 to generate a reception clock signal Crx according to the output-end clock signal Ctx and return to the step 41 . If not, go to step 44 to determine the relationship among the difference value K of M and N, the first preset value Th 1 and the second preset value Th 2 .
  • the output-end clock signal Ctx has M pulses after the reception-end clock signal is generated while the reception-end clock signal has N pulses as generated.
  • the first preset value Th 1 is larger than the second preset value Th 2 .
  • step 45 When the difference value K is larger than the first preset value Th 1 , go to step 45 to remove the media signal S 3 corresponding to the procedure clock signal C 1 and return to the step 43 .
  • step 46 When the difference value K is smaller than the second preset value Th 2 , go to step 46 to control the playing of the media signal S 3 according to the reception-end clock signal Crx and the procedure clock signal C 1 , and return to the step 44 .
  • step 47 If the difference value K is smaller than the first preset value Th 1 and larger than the second preset value Th 2 , go to step 47 to calculate and adjust the capacity value BT of the decoder buffer 213 . Afterward, in step 48 , store temporarily the media signal S 3 in the decoder buffer 213 . Then in step 49 , adjust the speed of playing the media signal S 3 and return to the step 44 .
  • the reception-end clock signal is generated by the output-end clock signal and synchronization is determined according to the difference between the reception-end clock signal and the output-end clock signal. Therefore, it can be prevented that wireless network interference and other factors result in the playing delay issue in playing media signals.

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)

Abstract

The timing synchronization module includes a phase locked loop (PLL) and a synchronization processing unit. The PLL receives an output-end clock signal. When the PLL receives the output-end clock signal for the first time, the PLL generates a reception-end clock signal according to the output-end clock signal. The synchronization processing unit receives a procedure clock signal and the reception-end clock signal. The output-end clock signal has M clocks after the reception-end clock signal is generated, while the reception-end clock signal has N clocks as generated. When the difference value of M and N is larger than a preset value, the synchronization processing unit removes the media signal corresponding to the procedure clock signal and generates the reception-end clock signal again. When the difference value is smaller than the preset value, the synchronization processing unit controls media signal playing according to the reception-end clock signal and the procedure clock signal.

Description

This application claims the benefit of Taiwan application Serial No. 94107379, filed Mar. 10, 2005, the subject matter of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a timing module and method for playing a media signal, and more particularly to a timing synchronization module and method for synchronously playing a media signal.
2. Description of the Related Art
Wireless broadband network has stepped into a widespread stage, and is applied in international airports, hotels, restaurants, coffee chains for instance. The users can just roam leisurely in network world by inserting wireless local area network (LAN) cards into their notebook computers or personal digital assistants (PDAs). Network resources can therefore be rapidly and conveniently retrieved and applied without space limitation.
In a real-time encoder system, using wireless broadband technology to transmit media data and play the data instantly is also an application of the wireless technology. In addition to outputting data such as images and sounds to the reception module, the output module outputs clock signals to the reception module as a signal synchronization reference for the reception module.
However, the clock signals outputted by the output module may be incomplete at the beginning, or become incomplete as received by the reception module due to network delay, interference, or other factors in transmission. As a result, the media signals cannot be synchronized and played successfully.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a timing synchronization module and method for synchronously playing a media signal. The Media signal is played synchronously based on the difference between the output-end clock signal and the reception-end clock signal.
The invention achieves the above-identified object by providing a timing synchronization module for control the playing of a media signal. The timing synchronization module includes a phase locked loop (PLL) and a synchronization processing unit. The PLL is for receiving an output-end clock signal. When the PLL receives the output-end clock signal for the first time, the PLL generates a reception-end clock signal according to the output-end clock signal. The synchronization processing unit is for receiving a procedure clock signal and the reception-end clock signal. The output-end clock signal has M clocks after the reception-end clock signal is generated, the reception-end clock signal has N clocks as generated, and when a difference value of M and N is larger than a preset value, the synchronization processing unit removes the media signal corresponding to the procedure clock signal and generates the reception-end clock signal again. When the difference value is smaller than the preset value, the PLL outputs the reception-end clock signal, and the synchronization processing unit controls the playing of the media signal according to the reception-end clock signal and the procedure clock signal.
The invention achieves the above-identified object by providing a method for synchronously playing a media signal. The method includes receiving an output-end clock signal; determining whether the output-end clock signal is received for the first time, and if yes, generating a reception-end clock signal according to the output-end clock signal, wherein the output-end clock signal has M clocks after the reception-end clock signal is generated and the reception-end clock signal has N clocks as generated; determining whether a difference value of M and N is larger than a preset value; if yes, removing the media signal corresponding to a procedure clock signal, generating again the reception-end clock signal and returning to the step of receiving an output-end clock signal; and if not, controlling the playing of the media signal according to the reception-end clock signal and the procedure clock signal and repeating the step of determining whether a difference between M and N is larger than a preset value.
Other objects, features, and advantages of the invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a reception module according to the first embodiment of the invention.
FIG. 2 is a block diagram of a reception module according to the second embodiment of the invention.
FIG. 3 is a flow chart of the method for synchronously playing media signals used in a reception module according to the first embodiment of the invention.
FIG. 4 is a flow chart of the method for synchronously playing media signals used in the reception module according to the second embodiment of the invention.
 DETAILED DESCRIPTION OF THE INVENTION
Referring to FIG. 1, a block diagram of a reception module according to the first embodiment of the invention is shown. The reception module 100 includes a timing synchronization module 110 and a signal processing module 120. The timing synchronization module 110, for controlling the playing of media signals S3, includes a phase locked loop (PLL) and a synchronization processing unit 112. The PLL 111 is for receiving output-end clock signals Ctx. When the PLL 111 receives the output-end clock signal Ctx for the first time, the PLL 111 generates a reception-end clock signal Crx according to the output-end clock signal Ctx. The synchronization processing unit 112 is for receiving a procedure clock signal C1 and the reception-end clock signal Crx. The signal processing module 120 includes a depacketizer 121 and a decoder 122. The depacketizer 121 receives a packet signal S1 and outputs a depacketized signal S2. The decoder 122 receives and decodes the depacketized signal S2, and then outputs the media signal S3 and the procedure clock signal C1. Moreover, the packet signal S1 and the output-end clock signal Ctx are transmitted through wireless network.
Suppose the output-end signal Ctx has M clocks after the reception-end signal Crx is generated and the reception-end signal Crx has N clocks as generated. Synchronization is determined according to the comparison of the difference value K of M and N, and a preset value Th. When the difference value K is larger than the preset value Th, the synchronization processing unit 112 controls the decoder 122 by a control signal S4 to remove the media signal S3 corresponding to the procedure clock signal C1, and the PLL 111 generates a reception-end clock signal Crx again according to the output-end clock signal Ctx. When the difference value K is smaller than the preset Th, the PLL 111 outputs the reception-end clock signal Crx, and the synchronization processing unit 112 controls the playing of the media signal S3 by the control signal S4 according to the reception-end clock signal Crx and the procedure clock signal C1.
Referring to FIG. 2, a block diagram of a reception module according to the second embodiment of the invention is shown. The reception module 200 includes a timing synchronization module 210 and the signal processing module 120. The signal processing module 120, the same as that in the first embodiment, is not necessary to be described again. The timing synchronization module 210, for controlling the playing of the media signal S3, includes a PLL 211, a synchronization processing unit 212, and a decoder buffer 213. The PLL 211 is for receiving an output-end clock signal Ctx. When the PLL 211 receives the output-end clock signal Ctx for the first time, the PLL 211 generates a reception-end clock signal according to the output-end clock signal Ctx. The synchronization processing unit 212 receives a procedure clock signal C1 and the reception-end clock signal Crx. The output-end clock signal Ctx is transmitted through wireless network.
The output-end clock signal Ctx has M pulses after the reception-end clock signal Crx is generated while the reception-end clock signal Crx has N pulses as generated. Synchronization is determined according to the comparison of the difference value K of M and N with a first preset value Th1 and a second preset value Th2, wherein the first preset value Th1 is larger than the second preset value Th2. When the difference value K is larger than the first preset value Th1, the synchronization processing unit 212 removes the media signal S3 corresponding to the procedure clock signal C1, and the PLL 211 generates a reception-end clock signal Crx again according to the output-end clock signal Ctx. When the difference value K is smaller than the second preset value Th2, the PLL 211 outputs the reception-end clock signal Crx while the synchronization processing unit 212 controls the playing of the media signal S3 according to the reception-end clock signal Crx and the procedure clock signal C1.
When the difference value C1 is smaller than the first preset value Th1 and larger than the second preset value Th2, the synchronization processing unit 212 adjusts the capacity value BT of the decoder buffer 213 such that the media signal S3 corresponding to the procedure clock signal C1 is temporarily stored in the decoder buffer 213, and adjusts the speed of playing the media signal S3. The capacity value BT of the decoder buffer 213 is adjusted according to whether the reception-end clock signal Crx falls behind the output-end clock signal Ctx, that is, whether N is smaller than M. If N is smaller than M, the capacity value BT of the decoder buffer 213 is reduced while if N is larger than M, the capacity value BT of the decoder buffer 213 is increased. In the process of adjusting the speed of playing the media signal S3, if the media signal S3 is an audio signal, the original playing speed of 44100 Hz is reduced to 16000 Hz for instance, and if the media signal S3 is a video signal, the original playing speed of 30 fps is reduced to 24 fps for instance.
Referring to FIG. 3, a flow chart of the method for synchronously playing media signals used in a reception module 100 according to the first embodiment of the invention is shown. First, in step 31, receive an output-end clock signal Ctx. Next, in step 32, determine whether the output-end clock signal is received for the first time. If yes, go to the step 33 to generate a reception-end clock signal Crx according to the output-end clock signal Ctx. If not, go to the step 34 to determine whether the difference value K between M and N is larger than a preset value Th. The output-end clock signal Ctx has M clocks after the reception-end clock signal Crx is generated while the reception-end clock signal Crx has N clocks as generated. If K is larger than Th, go to step 35 to remove the media signal S3 corresponding to the procedure clock signal C1, and return to the step 33. If K is smaller than Th, go to step 36 to control the playing of the media signal S3 according to the reception-end clock signal Crx and the procedure clock signal C1, and repeat the step 34.
Referring to FIG. 4, a flow chart of the method for synchronously playing media signals used in the reception module 200 according to the second embodiment of the invention is shown. First, in step 41, receive an output-end clock signal Ctx. Afterward, in step 42, determine whether the output-end clock signal Ctx is received for the first time. If yes, go to step 43 to generate a reception clock signal Crx according to the output-end clock signal Ctx and return to the step 41. If not, go to step 44 to determine the relationship among the difference value K of M and N, the first preset value Th1 and the second preset value Th2. The output-end clock signal Ctx has M pulses after the reception-end clock signal is generated while the reception-end clock signal has N pulses as generated. The first preset value Th1 is larger than the second preset value Th2.
When the difference value K is larger than the first preset value Th1, go to step 45 to remove the media signal S3 corresponding to the procedure clock signal C1 and return to the step 43. When the difference value K is smaller than the second preset value Th2, go to step 46 to control the playing of the media signal S3 according to the reception-end clock signal Crx and the procedure clock signal C1, and return to the step 44.
If the difference value K is smaller than the first preset value Th1 and larger than the second preset value Th2, go to step 47 to calculate and adjust the capacity value BT of the decoder buffer 213. Afterward, in step 48, store temporarily the media signal S3 in the decoder buffer 213. Then in step 49, adjust the speed of playing the media signal S3 and return to the step 44.
In the timing synchronization module and method for synchronously playing media signals disclosed by the above-mentioned embodiments of the invention, the reception-end clock signal is generated by the output-end clock signal and synchronization is determined according to the difference between the reception-end clock signal and the output-end clock signal. Therefore, it can be prevented that wireless network interference and other factors result in the playing delay issue in playing media signals.
While the invention has been described by way of example and in terms of a preferred embodiment, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.

Claims (4)

1. A timing synchronization module, for controlling the output of a media signal, the timing synchronization module comprising;
a phase locked loop (PLL), for receiving an output-end clock signal, wherein when the PLL receives the output-end clock signal for the first time, the PLL generates a reception-end clock signal according to the output-end clock signal;
a synchronization processing unit, for receiving a procedure clock signal and the output-end clock signal; and
a decoder buffer, wherein the output-end clock signal has M pulses after the reception-end clock signal is generated, the reception-end clock signal has N pulses as generated, wherein M and N are positive integers, and when a difference value between M and N is smaller than a first preset value and larger than a second preset value, the synchronization processing unit adjusts the volume of the decoder buffer so that the media signal corresponding to the procedure clock signal is stored temporarily in the decoder buffer, and adjusts the speed of playing the media signal;
wherein when the difference value is larger than the first preset value, the synchronization processing unit removes the media signal corresponding to the procedure clock signal, and the PLL generates the reception-end clock signal again according to the output-end clock signal;
wherein when the difference value is smaller than the second preset value, the PLL outputs the reception-end clock signal, and the synchronization processing unit controls the playing of the media signal according to the reception-end clock signal and the procedure clock signal.
2. The module according to claim 1, wherein the output-end clock signal is transmitted through wireless network.
3. The module according to claim 1, wherein the procedure clock signal and the media signal are outputted by a signal processing module, and the signal processing module comprises;
a depacketizer, for receiving the packet signal and outputting a depacketized signal; and
a decoder, for receiving and decoding the depacketized signal, and for outputting the media signal and the procedure clock signal.
4. The module according to claim 3, wherein the packet signal and the output-end clock signal are transmitted through wireless network.
US11/366,427 2005-03-10 2006-03-03 Timing synchronization module and method for synchronously playing a media signal Expired - Fee Related US7627071B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW94107379 2005-03-10
TW094107379A TWI267307B (en) 2005-03-10 2005-03-10 Timing synchronization module and method for synchronously playing media signal

Publications (2)

Publication Number Publication Date
US20060215741A1 US20060215741A1 (en) 2006-09-28
US7627071B2 true US7627071B2 (en) 2009-12-01

Family

ID=37035132

Family Applications (1)

Application Number Title Priority Date Filing Date
US11/366,427 Expired - Fee Related US7627071B2 (en) 2005-03-10 2006-03-03 Timing synchronization module and method for synchronously playing a media signal

Country Status (2)

Country Link
US (1) US7627071B2 (en)
TW (1) TWI267307B (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11294618B2 (en) 2003-07-28 2022-04-05 Sonos, Inc. Media player system
US11106424B2 (en) 2003-07-28 2021-08-31 Sonos, Inc. Synchronizing operations among a plurality of independently clocked digital data processing devices
US8234395B2 (en) 2003-07-28 2012-07-31 Sonos, Inc. System and method for synchronizing operations among a plurality of independently clocked digital data processing devices
US11106425B2 (en) 2003-07-28 2021-08-31 Sonos, Inc. Synchronizing operations among a plurality of independently clocked digital data processing devices
US8290603B1 (en) 2004-06-05 2012-10-16 Sonos, Inc. User interfaces for controlling and manipulating groupings in a multi-zone media system
US8020023B2 (en) 2003-07-28 2011-09-13 Sonos, Inc. Systems and methods for synchronizing operations among a plurality of independently clocked digital data processing devices without a voltage controlled crystal oscillator
US9207905B2 (en) 2003-07-28 2015-12-08 Sonos, Inc. Method and apparatus for providing synchrony group status information
US11650784B2 (en) 2003-07-28 2023-05-16 Sonos, Inc. Adjusting volume levels
US9977561B2 (en) 2004-04-01 2018-05-22 Sonos, Inc. Systems, methods, apparatus, and articles of manufacture to provide guest access

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5623483A (en) 1995-05-11 1997-04-22 Lucent Technologies Inc. Synchronization system for networked multimedia streams
US6970526B2 (en) * 2000-11-27 2005-11-29 Hynix Semiconductor Inc. Controlling the system time clock of an MPEG decoder
US20060072694A1 (en) * 2004-10-01 2006-04-06 Hui Dai Synchronizing clocks in wireless personal area networks
US20060161675A1 (en) * 2005-01-20 2006-07-20 Vixs Systems, Inc. System and method for multimedia delivery in a wireless environment
US20060182211A1 (en) * 2005-02-15 2006-08-17 Alcatel Synchronization system using redundant clock signals for equipment of a synchronous transport network
US7102446B1 (en) * 2005-02-11 2006-09-05 Silicon Image, Inc. Phase lock loop with coarse control loop having frequency lock detector and device including same
US20070009071A1 (en) * 2005-06-29 2007-01-11 Ranjan Singh Methods and apparatus to synchronize a clock in a voice over packet network
US7355652B2 (en) * 2004-10-13 2008-04-08 Cirrus Logic, Inc. Inverse tracking over two different clock domains
US7369000B2 (en) * 2004-04-15 2008-05-06 Mediatek Incorporation Adaptive frequency detector of phase locked loop

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5623483A (en) 1995-05-11 1997-04-22 Lucent Technologies Inc. Synchronization system for networked multimedia streams
US6970526B2 (en) * 2000-11-27 2005-11-29 Hynix Semiconductor Inc. Controlling the system time clock of an MPEG decoder
US7369000B2 (en) * 2004-04-15 2008-05-06 Mediatek Incorporation Adaptive frequency detector of phase locked loop
US20060072694A1 (en) * 2004-10-01 2006-04-06 Hui Dai Synchronizing clocks in wireless personal area networks
US7355652B2 (en) * 2004-10-13 2008-04-08 Cirrus Logic, Inc. Inverse tracking over two different clock domains
US20060161675A1 (en) * 2005-01-20 2006-07-20 Vixs Systems, Inc. System and method for multimedia delivery in a wireless environment
US7102446B1 (en) * 2005-02-11 2006-09-05 Silicon Image, Inc. Phase lock loop with coarse control loop having frequency lock detector and device including same
US20060182211A1 (en) * 2005-02-15 2006-08-17 Alcatel Synchronization system using redundant clock signals for equipment of a synchronous transport network
US20070009071A1 (en) * 2005-06-29 2007-01-11 Ranjan Singh Methods and apparatus to synchronize a clock in a voice over packet network

Also Published As

Publication number Publication date
TW200633543A (en) 2006-09-16
US20060215741A1 (en) 2006-09-28
TWI267307B (en) 2006-11-21

Similar Documents

Publication Publication Date Title
US7228059B2 (en) Audio reproducing apparatus and audio reproduction control method for use in the same
US7657829B2 (en) Audio and video buffer synchronization based on actual output feedback
US20100142927A1 (en) Audio and video synchronization apparatus and method in wireless communication network
US20020141451A1 (en) Clock slaving methods and arrangements
EP1195996A2 (en) Apparatus, method and computer program product for decoding and reproducing moving images, time control method and multimedia information receiving apparatus
US7627071B2 (en) Timing synchronization module and method for synchronously playing a media signal
KR20090079406A (en) Transmitter and receiver of moving picture transmission system, buffer control method thereof
WO2010116588A1 (en) Digital television broadcasting reproduction device and reproduction method therefor
KR20050094036A (en) Resynchronizing drifted data streams with a minimum of noticeable artifacts
US7656947B2 (en) Synchronization device and synchronization method in digital broadcast receiver
KR101787424B1 (en) Mechanism for clock recovery for streaming content being communicated over a packetized communication network
JP4452136B2 (en) Data synchronized playback device and terminal device
JP2004350292A (en) Apparatus and method for transmitting asynchronous transmission stream of DVB-ASI digital broadcast receiver
WO2017082059A1 (en) Information processing device, information processing method, and program
JP2001230750A (en) Stream transmitting apparatus and its receiving apparatus, and fundamental frequency synchronization method
US20050282580A1 (en) Video and audio synchronization
US20070248170A1 (en) Transmitting Apparatus, Receiving Apparatus, and Reproducing Apparatus
US20060166627A1 (en) Staged locking of two phase locked loops
US7436919B2 (en) Methods and apparatus for bit synchronizing data transferred across a multi-pin asynchronous serial interface
JP2004350102A (en) Radio transmission system
WO2021002135A1 (en) Data transmission device, data transmission system, and data transmission method
JP2007215092A (en) Audio data processing apparatus
WO2014064781A1 (en) Digital broadcast receiving apparatus and digital broadcast receiving method
US20100058096A1 (en) Signal processing apparatus and method thereof
KR100527427B1 (en) Moving Image Reproduction Device with High Power and Sound Quality, and The Reproduction Method

Legal Events

Date Code Title Description
AS Assignment

Owner name: BENQ CORPORATION, TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHIN, YI-LON;LEE, CHANG-HUNG;REEL/FRAME:017637/0938

Effective date: 20051004

AS Assignment

Owner name: QISDA CORPORATION, TAIWAN

Free format text: CHANGE OF NAME;ASSIGNOR:BENQ CORPORATION;REEL/FRAME:023288/0176

Effective date: 20070831

CC Certificate of correction
FPAY Fee payment

Year of fee payment: 4

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees

Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.)

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Expired due to failure to pay maintenance fee

Effective date: 20171201