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US7179759B2 - Barrier layer and fabrication method thereof - Google Patents

Barrier layer and fabrication method thereof Download PDF

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Publication number
US7179759B2
US7179759B2 US10/955,519 US95551904A US7179759B2 US 7179759 B2 US7179759 B2 US 7179759B2 US 95551904 A US95551904 A US 95551904A US 7179759 B2 US7179759 B2 US 7179759B2
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Prior art keywords
barrier layer
forming
watts
sccm
barrier
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US20060068604A1 (en
Inventor
Cheng-Lin Huang
Ching-Hua Hsieh
Shau-Lin Shue
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. reassignment TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HSIEH, CHING-HUA, HUANG, CHENG-LIN, SHUE, SHAU-LIN
Priority to CNA2005100029833A priority patent/CN1755914A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a film layer and a method for semiconductor devices; more particularly, to a barrier layer and a fabrication method thereof.
  • CMOS Complementary Metal Oxide Semiconductor
  • IC integrated circuits
  • a barrier layer usually is formed in a via or contact hole before deposition of a metal layer.
  • the conformity of the barrier layer affects the subsequent deposition of the metal layer.
  • a non-conformal barrier layer results in an overhead issue at the top of the via or contact hole.
  • the overheads may cause a pin hole in the via or contact hole so that the metal layer cannot fill therein.
  • the overhead issue becomes worse when the scale of the contact or via hole shrinks. Accordingly, the formation of a conformal barrier layer in a miniaturized via or contact hole is critical in semiconductor manufacturing.
  • U.S. Pat. No. 6,402,907 shows a method of forming a barrier layer in a high aspect ratio recess in a dielectric layer on a semiconductor wafer.
  • the method includes two main steps: (a) sputtering, at a pressure of 1 mTorr or less, a titanium layer onto an exposed surface of the recesses with the dielectric layer at a first distance from a sputter source or target; and (b) sputtering at a pressure in the range 1 millitorr to 0.5 millitorr a stochiometric titanium nitride layer onto the titanium layer with the dielectric at a second shorter distance from the sputter source or target.
  • U.S. Patent Publication No. 2003/0042133 shows a method for forming a barrier layer in a via or contact hole. The method first applies a first pressure in the chamber during an increase in pressure which is different from a second pressure in the chamber during a decrease in pressure, while an equal amount of the nitrogen gas is provided into the sputter chamber. Accelerated particles collide with the target to sputter the metal material from the target.
  • a method for forming a barrier layer comprises applying a working pressure for forming the barrier layer from about 0.5 mTorr to about 200 mTorr without substantially forming crystalline material therein.
  • a barrier layer is also disclosed.
  • the barrier layer is formed by the method described above.
  • the barrier layer comprises a compound made from barrier material selected from a group consisting Ta, W, Ti, Ru, Zr, Hf, V, Nb, Cr and Mo and at least one reaction gas containing at least one component of oxygen, nitrogen or carbon; a flow rate of the reaction gas from about 5 standard cubic centimeters per minute (sccm) to about 200 sccm; an argon gas with a flow rate from about 5 sccm to about 200 sccm; a target DC power from about 10,000 Watts to about 90,000 Watts; and a wafer bias power from about 100 Watts to about 1,500 Watts.
  • a ratio of the component to the barrier material not less than about 0.45.
  • the barrier layer comprises a N/Ta ratio from about 0.45 to about 1.00.
  • FIG. 1 is a drawing showing relationships between pressure and mean free path of different reaction gases.
  • FIGS. 2A and 2B are schematic cross sectional drawings showing exemplary barrier layers depositing in a via hole and in a via hole/trench structure, respectively.
  • FIGS. 3A–3B and 3 C– 3 D are Transmission Electronic Microscope (TEM) pictures and diffraction patterns of barrier layers formed by a prior art method and an exemplary method, respectively.
  • TEM Transmission Electronic Microscope
  • FIG. 1 is a drawing showing relationships between pressure and mean free path for different reaction gases.
  • the drawing shows linear relationships between the pressure and the mean free path of different reaction gases.
  • the relationships can be shown by the equation (1) as follows:
  • L represents mean free path
  • ⁇ represents the molecular diameter of the background gas atoms
  • n represents number density (atoms/cm 3 ) of the background gas
  • T represents temperature
  • P represents pressure
  • FIGS. 2A and 2B are schematic cross sectional drawings showing exemplary barrier layers depositing in a via hole and in a via hole/trench structure, respectively.
  • a metal layer 210 a is formed on a substrate 200 a .
  • a dielectric layer 220 a is formed over the substrate, covering the metal layer 210 a .
  • a via hole 240 a is formed within the dielectric layer 220 a , exposing a portion of a surface of the metal layer 210 a.
  • the substrate 200 a can be, for example, a silicon substrate, a III–V compound substrate, a glass substrate, or any other substrate similar thereto.
  • the metal layer 210 a can be, for example, aluminum, aluminum copper or copper.
  • the metal layer 210 a can be formed by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), electroplating or electroless plating or a combination thereof.
  • the material of the dielectric layer 220 a includes, for example, undoped silicate glass (USG), boron doped silicate glass (BSG), phosphorous doped silicate glass (PSG), boron phosphorous doped silicate glass (BPSG), polyimides, benzocyclobutene, parylenes, diamond-like carbon, poly(arylene ethers), cyclotenes, fluorocarbons, methyl silsesquioxane, hydrogen silsesquioxanes, nanoporous oxides or carbon doped silicon dioxides.
  • the dielectric layer 220 a can be formed by, for example, CVD, PVD, or spin coating.
  • the via hole 240 a can be formed by a photolithographic process and an etch process.
  • a metal layer 210 b is formed on a substrate 200 b .
  • a dielectric layer 220 b is formed over the substrate, covering the metal layer 210 b .
  • a via hole/trench 240 b is formed within the dielectric layer 220 b , exposing a portion of a surface of the metal layer 210 b.
  • the substrate 200 b , the metal layer 210 b and the dielectric layer 220 b of FIG. 2B are similar to the substrate 200 a , the metal layer 210 a and the dielectric layer 220 a of FIG. 2A , respectively. Detailed descriptions are not repeated.
  • the via hole/trench 240 b can be formed by, for example, a via-first or a trench-first dual damascene process.
  • the method of forming the via hole/trench 240 b comprises photolithographic and etch processes.
  • the method of forming either the via-first dual damascene or a trench-first dual damascene is known in the semiconductor industry.
  • Barrier layers 230 a and 230 b are formed in the via hole 240 a and the via hole/trench 240 b , respectively.
  • the barrier layers 230 a and 230 b are substantially conformal over the via hole 240 a and the via hole/trench 240 b , respectively.
  • the barrier layers 230 a and 230 b are formed under a high working pressure.
  • the working pressure may be from about 0.5 mTorr to about 200 mTorr.
  • the barrier layers 230 a and 230 b can be a compound made from barrier material selected from a group consisting Ta, W, Ti, Ru, Zr, Hf, V, Nb, Cr and Mo and at least one reaction gas containing at least one component of oxygen, nitrogen or carbon.
  • the reaction gas can be, for example, nitrogen.
  • the barrier layers 230 a and 230 b can be, for example, TaN, TaO, TaON, WN, TiN or any compound thereof.
  • a ratio of the component to the barrier material is not less than about 0.45.
  • a flow rate of the reaction gas is from about 5 standard cubic centimeters per minute (sccm) to about 200 sccm.
  • a target direct current (DC) power is from about 10,000 Watts to about 90,000 Watts;
  • a wafer bias power is from about 100 Watts to about 1,500 Watts.
  • the barrier layers 230 a and 230 b are a TaN layer.
  • the barrier layers 230 a and 230 b have a N/Ta ratio from about 0.45 to about 1.00.
  • the flow rate of the reaction gas containing the nitrogen component, such as N 2 is from about 0.5 mTorr to about 200 mTorr.
  • a flow rate of argon (Ar) is from about 5 sccm to about 200 sccm.
  • a target DC power is from about 10,000 Watts to about 90,000 Watts, and a wafer bias power is from about 100 Watts to about 1,500 Watts.
  • a wafer temperature is from about 25° C. to about 200° C.
  • the barrier layers 230 a and 230 b can be substantially conformal over the via hole 240 a and the via hole/trench 240 b , respectively.
  • the crystal properties of the barrier layers 230 a and 230 b can be identified by a technique that generates a diffraction pattern.
  • the technique includes, for example, X-ray diffraction or narrow beam diffraction.
  • FIGS. 3A–3B and 3 C– 3 D are Transmission Electronic Microscope (TEM) pictures and diffraction patterns of barrier layers formed by a prior art method and an exemplary method, respectively.
  • TEM Transmission Electronic Microscope
  • the C area shown in the TEM picture represents a Ta layer; the D area represents a TaN layer which is formed by a prior art low-pressure method.
  • the diffraction pattern at the D area is shown in FIG. 3B .
  • the narrow beam diffraction pattern shows fuzzy rings and dimming spots around the center of the diffraction pattern. These fuzzy rings and dimming spots show the existence of nano-crystalline in the TaN layer.
  • the C area shown in the TEM picture represents a Ta layer; the D area represents a TaN layer which is formed by the method of this embodiment.
  • the diffraction pattern at the D area is shown in FIG. 3D .
  • the narrow beam diffraction pattern shows no diffraction ring and diffraction spot.
  • the barrier layer comprises more ⁇ -Ta (B.C.C. structure). With more ⁇ -Ta phase, the structure of the barrier layer tends to be amorphous (nano-crystalline) within the TaN layer. Accordingly, the TaN layer formed by this exemplary method substantially does not comprise a long-term order crystalline microstructure.
  • the barrier layer formed by the exemplary methods is substantially conformal over the via or contact hole. Accordingly, the subsequent metal deposition process completely fills the metal layer in the via or contact hole without forming pin hole therein.

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Abstract

A barrier layer and a fabrication thereof are disclosed. The barrier layer comprises at least one barrier material selected from the group consisting of Ta, W, Ti, Ru, Zr, Hf, V, Nb, Cr and Mo and at least one component of oxygen, nitrogen or carbon. A ratio of the component to the barrier material is not less than about 0.45. The fabrication method of the barrier layer applies a working pressure for forming the barrier layer from about 0.5 mTorr to about 200 mTorr substantially without forming crystalline material therein.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a film layer and a method for semiconductor devices; more particularly, to a barrier layer and a fabrication method thereof.
2. Description of the Related Art
Complementary Metal Oxide Semiconductor (CMOS) technology has been frequently applied in manufacturing integrated circuits (IC). With the advance of CMOS technology, the miniaturization of CMOS devices according to a scaling rule is used in a semiconductor device to achieve large-scale integration and high-speed operation. In addition to the miniaturization of the scale of the CMOS devices, multiple-level interconnect technology is also applied to increase the high density of integration.
In multiple-level interconnect technology, a barrier layer usually is formed in a via or contact hole before deposition of a metal layer. The conformity of the barrier layer affects the subsequent deposition of the metal layer. In a worse case, a non-conformal barrier layer results in an overhead issue at the top of the via or contact hole. The overheads may cause a pin hole in the via or contact hole so that the metal layer cannot fill therein. The overhead issue becomes worse when the scale of the contact or via hole shrinks. Accordingly, the formation of a conformal barrier layer in a miniaturized via or contact hole is critical in semiconductor manufacturing.
U.S. Pat. No. 6,402,907 shows a method of forming a barrier layer in a high aspect ratio recess in a dielectric layer on a semiconductor wafer. The method includes two main steps: (a) sputtering, at a pressure of 1 mTorr or less, a titanium layer onto an exposed surface of the recesses with the dielectric layer at a first distance from a sputter source or target; and (b) sputtering at a pressure in the range 1 millitorr to 0.5 millitorr a stochiometric titanium nitride layer onto the titanium layer with the dielectric at a second shorter distance from the sputter source or target.
U.S. Patent Publication No. 2003/0042133 shows a method for forming a barrier layer in a via or contact hole. The method first applies a first pressure in the chamber during an increase in pressure which is different from a second pressure in the chamber during a decrease in pressure, while an equal amount of the nitrogen gas is provided into the sputter chamber. Accelerated particles collide with the target to sputter the metal material from the target.
SUMMARY OF THE INVENTION
A method for forming a barrier layer is provided. The method comprises applying a working pressure for forming the barrier layer from about 0.5 mTorr to about 200 mTorr without substantially forming crystalline material therein.
A barrier layer is also disclosed. The barrier layer is formed by the method described above.
The barrier layer comprises a compound made from barrier material selected from a group consisting Ta, W, Ti, Ru, Zr, Hf, V, Nb, Cr and Mo and at least one reaction gas containing at least one component of oxygen, nitrogen or carbon; a flow rate of the reaction gas from about 5 standard cubic centimeters per minute (sccm) to about 200 sccm; an argon gas with a flow rate from about 5 sccm to about 200 sccm; a target DC power from about 10,000 Watts to about 90,000 Watts; and a wafer bias power from about 100 Watts to about 1,500 Watts. A ratio of the component to the barrier material not less than about 0.45.
In a particularly preferred embodiment, the barrier layer comprises a N/Ta ratio from about 0.45 to about 1.00.
The above and other features of the present invention will be better understood from the following detailed description of the preferred embodiments of the invention that is provided in connection with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a drawing showing relationships between pressure and mean free path of different reaction gases.
FIGS. 2A and 2B are schematic cross sectional drawings showing exemplary barrier layers depositing in a via hole and in a via hole/trench structure, respectively.
FIGS. 3A–3B and 3C–3D are Transmission Electronic Microscope (TEM) pictures and diffraction patterns of barrier layers formed by a prior art method and an exemplary method, respectively.
 DESCRIPTION OF THE PREFERRED EMBODIMENT
FIG. 1 is a drawing showing relationships between pressure and mean free path for different reaction gases.
Referring to FIG. 1, the drawing shows linear relationships between the pressure and the mean free path of different reaction gases. The relationships can be shown by the equation (1) as follows:
L = 1 2 ⁢ ( πδ 2 ) = 0.707 δ ⁢ ⁢ n ≈ 2.331 × 10 - 20 ⁢ T P ⁢ ⁢ δ 2 ( 1 )
wherein L represents mean free path; δ represents the molecular diameter of the background gas atoms; n represents number density (atoms/cm3) of the background gas; T represents temperature; and P represents pressure.
From equation (1), the higher the pressure, the shorter the mean free path of atoms. Atoms sputtered by Physical Vapor deposition (PVD) with a reaction gas such as nitrogen or argon are disposed on the via or contact hole structure. With kinetic energy, the atoms move along the via or contact hole profile. The atoms on the sidewalls of the via or contact hole profile tend to move out from the sidewall areas. Under a low pressure, the mean free path of atoms increases and the moving of the atoms out of the sidewalls of the via or contact hole becomes more serious. The moving of the atoms results in a non-conformal barrier layer over the via or contact hole profile. This phenomenon, however, can be suppressed by increasing the working pressure.
FIGS. 2A and 2B are schematic cross sectional drawings showing exemplary barrier layers depositing in a via hole and in a via hole/trench structure, respectively.
Referring to FIG. 2A, a metal layer 210 a is formed on a substrate 200 a. A dielectric layer 220 a is formed over the substrate, covering the metal layer 210 a. A via hole 240 a is formed within the dielectric layer 220 a, exposing a portion of a surface of the metal layer 210 a.
The substrate 200 a can be, for example, a silicon substrate, a III–V compound substrate, a glass substrate, or any other substrate similar thereto. The metal layer 210 a can be, for example, aluminum, aluminum copper or copper. The metal layer 210 a can be formed by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), electroplating or electroless plating or a combination thereof. The material of the dielectric layer 220 a includes, for example, undoped silicate glass (USG), boron doped silicate glass (BSG), phosphorous doped silicate glass (PSG), boron phosphorous doped silicate glass (BPSG), polyimides, benzocyclobutene, parylenes, diamond-like carbon, poly(arylene ethers), cyclotenes, fluorocarbons, methyl silsesquioxane, hydrogen silsesquioxanes, nanoporous oxides or carbon doped silicon dioxides. The dielectric layer 220 a can be formed by, for example, CVD, PVD, or spin coating. The via hole 240 a can be formed by a photolithographic process and an etch process.
Referring to FIG. 2B, a metal layer 210 b is formed on a substrate 200 b. A dielectric layer 220 b is formed over the substrate, covering the metal layer 210 b. A via hole/trench 240 b is formed within the dielectric layer 220 b, exposing a portion of a surface of the metal layer 210 b.
The substrate 200 b, the metal layer 210 b and the dielectric layer 220 b of FIG. 2B are similar to the substrate 200 a, the metal layer 210 a and the dielectric layer 220 a of FIG. 2A, respectively. Detailed descriptions are not repeated. The via hole/trench 240 b can be formed by, for example, a via-first or a trench-first dual damascene process. The method of forming the via hole/trench 240 b comprises photolithographic and etch processes. The method of forming either the via-first dual damascene or a trench-first dual damascene is known in the semiconductor industry.
Barrier layers 230 a and 230 b are formed in the via hole 240 a and the via hole/trench 240 b, respectively. The barrier layers 230 a and 230 b are substantially conformal over the via hole 240 a and the via hole/trench 240 b, respectively. The barrier layers 230 a and 230 b are formed under a high working pressure. For example, the working pressure may be from about 0.5 mTorr to about 200 mTorr. The barrier layers 230 a and 230 b can be a compound made from barrier material selected from a group consisting Ta, W, Ti, Ru, Zr, Hf, V, Nb, Cr and Mo and at least one reaction gas containing at least one component of oxygen, nitrogen or carbon. The reaction gas can be, for example, nitrogen. Accordingly, the barrier layers 230 a and 230 b can be, for example, TaN, TaO, TaON, WN, TiN or any compound thereof. For the barrier layers 230 a and 230 b, a ratio of the component to the barrier material is not less than about 0.45.
A flow rate of the reaction gas is from about 5 standard cubic centimeters per minute (sccm) to about 200 sccm. In addition, a target direct current (DC) power is from about 10,000 Watts to about 90,000 Watts; a wafer bias power is from about 100 Watts to about 1,500 Watts.
In this embodiment, the barrier layers 230 a and 230 b are a TaN layer. The barrier layers 230 a and 230 b have a N/Ta ratio from about 0.45 to about 1.00. The flow rate of the reaction gas containing the nitrogen component, such as N2, is from about 0.5 mTorr to about 200 mTorr. A flow rate of argon (Ar) is from about 5 sccm to about 200 sccm. A target DC power is from about 10,000 Watts to about 90,000 Watts, and a wafer bias power is from about 100 Watts to about 1,500 Watts. A wafer temperature is from about 25° C. to about 200° C.
Due to the high working pressure deposition, the barrier layers 230 a and 230 b can be substantially conformal over the via hole 240 a and the via hole/trench 240 b, respectively.
The crystal properties of the barrier layers 230 a and 230 b can be identified by a technique that generates a diffraction pattern. The technique includes, for example, X-ray diffraction or narrow beam diffraction.
FIGS. 3A–3B and 3C–3D are Transmission Electronic Microscope (TEM) pictures and diffraction patterns of barrier layers formed by a prior art method and an exemplary method, respectively.
Referring to FIG. 3A, the C area shown in the TEM picture represents a Ta layer; the D area represents a TaN layer which is formed by a prior art low-pressure method. The diffraction pattern at the D area is shown in FIG. 3B. Referring to FIG. 3B, the narrow beam diffraction pattern shows fuzzy rings and dimming spots around the center of the diffraction pattern. These fuzzy rings and dimming spots show the existence of nano-crystalline in the TaN layer.
Referring to FIG. 3C, the C area shown in the TEM picture represents a Ta layer; the D area represents a TaN layer which is formed by the method of this embodiment. The diffraction pattern at the D area is shown in FIG. 3D. Referring to FIG. 3D, the narrow beam diffraction pattern shows no diffraction ring and diffraction spot. On the basis of the narrow beam diffraction pattern, the barrier layer comprises more α-Ta (B.C.C. structure). With more α-Ta phase, the structure of the barrier layer tends to be amorphous (nano-crystalline) within the TaN layer. Accordingly, the TaN layer formed by this exemplary method substantially does not comprise a long-term order crystalline microstructure.
Under a high working pressure, the barrier layer formed by the exemplary methods is substantially conformal over the via or contact hole. Accordingly, the subsequent metal deposition process completely fills the metal layer in the via or contact hole without forming pin hole therein.
Although the present invention has been described in terms of exemplary embodiments, it is not limited thereto. Rather, the appended claims should be constructed broadly to include other variants and embodiments of the invention which may be made by those skilled in the field of this art without departing from the scope and range of equivalents of the invention.

Claims (23)

1. A method for forming a barrier layer, comprising:
applying a working pressure from about 0.5 mTorr to about 200 mTorr;
applying a target DC power from about 10,000 Watts to about 90,000 Watts;
applying a wafer bias power from about 100 Watts to about 1,500 Watts; and
forming the barrier layer without substantially forming crystalline material therein.
2. The method for forming a barrier layer of claim 1, wherein a ratio of the component of the reaction gas to the barrier material is not less than about 0.45.
3. The method for forming a barrier layer of claim 1, wherein the barrier layer is substantially conformally formed in a via or contact hole.
4. The method for forming a barrier layer of claim 1, wherein the barrier layer is a compound made from barrier material selected from the group consisting of Ta, W, Ti, Ru, Zr, Hf, V, Nb, Cr and Mo and at least one reaction gas containing at least one component of oxygen, nitrogen or carbon.
5. The method for forming a barrier layer of claim 4, wherein a flow rate of the reaction gas is from about 0.5 standard cubic centimeters per minute (sccm) to about 200 sccm.
6. The method for forming a barrier layer of claim 5, wherein the reaction gas is nitrogen.
7. The method for forming a barrier layer of claim 6, further comprising an argon gas with a flow rate from about 0.5 sccm to about 200 sccm.
8. A barrier layer formed by the method of claim 1.
9. The barrier layer of claim 8, wherein the barrier layer comprises at least one barrier material of Ta, W, Ti, Ru, Zr, Hf, V, Nb, Cr or Mo and at least one component of oxygen, nitrogen or carbon, a ratio of the component to the barrier material not less than about 0.45.
10. The barrier layer of claim 9, wherein the barrier layer substantially does not comprise a long-term order crystalline microstructure.
11. The barrier layer of claim 10, wherein the crystalline material is adapted to be identified by a technique that generates a diffraction pattern.
12. The barrier layer of claim 11, wherein the technique includes X-ray diffraction or narrow beam diffraction.
13. A method for forming a barrier layer, comprising:
applying a working pressure from about 0.5 mTorr to about 200 mTorr; and
forming the barrier layer without substantially forming crystalline material therein,
wherein the component is nitrogen and the barrier material is Ta, and an N/Ta ratio is from about 0.45 to about 1.00.
14. The method for forming a barrier layer of claim 8, wherein a target DC power is from about 10,000 Watts to about 90,000 Watts, and a wafer bias power is from about 100 Watts to about 1,500 Watts.
15. The method for forming a barrier layer of claim 13, wherein a flow rate of the reaction gas containing the nitrogen component is from about 5 sccm to about 200 sccm.
16. The method for forming a barrier layer of claim 15, wherein the reaction gas is nitrogen.
17. The method for forming a barrier layer of claim 16, further comprising an argon gas with a flow rate from about 5 sccm to about 200 sccm.
18. A barrier layer formed by the method of claim 13.
19. The barrier layer of claim 18, wherein the barrier layer substantially does not comprise a β-Ta phase.
20. The barrier layer of claim 18, wherein the barrier layer comprises an α-Ta phase.
21. The barrier layer of claim 18, wherein the crystalline material is adapted to be identified by a technique that generates a diffraction pattern.
22. The barrier layer of claim 21, wherein the technique includes X-ray diffraction or narrow beam diffraction.
23. A method for forming a barrier layer, comprising a working pressure for forming the barrier layer from about 0.5 mTorr to about 200 mTorr; the barrier layer comprising a compound made from barrier material selected from the group consisting of Ta, W, Ti, Ru, Zr, Hf, V, Nb, Cr arid Mo and at least one reaction gas containing at least one component of oxygen, nitrogen or carbon; a flow rate of the reaction gas from about 5 standard cubic centimeters per minute (sccm) to about 200 sccm; an argon gas with a flow rate from about 5 sccm to about 200 sccm; a target DC power from about 10,000 Watts to about 90,000 Watts; and a wafer bias power from about 100 Watts to about 1,500 Watts.
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