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US7022625B2 - Method of fabricating a gate dielectric layer with reduced gate tunnelling current and reduced boron penetration - Google Patents

Method of fabricating a gate dielectric layer with reduced gate tunnelling current and reduced boron penetration Download PDF

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US7022625B2
US7022625B2 US10/205,517 US20551702A US7022625B2 US 7022625 B2 US7022625 B2 US 7022625B2 US 20551702 A US20551702 A US 20551702A US 7022625 B2 US7022625 B2 US 7022625B2
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silicon nitride
layer
dielectric layer
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US20040018674A1 (en
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Chew Hoe Ang
Alan Lek
Wenhe Lin
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GlobalFoundries Singapore Pte Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0177—Manufacturing their gate conductors the gate conductors having different materials or different implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer

Definitions

  • the present invention relates to methods used to fabricate semiconductor devices and more specifically to a method used to fabricate a gate dielectric layer offering reduced tunnelling current and improved boron penetration characteristics.
  • NMOS N channel metal oxide semiconductor
  • PMOS P channel
  • CMOS complimentary metal oxide semiconductor
  • the use of thin gate insulator layers have however presenting yield problems not encountered for counterpart devices comprised with thicker gate insulator layers.
  • thinner gate insulator layers such as silicon dioxide insulator layers do not offer as much protection as thicker counterparts against boron penetration from overlying P type doped polysilicon gate structures, resulting in a degraded gate insulator layer as well as a dopant depleted gate structure.
  • thinner gate insulator layers again such as silicon dioxide, present a greater risk of high gate tunnelling currents, than tunnelling risks encountered with thicker gate insulator counterparts.
  • This invention will describe a method of forming a gate dielectric layer featuring characteristics wherein reduced boron penetration from an overlying polysilicon gate structure, as well as reduced tunnelling current, are realized.
  • the gate dielectric layer offering the reduced boron penetration and reduced tunnelling current is a silicon nitride-silicon dioxide composite insulator layer, formed via a novel process sequence that allows the desired scaled down thickness to be realized.
  • Prior art such as Chhagan et al, in U.S. Pat. No. 6,277,716 B1, Chau et al, in U.S. Pat. No. 5,908,313, Taft et al, in U.S. Pat. No. 5,441,914, and Hurley, in U.S. Pat. No.
  • 6,350,708 B1 describe methods of forming silicon nitride layers for various applications including use a gate insulator layer.
  • none of the prior art describe the novel process sequence of this present invention, in which a scaled down, silicon nitride-silicon dioxide composite layer is formed.
  • CMOS complimentary metal oxide semiconductor
  • a method of fabricating a silicon nitride-silicon dioxide gate dielectric layer via a process sequence in which the composite gate dielectric layer is formed with reduced risk of boron penetration from overlying gate structures, as well as reduced tunnelling current is described.
  • a porous silicon rich silicon nitride layer is deposited on a semiconductor substrate, followed by a thermal oxidation procedure resulting in a thin silicon dioxide layer formed underlying the porous silicon rich silicon nitride layer.
  • An anneal procedure, performed in a nitrogen containing ambient, is next performed for densification of the porous silicon rich silicon nitride layer, as well as to remove the fixed charge located at the silicon dioxide-semiconductor substrate interface.
  • Conductive gate structures, including P type doped, polysilicon gate structures are next formed on the composite dielectric layer comprised of densified silicon nitride on an underlying silicon dioxide layer.
  • FIGS. 1–4 which schematically in cross-sectional style describe key stages used for fabrication of a silicon nitride-silicon dioxide gate dielectric layer, wherein a novel process sequence was employed to form the gate dielectric layer with reduced tunnelling current, and reduced risk of boron penetration from an overlying boron doped polysilicon gate structure.
  • Semiconductor substrate 1 comprised of P type single crystalline silicon, featuring a ⁇ 100>crystallographic orientation, is used and schematically shown in FIG. 1 .
  • Porous, or low density silicon nitride layer 2 a a silicon rich silicon nitride layer, is next deposited on semiconductor substrate 1 , at a thickness between about 10 to 30 Angstroms, via low pressure chemical vapor deposition (LPCVD), or via plasma enhanced chemical vapor deposition (PECVD), procedures.
  • LPCVD low pressure chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • the objective is to form a porous, or low density silicon nitride layer which will allow a subsequent thermal oxidation procedure to form a thin silicon dioxide layer on the semiconductor surface, via diffusion of oxygen through the porous regions of the silicon nitride layer, thus specific silicon nitride deposition conditions are needed. Therefore porous, silicon rich silicon nitride layer 2 a , schematically shown in FIG.
  • a thermal oxidation procedure performed at a temperature between about 900 to 1050° C., is next performed in an oxygen ambient, resulting in the growth of silicon dioxide layer 3 , on semiconductor substrate 1 , underlying porous silicon nitride layer 2 a .
  • This is schematically shown in FIG. 2 .
  • the porosity of silicon nitride layer 2 a allowed oxygen to reach the surface of semiconductor substrate 1 , resulting in the growth of silicon dioxide layer 3 , at a thickness between about 2 to 10 Angstroms.
  • An anneal procedure is next performed to densify porous silicon nitride layer 2 a , as well as to remove fixed oxide charges located at the silicon dioxide-semiconductor interface.
  • a first cycle of the anneal procedure is performed at a temperature between about 800 to 1100° C., in an NH 3 —NO ambient, for between about 30 to 150 sec.
  • the first anneal cycle densifies porous silicon nitride layer 2 a , resulting in a densified or less permeable, silicon nitride layer 2 b .
  • Silicon nitride layer 2 b now is stoichiometrically comprised as Si 3 N 4 .
  • a second cycle of the anneal procedure is performed at a temperature between about 1000 to 1100° C., in an inert ambient such as nitrogen or argon, allowing the fixed positive charge located at the silicon dioxide-semiconductor substrate interface, occurring as a result of the previously performed thermal oxidation procedure, to be reduced.
  • a gate dielectric layer comprised of densified silicon nitride layer 2 b , overlying silicon dioxide layer 3 , shown schematically in FIG. 3 , has been formed via the above process sequence, featuring deposition of a porous silicon nitride layer, formation of a silicon dioxide layer on the semiconductor surface, overlying the porous silicon nitride layer, and densification of the porous silicon nitride layer.
  • gate structure 4 on the underlying gate dielectric layer is next addressed and schematically described using FIG. 4 .
  • a polysilicon layer, doped with boron is deposited via LPCVD procedures at a thickness between about 500 to 3000 Angstroms.
  • the polysilicon layer will be doped with boron for attainment of a specific work function and thus a specific threshold voltage.
  • the polysilicon layer can be doped N type.
  • a photoresist shape is used as an etch mask allowing an anisotropic reactive ion etching (RIE), procedure to define gate structure 4 .
  • RIE anisotropic reactive ion etching
  • the RIE procedure is performed using Cl 2 as an etchant for polysilicon, with an over etch cycle used to remove regions of silicon nitride layer 2 b , not covered by the photoresist shape or by gate structure 4 .
  • Removal of the photoresist shape is accomplished via plasma oxygen ashing and wet clean procedures.
  • the removal of regions of silicon dioxide layer 3 , not covered by gate structure 4 is accomplished during a buffered hydrofluoric acid cycle of the wet clean procedure.
  • Subsequent processing steps such as source/drain formation, performed at high temperatures, can result in boron penetration from the boron doped polysilicon gate structure, through thin silicon dioxide layer 3 , altering the dopant characteristics of the channel region, adversely influencing device parameters and performance.
  • the presence of densified silicon nitride layer 2 b prevented occurrence of this undesirable phenomena.

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Abstract

A method of forming a silicon nitride-silicon dioxide, composite gate dielectric layer, offering reduced risk of boron penetration from an overlying boron doped polysilicon gate structure, has been developed. A porous, silicon rich silicon nitride layer is first deposited on a semiconductor substrate, allowing a subsequent thermal oxidation procedure to grow a thin silicon dioxide layer on the semiconductor substrate, underlying the porous, silicon rich silicon nitride layer. A two step anneal procedure is then employed with a first step performed in a nitrogen containing ambient to densify the porous, silicon rich silicon nitride layer, while a second step of the anneal procedure, performed in an inert ambient at a high temperature, reduces the foxed charge at the silicon dioxide-semiconductor interface.

Description

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices and more specifically to a method used to fabricate a gate dielectric layer offering reduced tunnelling current and improved boron penetration characteristics.
(2) Description of Prior Art
Micro-miniaturization, or the ability to fabricate semiconductor devices with sub-micron features, has allowed the performance of sub-micron devices to be increased while the fabrication costs for these same devices have been reduced. The scaling down of semiconductor devices, such as N channel metal oxide semiconductor (NMOS), and P channel (PMOS), elements of complimentary metal oxide semiconductor (CMOS), has included the scaling down of the thickness of the gate insulator layer. The use of thin gate insulator layers have however presenting yield problems not encountered for counterpart devices comprised with thicker gate insulator layers. For example thinner gate insulator layers such as silicon dioxide insulator layers do not offer as much protection as thicker counterparts against boron penetration from overlying P type doped polysilicon gate structures, resulting in a degraded gate insulator layer as well as a dopant depleted gate structure. In addition the thinner gate insulator layers, again such as silicon dioxide, present a greater risk of high gate tunnelling currents, than tunnelling risks encountered with thicker gate insulator counterparts.
This invention will describe a method of forming a gate dielectric layer featuring characteristics wherein reduced boron penetration from an overlying polysilicon gate structure, as well as reduced tunnelling current, are realized. The gate dielectric layer offering the reduced boron penetration and reduced tunnelling current, is a silicon nitride-silicon dioxide composite insulator layer, formed via a novel process sequence that allows the desired scaled down thickness to be realized. Prior art such as Chhagan et al, in U.S. Pat. No. 6,277,716 B1, Chau et al, in U.S. Pat. No. 5,908,313, Taft et al, in U.S. Pat. No. 5,441,914, and Hurley, in U.S. Pat. No. 6,350,708 B1, describe methods of forming silicon nitride layers for various applications including use a gate insulator layer. However none of the prior art describe the novel process sequence of this present invention, in which a scaled down, silicon nitride-silicon dioxide composite layer is formed.
SUMMARY OF THE INVENTION
It is an object of this invention to fabricate a gate dielectric layer for complimentary metal oxide semiconductor (CMOS), applications, featuring resistance to boron penetration from an overlying boron doped, polysilicon gate structure, and offering a reduction in tunnelling current when compared to counterpart gate dielectric layers.
It is another object of this invention to fabricate a silicon nitride-silicon dioxide composite insulator layer for use as a gate dielectric layer.
It is still another object of this invention to form the silicon nitride-silicon dioxide gate dielectric layer via deposition of a porous silicon rich, silicon nitride layer, followed by an oxidation procedure creating an underlying silicon dioxide layer, and a subsequent ammonia treatment used to densify the porous silicon nitride layer.
In accordance with the present invention a method of fabricating a silicon nitride-silicon dioxide gate dielectric layer via a process sequence in which the composite gate dielectric layer is formed with reduced risk of boron penetration from overlying gate structures, as well as reduced tunnelling current, is described. A porous silicon rich silicon nitride layer is deposited on a semiconductor substrate, followed by a thermal oxidation procedure resulting in a thin silicon dioxide layer formed underlying the porous silicon rich silicon nitride layer. An anneal procedure, performed in a nitrogen containing ambient, is next performed for densification of the porous silicon rich silicon nitride layer, as well as to remove the fixed charge located at the silicon dioxide-semiconductor substrate interface. Conductive gate structures, including P type doped, polysilicon gate structures, are next formed on the composite dielectric layer comprised of densified silicon nitride on an underlying silicon dioxide layer.
BRIEF DESCRIPTION OF THE DRAWINGS
The object and other advantages of this invention are best described in the preferred embodiment with reference to the attached drawings that include:
FIGS. 1–4, which schematically in cross-sectional style describe key stages used for fabrication of a silicon nitride-silicon dioxide gate dielectric layer, wherein a novel process sequence was employed to form the gate dielectric layer with reduced tunnelling current, and reduced risk of boron penetration from an overlying boron doped polysilicon gate structure.
 DESCRIPTION OF THE PREFERRED EMBODIMENTS
The method of forming a silicon nitride-silicon dioxide gate dielectric layer via a process sequence allowing reduced gate tunnelling current to be realized, in addition to presenting a barrier to eliminate boron penetration from an overlying boron doped polysilicon gate structure, will now be described in detail. Semiconductor substrate 1, comprised of P type single crystalline silicon, featuring a <100>crystallographic orientation, is used and schematically shown in FIG. 1. Porous, or low density silicon nitride layer 2 a, a silicon rich silicon nitride layer, is next deposited on semiconductor substrate 1, at a thickness between about 10 to 30 Angstroms, via low pressure chemical vapor deposition (LPCVD), or via plasma enhanced chemical vapor deposition (PECVD), procedures. The objective is to form a porous, or low density silicon nitride layer which will allow a subsequent thermal oxidation procedure to form a thin silicon dioxide layer on the semiconductor surface, via diffusion of oxygen through the porous regions of the silicon nitride layer, thus specific silicon nitride deposition conditions are needed. Therefore porous, silicon rich silicon nitride layer 2 a, schematically shown in FIG. 1, is deposited at a temperature between about 750 to 900° C., at a pressure between about 30 to 50 torr, using between about 1 to 5 sccm of SiH4, and between about 300 to 600 sccm of nitrogen.
A thermal oxidation procedure, performed at a temperature between about 900 to 1050° C., is next performed in an oxygen ambient, resulting in the growth of silicon dioxide layer 3, on semiconductor substrate 1, underlying porous silicon nitride layer 2 a. This is schematically shown in FIG. 2. The porosity of silicon nitride layer 2 a, allowed oxygen to reach the surface of semiconductor substrate 1, resulting in the growth of silicon dioxide layer 3, at a thickness between about 2 to 10 Angstroms.
An anneal procedure is next performed to densify porous silicon nitride layer 2 a, as well as to remove fixed oxide charges located at the silicon dioxide-semiconductor interface. A first cycle of the anneal procedure is performed at a temperature between about 800 to 1100° C., in an NH3—NO ambient, for between about 30 to 150 sec. The first anneal cycle densifies porous silicon nitride layer 2 a, resulting in a densified or less permeable, silicon nitride layer 2 b. Silicon nitride layer 2 b, now is stoichiometrically comprised as Si3N4. A second cycle of the anneal procedure is performed at a temperature between about 1000 to 1100° C., in an inert ambient such as nitrogen or argon, allowing the fixed positive charge located at the silicon dioxide-semiconductor substrate interface, occurring as a result of the previously performed thermal oxidation procedure, to be reduced. Thus a gate dielectric layer comprised of densified silicon nitride layer 2 b, overlying silicon dioxide layer 3, shown schematically in FIG. 3, has been formed via the above process sequence, featuring deposition of a porous silicon nitride layer, formation of a silicon dioxide layer on the semiconductor surface, overlying the porous silicon nitride layer, and densification of the porous silicon nitride layer.
The formation of gate structure 4, on the underlying gate dielectric layer is next addressed and schematically described using FIG. 4. A polysilicon layer, doped with boron is deposited via LPCVD procedures at a thickness between about 500 to 3000 Angstroms. For purposes of this invention the polysilicon layer will be doped with boron for attainment of a specific work function and thus a specific threshold voltage. However if desired the polysilicon layer can be doped N type. A photoresist shape, not shown in the drawings, is used as an etch mask allowing an anisotropic reactive ion etching (RIE), procedure to define gate structure 4. The RIE procedure is performed using Cl2 as an etchant for polysilicon, with an over etch cycle used to remove regions of silicon nitride layer 2 b, not covered by the photoresist shape or by gate structure 4. Removal of the photoresist shape is accomplished via plasma oxygen ashing and wet clean procedures. The removal of regions of silicon dioxide layer 3, not covered by gate structure 4, is accomplished during a buffered hydrofluoric acid cycle of the wet clean procedure. Subsequent processing steps such as source/drain formation, performed at high temperatures, can result in boron penetration from the boron doped polysilicon gate structure, through thin silicon dioxide layer 3, altering the dopant characteristics of the channel region, adversely influencing device parameters and performance. The presence of densified silicon nitride layer 2 b, prevented occurrence of this undesirable phenomena.
While this invention has been particularly shown and described with reference to, the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of this invention.

Claims (13)

1. A method of forming a composite gate dielectric layer on a semiconductor substrate, comprising the steps of:
depositing a porous, silicon rich silicon nitride layer, at a thickness between about 10 to 30 Angstroms on said semiconductor substrate;
performing a thermal oxidation procedure to from a second dielectric layer on said semiconductor substrate, underlying said porous, silicon rich silicon nitride layer;
performing an anneal procedure resulting in said composite gate dielectric layer comprised of densified said porous, silicon rich silicon nitride layer overlying said second dielectric layer; and
forming a conductive gate structure on said composite gate dielectric layer.
2. The method of claim 1, wherein said porous, silicon rich silicon nitride layer is obtained via a low pressure chemical vapor deposition (LPCVD), or via a plasma enhanced chemical vapor deposition (PECVD), procedure, performed at a temperature between about 750 to 900° C.
3. The method of claim 1, wherein said porous, silicon rich silicon nitride layer is obtained via LPCVD or PECVD procedures using between about 1 to 5 sccm of SiH4, and using between about 300 to 600 sccm of nitrogen.
4. The method of claim 1, wherein said second dielectric layer is a silicon dioxide layer at a thickness between about 2 to 10 Angstroms.
5. The method of claim 4, wherein said silicon dioxide layer is obtained via a thermal oxidation procedure performed at a temperature between about 900 to 1050° C.
6. The method of claim 4, wherein said silicon dioxide layer is obtained via a thermal oxidation procedure performed in an oxygen ambient.
7. The method of claim 1, wherein a first cycle of said anneal procedure is performed at a temperature between about 800 to 1100° C.
8. The method of claim 1, wherein a first cycle of said anneal procedure is performed in an NH3—NO ambient.
9. The method of claim 1, wherein a first cycle of said anneal procedure is performed for a time between about 30 to 150 sec.
10. The method of claim 1, wherein a second cycle of said anneal procedure is performed at a temperature between about 1000 to 1100° C.
11. The method of claim 1, wherein a second cycle of said anneal procedure is performed in a nitrogen or argon ambient.
12. The method of claim 1, wherein said conductive gate structure is a boron doped, polysilicon gate structure.
13. The method of claim 1, wherein a second cycle of said anneal procedure, used to reduce fixed charge at a first dielectric layer-semiconductor substrate interface, is performed at a temperature between about 1000 to 1100° C., in a nitrogen or argon ambient.
US10/205,517 2002-07-25 2002-07-25 Method of fabricating a gate dielectric layer with reduced gate tunnelling current and reduced boron penetration Expired - Lifetime US7022625B2 (en)

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SG200303243A SG121776A1 (en) 2002-07-25 2003-05-19 A method of fabricating a gate dielectric layer with reduced gate tunnelling current and reduced boron penetration

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050045967A1 (en) * 2003-08-29 2005-03-03 Semiconductor Leading Edge Technologies, Inc. Method for manufacturing semiconductor device and semiconductor device
US20050236679A1 (en) * 2004-01-06 2005-10-27 Fujitsu Limited Semiconductor device, and method and apparatus for manufacturing the same

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007017312A (en) * 2005-07-08 2007-01-25 Hitachi Ltd Semiconductor gas sensor and manufacturing method thereof
US7601648B2 (en) * 2006-07-31 2009-10-13 Applied Materials, Inc. Method for fabricating an integrated gate dielectric layer for field effect transistors
US20160376700A1 (en) * 2013-02-01 2016-12-29 Asm Ip Holding B.V. System for treatment of deposition reactor
KR102832749B1 (en) 2016-09-23 2025-07-10 엘지디스플레이 주식회사 Flexible display device
CN114999907B (en) * 2022-08-08 2023-03-17 合肥新晶集成电路有限公司 Manufacturing method of grid oxide layer and manufacturing method of field effect transistor

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5441914A (en) 1994-05-02 1995-08-15 Motorola Inc. Method of forming conductive interconnect structure
US5464783A (en) * 1993-03-24 1995-11-07 At&T Corp. Oxynitride-dioxide composite gate dielectric process for MOS manufacture
US5908313A (en) 1996-12-31 1999-06-01 Intel Corporation Method of forming a transistor
US6027977A (en) 1997-05-14 2000-02-22 Nec Corporation Method of fabricating semiconductor device with MIS structure
US6114258A (en) 1998-10-19 2000-09-05 Applied Materials, Inc. Method of oxidizing a substrate in the presence of nitride and oxynitride films
US6277716B1 (en) 1999-10-25 2001-08-21 Chartered Semiconductor Manufacturing Ltd. Method of reduce gate oxide damage by using a multi-step etch process with a predictable premature endpoint system
US6350708B1 (en) 1996-05-30 2002-02-26 Micron Technology, Inc. Silicon nitride deposition method
US20040147136A1 (en) 2003-01-29 2004-07-29 Macronix International Co., Ltd. Method for making the gate dielectric layer by oxygen radicals and hydroxyl radicals mixture

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5464783A (en) * 1993-03-24 1995-11-07 At&T Corp. Oxynitride-dioxide composite gate dielectric process for MOS manufacture
US5441914A (en) 1994-05-02 1995-08-15 Motorola Inc. Method of forming conductive interconnect structure
US6350708B1 (en) 1996-05-30 2002-02-26 Micron Technology, Inc. Silicon nitride deposition method
US5908313A (en) 1996-12-31 1999-06-01 Intel Corporation Method of forming a transistor
US6027977A (en) 1997-05-14 2000-02-22 Nec Corporation Method of fabricating semiconductor device with MIS structure
US6114258A (en) 1998-10-19 2000-09-05 Applied Materials, Inc. Method of oxidizing a substrate in the presence of nitride and oxynitride films
US6277716B1 (en) 1999-10-25 2001-08-21 Chartered Semiconductor Manufacturing Ltd. Method of reduce gate oxide damage by using a multi-step etch process with a predictable premature endpoint system
US20040147136A1 (en) 2003-01-29 2004-07-29 Macronix International Co., Ltd. Method for making the gate dielectric layer by oxygen radicals and hydroxyl radicals mixture

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050045967A1 (en) * 2003-08-29 2005-03-03 Semiconductor Leading Edge Technologies, Inc. Method for manufacturing semiconductor device and semiconductor device
US7306985B2 (en) * 2003-08-29 2007-12-11 Seiko Epson Corporation Method for manufacturing semiconductor device including heat treating with a flash lamp
US20050236679A1 (en) * 2004-01-06 2005-10-27 Fujitsu Limited Semiconductor device, and method and apparatus for manufacturing the same
US7678711B2 (en) * 2004-01-06 2010-03-16 Fujitsu Microelectronics Limited Semiconductor device, and method and apparatus for manufacturing the same

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US20040018674A1 (en) 2004-01-29

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