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US6951801B2 - Metal reduction in wafer scribe area - Google Patents

Metal reduction in wafer scribe area Download PDF

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Publication number
US6951801B2
US6951801B2 US10/351,798 US35179803A US6951801B2 US 6951801 B2 US6951801 B2 US 6951801B2 US 35179803 A US35179803 A US 35179803A US 6951801 B2 US6951801 B2 US 6951801B2
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layer
metal
saw path
wafer
exposed metal
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US20040147097A1 (en
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Scott K. Pozder
Trent S. Uehling
Lakshmi N. Ramanathan
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NXP USA Inc
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Freescale Semiconductor Inc
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Priority to TW093100911A priority patent/TWI325155B/zh
Priority to PCT/US2004/001925 priority patent/WO2004073014A2/fr
Priority to JP2006502974A priority patent/JP2006516824A/ja
Priority to KR1020057013873A priority patent/KR101001530B1/ko
Priority to CN2004800029150A priority patent/CN1777978B/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3043—Making grooves, e.g. cutting

Definitions

  • This invention relates in general to the manufacture of semiconductor devices and in particular to the reduction of metal in a scribe area between semiconductor die areas of a wafer.
  • Copper is used in scribe area interconnect layers of a semiconductor wafer e.g. for test structures and alignment keys. During the singulation of the die areas of a wafer, the copper in the scribe area interconnect layer may build up on a saw blade. This copper build up on the saw blade causes cracking and chipping of the wafer. The cracks and chips may lead to a mechanical failure of the die during its application.
  • Multiple saw blades may be used for cutting a scribe area to reduce the damage to the substrate of the wafer from the copper buildup on a saw blade.
  • a first saw blade would be used to cut the interconnect layer. Copper build up from the interconnect layer would accumulate on the first saw blade.
  • a second saw blade would follow the same saw path to cut the under laying substrate. Because this second saw blade would not be cutting any copper, little if any copper would build up on this saw blade.
  • utilizing two saw blades may cause other problems due to saw misalignment.
  • ledges in the die edge may be created due to the copper build up on the first saw blade in that the saw blade with copper build up may be wider than the second saw blade.
  • Crack stop trenches located at the die edge may be used to prevent cracking of the die.
  • these trenches may require additional processes for patterning, etching of the pattern, removal of the mask, and etching.
  • cracks may propagate beneath the trench into the active area of the die.
  • trenches in the die may open the die to moisture. Accordingly, it is desirable to reduce the cause of cracking in wafer fabrication.
  • What is needed is an improved method for reducing the amount of copper or other metals in the saw path to prevent the accumulation of metal on a saw blade or other type of wafer cutting device so as to reduce cracking, chipping, or other damage to the wafer.
  • FIG. 1 is a partial cross sectional view of one embodiment of a semiconductor wafer at a stage during its manufacture according to the present invention.
  • FIG. 2 is a partial cross sectional view of one embodiment of a semiconductor wafer at another stage during its manufacture according to the present invention.
  • FIG. 3 is a partial cross sectional view of one embodiment of a semiconductor wafer at another stage during its manufacture according to the present invention.
  • FIG. 4 is a partial cross sectional view of one embodiment of a semiconductor wafer at another stage during its manufacture according to the present invention.
  • FIG. 5 is a partial cross sectional view of one embodiment of a semiconductor wafer at another stage during its manufacture according to the present invention.
  • FIG. 6 is a partial cross sectional view of one embodiment of a semiconductor wafer at another stage during its manufacture according to the present invention.
  • FIG. 7 is a partial cross sectional view of one embodiment of a semiconductor wafer at another stage during its manufacture according to the present invention.
  • FIG. 8 is a partial cross sectional view of one embodiment of a semiconductor wafer at another stage during its manufacture according to the present invention.
  • FIG. 9 is a partial cross sectional view of one embodiment of a semiconductor wafer at another stage during its manufacture according to the present invention.
  • FIG. 10 is a partial top view of one embodiment of semiconductor wafer according to the present invention.
  • FIG. 1 is a partial cross sectional view of one embodiment of a semiconductor wafer during its manufacture according to the present invention.
  • FIG. 1 shows a portion of a wafer 101 prior to the formation of solder balls (or the formation of other die-to-package external conductive connection structures in other embodiments).
  • Die area 105 of wafer 101 is a portion of wafer 101 from which a semiconductor die (not shown) is made.
  • Wafer 101 includes multiple die areas (not shown) separated by scribe areas (not shown).
  • FIG. 1 shows a portion of scribe area 103 located adjacent to die area 105 .
  • a second die area (not shown) is located to the left of scribe area 103 , relative to the view shown in FIG. 1 .
  • a die made from die area 105 is utilized in a flip chip configuration in a semiconductor package.
  • Wafer 101 includes an interconnect stack layer 107 located on top of substrate 109 .
  • stack layer 107 includes multiple layers of dielectric material and interconnecting electrical conductive structures such as vias and trace layers. These interconnecting electrically conductive structures are made of metal (e.g. copper, aluminum, silver, or gold) and electrically couple devices (not shown) formed in substrate 109 with external conductive connection structures such as e.g. solder balls.
  • the multiple layers of interconnect stack layer 107 are, in one embodiment, formed by a dual inlaid process, but may, in other embodiments, be formed by other processes such as e.g. a single inlaid process.
  • a saw blade or other cutting device is used to separate the die areas (e.g. 105 ) from each other during the later stages of manufacture (see FIG. 9 ).
  • a saw blade cuts the wafer at a saw path 111 .
  • Conductive structures 112 which are made of copper in one embodiment, are located in saw path 111 . These conductive structures are utilized for testing and alignment guides during manufacture but typically are not electrically coupled to the devices formed in the substrate 109 of die area 105 and are not utilized during the operation of a die in its end use.
  • the copper of these conductive structures 112 in the saw path 111 may build up on the saw blade thereby causing problems during singulation. As will be described later, portions of the metal in the saw path 111 are removed to reduce the metal buildup on a saw blade.
  • a passivation layer 121 is located on interconnect layer 107 .
  • Passivation layer 121 is made of a dielectric passivation material such as e.g. silicon nitride.
  • Passivation layer 121 is formed over the die areas e.g. 105 of wafer 101 and is utilize as a protective layer of the die area.
  • Passivation layer 121 includes openings for coupling external conductive connection structures (e.g. solder balls) to electrically conductive pads (e.g. 131 ) in interconnect stack layer 107 .
  • a polyimide layer 124 is formed over die area 105 and is utilized for stress relief and die protection. Polyimide layer 124 includes openings for coupling external conductive connection structures (e.g.
  • passivation layer 121 may be located over portions of the scribe area that do not include metals in the saw path that are to be removed.
  • An edge seal ring 119 and crack stop ring 117 extend around the perimeter of die area 105 . Theses structures are made of metal traces with trench vias located in between the traces. The contact vias 120 of the seal ring 119 and crack stop ring 117 may be may of a different material such as tungsten.
  • Conductive structures 113 and 115 are ring structures located on the edge of saw path 111 in stack layer 107 and surround die area 105 .
  • structures 113 and 115 are located 20 and 15 microns, respectively, from crack stop 117 .
  • conductive structures 113 and 115 are removed to form crack stop trenches in the scribe area.
  • FIG. 2 shows a partial cross sectional view of a portion of wafer 101 after the application of a barrier adhesion layer 203 and a electrical bus layer 205 on barrier adhesion layer 203 .
  • layer 203 is a layer of titanium tungsten (TiW) formed by a physical vapor deposition process and is 2700 Angstroms.
  • layer 203 may include nickel.
  • layer 203 may be a layer of titanium nitride (TiN), tantalum (Ta), nickel (N), or tungsten (W).
  • Layer 205 includes copper and is also applied, in one embodiment, over the entire wafer by a physical vapor deposition process.
  • layer 205 may be applied by other processes such as e.g. electroless plating or chemical vapor deposition. Layer 205 acts as an electrical bus for further electroplating for forming other structures such as copper stud 307 (see FIG. 3 ). In one embodiment, layer 205 is 5300 angstroms thick.
  • FIG. 3 shows a partial cross sectional view of a portion of wafer 101 after the formation of copper studs (e.g. 307 ) and solder caps (e.g. 309 ) for forming external conductive connection structures for externally coupling the devices of a die in substrate 109 .
  • a photo resist layer 303 is first patterned on layer 205 having openings exposing layer 205 at locations over the conductive pads (e.g. 131 ). Copper studs (e.g. 307 ) are then formed in the openings of the photo resist by electroplating. Afterwards, solder caps (e.g. 309 ) are also formed by electroplating.
  • FIG. 4 shows a partial cross sectional view of a portion of wafer 101 where photo resist 303 has been removed.
  • the surface of the wafer is then wet etched to selectively remove copper layer 205 .
  • the wet etch is performed using an ammonical enchant such as METEX FA and METEX FB sold by the MACDERMID CORPORATION of Connecticut.
  • METEX FA and METEX FB sold by the MACDERMID CORPORATION of Connecticut.
  • Also removed during this process are a portion of the side walls of the copper studs (e.g. 307 ).
  • the portion of the sidewalls removed has a width that is approximately the same as the thickness of layer 205 .
  • FIG. 5 shows a partial cross sectional view of a portion of wafer 101 after the removal of layer 205 .
  • the portion of layer 203 not under a stud ( 307 ) is then removed in a chemical bath e.g. using hydrogen peroxide.
  • the resulting structure is shown in FIG. 6 .
  • FIG. 6 shows a partial cross sectional view of wafer 101 after the removal of portions of layer 203 .
  • portions of stack layer 107 not located under passivation layer 121 and/or solder cap 309 are exposed.
  • wafer 101 is then wet etched to remove exposed copper in test structure 112 and in conductive structures 113 and 115 .
  • the resultant structure from this wet etch process is shown in FIG. 7 .
  • the exposed copper of test structure 112 , conductive structure 113 and conductive structure 115 in top interconnect layer 703 have been removed by the wet etch process to leave openings 708 , 713 , and 717 , respectively.
  • interconnect layer 107 was formed with a dual inlaid process, the copper in vias 711 , 715 , and 721 of layer 704 are also removed.
  • the copper of test structure 112 , conductive structure 113 , and conductive structure 115 in stack layer 705 are not removed in that there is a conductive barrier adhesion layer (not shown) located between the conductive structures (shown as removed in FIG. 7 ) of via stack layer 704 and the conductive structures (e.g. 720 ) in stack layer 705 .
  • the barrier adhesion layer includes at least one of titanium, tantalum, and tungsten.
  • the wet etch of the exposed metal in stack layers 703 and 704 also removes copper from the sidewalls of the copper studs (e.g. 307 ) and the copper layer 205 located underneath, exposing a portion of the top of layer 203 and a portion of the bottom of solder cap 309 . Furthermore, the ammonium ions of the wet etch used to remove the exposed metal in stack layers 703 and 704 may also remove complex trace amounts of lead located on exposed passivation layer 121 and polyimide layer 124 .
  • wafer 101 is subjected to another chemical bath using e.g. hydrogen peroxide to remove the barrier adhesion layer (not shown) on the conductive metal (e.g. 720 ) of stack layer 705 .
  • This bath also removes a portion of layer 203 that is exposed.
  • wafer 101 is subjected to another wet etch process to remove the exposed copper e.g. 720 in stack layers 705 and 706 .
  • FIG. 8 shows a partial cross sectional view of wafer 101 where all of the copper of conductive structures 113 and 115 have been removed to form crack stop trenches 807 and 809 , respectively.
  • the exposed copper in saw path 111 has been removed as well.
  • the copper in the lower stack layers in some embodiments, may not generate build up on the saw in that the amount of copper in the saw blade path at layer 703 is greater than at the lower levels because the metal traces are narrower at the lower levels and are a smaller fraction of the saw blade width.
  • the diameter of the copper stud (e.g. 307 ) as well as the exposed portions of layers 205 and 203 are reduced.
  • FIG. 9 shows a partial cross sectional side view of wafer 101 being cut with saw blade 903 along saw path 111 .
  • saw blade 903 is cutting both stack layer 107 and substrate 109 .
  • a single saw blade e.g. 903
  • alignment problems using multiple saw blades may be eliminated as well.
  • multiple saw blades may be used to cut the wafer.
  • cracking due to saw blade 903 cutting through saw path 111 may be inhibited from propagating to die area 105 by structures 113 and 115 which serve as crack stop trenches.
  • the solder of the cap (e.g. 309 ) is reflowed in a hydrogen furnace to form a solder ball on the copper studs (e.g. 307 ).
  • the solder of the caps are reflowed prior to singulation.
  • the solder of the caps are reflowed after the etching of layer 205 and prior to the removal of layer 203 .
  • FIG. 10 shows a top portion of wafer 101 .
  • Wafer 101 includes multiple die areas with die areas 1005 , 1006 , 1007 , and 1008 being shown in FIG. 10 . Shown between the die areas are scribe areas 1003 and 1004 . Located in scribe areas 1003 and 1004 are saw paths 1009 and 1010 , respectively. Scribe area 1004 has a width of 1023 which in one embodiment is 100 microns. Saw path 1010 has a width of 1021 , which in one embodiment is 50-55 microns. In one embodiment, the width of saw path 1010 is the width of a saw blade (e.g. 903 ) plus tolerances for alignment and placement. In one embodiment, those tolerances are 5 microns. To singulate die areas 1005 - 1008 into die, a saw blade e.g. 903 is cuts through wafer 101 along saw path 1010 and 1009 .
  • a saw blade e.g. 903 is cuts through wafer 101 along saw path 1010 and 1009
  • not all of the metal of conductive structures 113 and 115 and not all of the exposed metal in saw path 111 is removed prior to singulation of the die areas.
  • singulation may be performed on the wafer structure as it is shown in FIG. 7 , where only the copper located in stack layers 703 and 704 (or in some embodiments, in only layer 703 ) is removed.
  • conductive material at some of the lower layers may be removed as well.
  • the exposed copper in saw path 111 and the copper in conductive structures 113 and 115 at stack layers 703 , 704 , 705 and 706 may be removed wherein the copper in stack layers 707 and below would remain.
  • the conductive structures of the scribe area may be made of other types of metal such as gold, silver, or aluminum.
  • the removal of metal from a scribe area may be utilized with die structures of other types and/or configurations.
  • the removal of metal from a scribe area may be utilized for a die structure with no polyimide layer 124 .
  • the removal of metal from a scribe area may be utilized with die structures having other types of external conductive connection structures e.g. such as die not utilizing a solder cap (e.g. 309 ) where wire bonds are attached to copper studs (e.g. 307 ).
  • the scribe area width of a wire bond wafer can be 80 ⁇ m, where the wafer is back ground to 0.35 mm thickness, and a 30-35 ⁇ m saw blade is used for singulation. Also in other embodiments, the removal of exposed metal from a saw path may be made in die not implementing crack stop trenches 807 and 809 . In other embodiments, layers 203 and 205 and stud 307 may be made of nickel.
  • a method of forming a semiconductor die includes providing a wafer.
  • the wafer includes a substrate and a stack layer comprising a plurality of layers with interconnecting metal overlying the substrate.
  • the stack layer comprises exposed metal at a portion of a surface of a saw path within a scribe area separating a plurality of die. Some of the exposed metal extends into the plurality of dielectric layers.
  • the method further includes forming a dielectric passivation layer selectively overlying the stack layer and removing exposed metal at least to a first depth in a saw path of the scribe area to form recessed regions in the saw path.
  • a semiconductor wafer in another aspect of the invention, includes a substrate and a stack layer.
  • the stack layer comprises a plurality of layers overlying the substrate and includes interconnect metal.
  • the wafer includes a first die area and a second die area separated by a scribe area.
  • the wafer further includes a dielectric passivation layer selectively overlying the stack layer and a saw path within the scribe area. The saw path has at least one recessed region in the stack layer in which metal has been removed.
  • a method of forming a semiconductor die includes providing a substrate on a wafer having multiple die areas that are physically separated by a plurality of scribe areas each having a saw path. The method also includes forming a stack layer overlying the substrate and having dielectric material and interconnecting metal. The stack layer includes exposed metal at a portion of a surface of a saw path of a scribe area of the plurality. The method further includes processing the saw path within the scribe area by etching the exposed metal to at least a first depth to form a recessed region in the saw path.

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US10/351,798 2003-01-27 2003-01-27 Metal reduction in wafer scribe area Expired - Lifetime US6951801B2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
US10/351,798 US6951801B2 (en) 2003-01-27 2003-01-27 Metal reduction in wafer scribe area
TW093100911A TWI325155B (en) 2003-01-27 2004-01-14 Metal reduction in wafer scribe area
PCT/US2004/001925 WO2004073014A2 (fr) 2003-01-27 2004-01-23 Reduction metallique dans la zone de decoupe d'une plaquette
JP2006502974A JP2006516824A (ja) 2003-01-27 2004-01-23 ウエハ・スクライブ領域の金属低減
KR1020057013873A KR101001530B1 (ko) 2003-01-27 2004-01-23 웨이퍼 스크라이브 영역 내의 금속 감소
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US9331019B2 (en) 2012-11-29 2016-05-03 Infineon Technologies Ag Device comprising a ductile layer and method of making the same
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US8937009B2 (en) 2013-04-25 2015-01-20 International Business Machines Corporation Far back end of the line metallization method and structures
US10553508B2 (en) 2014-01-13 2020-02-04 Nxp Usa, Inc. Semiconductor manufacturing using disposable test circuitry within scribe lanes
US9601354B2 (en) 2014-08-27 2017-03-21 Nxp Usa, Inc. Semiconductor manufacturing for forming bond pads and seal rings
US11114384B2 (en) * 2017-10-13 2021-09-07 Infineon Technologies Austria Ag Oxide-peeling stopper

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CN1777978A (zh) 2006-05-24
JP2006516824A (ja) 2006-07-06
TW200416857A (en) 2004-09-01
CN1777978B (zh) 2010-07-21
WO2004073014A2 (fr) 2004-08-26
US20040147097A1 (en) 2004-07-29
KR20050095630A (ko) 2005-09-29
TWI325155B (en) 2010-05-21
WO2004073014A3 (fr) 2005-04-21

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