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US3860914A - Digital data recorder - Google Patents

Digital data recorder Download PDF

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Publication number
US3860914A
US3860914A US321910A US32191073A US3860914A US 3860914 A US3860914 A US 3860914A US 321910 A US321910 A US 321910A US 32191073 A US32191073 A US 32191073A US 3860914 A US3860914 A US 3860914A
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US
United States
Prior art keywords
counter
output
stage
digital data
recorder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US321910A
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English (en)
Inventor
William E Zitelli
Alan F Mandel
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Westinghouse Electric Corp
Original Assignee
Westinghouse Electric Corp
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Filing date
Publication date
Application filed by Westinghouse Electric Corp filed Critical Westinghouse Electric Corp
Priority to US321910A priority Critical patent/US3860914A/en
Priority to GB5999673A priority patent/GB1460747A/en
Priority to CA189,236A priority patent/CA984471A/en
Priority to DE2400112A priority patent/DE2400112A1/de
Priority to ES1974199301U priority patent/ES199301Y/es
Priority to BE1005628A priority patent/BE809486A/xx
Application granted granted Critical
Publication of US3860914A publication Critical patent/US3860914A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G21—NUCLEAR PHYSICS; NUCLEAR ENGINEERING
    • G21C—NUCLEAR REACTORS
    • G21C17/00—Monitoring; Testing ; Maintaining
    • G21C17/10—Structural combination of fuel element, control rod, reactor core, or moderator structure with sensitive instruments, e.g. for measuring radioactivity, strain
    • G21C17/12—Sensitive element forming part of control element
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/40—Monitoring; Error detection; Preventing or correcting improper counter operation
    • H03K21/403—Arrangements for storing the counting state in case of power supply interruption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
    • H03K23/50—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits
    • H03K23/56—Reversible counters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E30/00—Energy generation of nuclear origin
    • Y02E30/30—Nuclear fission reactors

Definitions

  • a digital data recorder having inherent circuitry characteristics that will re-establish the recorded data state previously established just prior to a power failure upon the return of the source power supply.
  • the retentive characteristics of the recorder are supplied from an arrangement of magnetic memory cores which controllably vary the time constants associated with given portions of the circuitry of a digital counter comprising the major subunit of this invention.
  • the counter is supplied with a zero inhibit to prevent reverse counting past the zero output state, thus preventing a false indication of the recorded data.
  • the circuitry thus described basically comprising solid state elements, provides a compact, resilient unit with no mechanical moving elements.
  • the present invention is related in general to digital data recorders and more particularly to such recorders that retain data information for later presentation upon loss of the recorder supply voltage.
  • the plant power demand controls adjustment of the position of control rod banks within the reactor.
  • An important safety feature in the operation of the plant is the ability to record the required control rod bank position and secure this information in the event of a loss of power to the recorder.
  • the rod position demand data is independent of the actual rod position data obtained from sensors positioned along the control rod housing and therefore it is specifically desirable to record the rod position demand data so that it can be compared with the actual rod position to insure that the rods are following their respective control signals. Additionally, in the event of a plant power supply failure, the apparatus assigned to record data will be required to maintain the information for presentation upon the resumption of power to enable the plant operator to determine the rod position demand at the time of failure.
  • the first utilizes pulsed signals generated from relay contact closures to simulate discrete rod movement demands.
  • the pulsed signals are communicated to a solenoid, which when energized, mechanically forces a stepping relay in the form of a wheel to be rotated one step.
  • the wheel is numbered from zero to nine and is mechanically connected to other similarly numbered wheels geared in a manner to record and display a decimal output count.
  • the decimal number is then representative of the position demand of the rod control bank. Since the stable output states of the counter are independent of the source power supply, the data can be maintained irrespective of a loss of plant power.
  • pulsed signals generated from relay contact closures representative of discrete rod movement demands are communicated to a pulse conditioning circuit.
  • This circuit modifies the pulses to drive an up-down counter formed basically from diode transistor logic gates.
  • the outputs of the counter are then connected to relay drivers which energize latching reed relays.
  • the digital output displayed by the latching reed relays is then proportional to the rod position demand and is retained in the state of the relays which can only be altered by further pulsing of the counter. In the manner, any loss of power to the system will not result in loss of the recorded information.
  • this invention provides a compact, resilient,
  • the electronic, digital data recorder having the inherent circuitry characteristics of re-establishing the recorded data state previously established just prior to a power failure upon the return of the source power supply.
  • the retentive features of the recorder are supplied from a novel arrangement of magnetic memory cores which controllably vary the time constants associated with part of the recorder circuitry within the feedback loops of an incorporated digital counter.
  • the counter is supplied with a zero state inhibit to prevent counter stepping in reverse count past the zero data output state, which would otherwise exhibit itself as a false indication of the recorded data.
  • the entire recorder unit, excluding memory cores is amenable to solid state construction and is operable in extremely adverse environments, such as are found in nuclear reactor applications, to provide a reliable and durable output function.
  • FIG. I is a block diagram of one embodiment of the data recorder of this invention.
  • FIG. 2 is a block diagram of a one bit stage of the counter identified in FIG. 1;
  • FIG. 3 is a schematic circuitry diagram of theone bit stage previously identified in FIG. 2;
  • FIG. 4 is a schematic circuitry diagram of the first two stages of the counter identified in FIG. 1;
  • FIG. 5 is a schematic circuitry diagram of the third stage of the counter previously identified in FIG. 1;
  • FIG. 6 is a simplified schematic circuitry diagram illustrative of the retentive characteristics of the circuits previously described in FIGS. 4, S and 6;
  • FIG. 7 is a graphical illustration of the hysteresis loop of the magnetic memory core utilized in the circuits of FIGS. 4, 5 and 6;
  • FIG. 8 is a schematic circuitry diagram of the pulse conditioning circuit previously identified in FIG. 1;
  • FIG. 9 is a schematic circuitry diagram of the power control circuit previously identified in FIG. I.
  • FIGS. 10A and 10B show graphical illustrations of the input and output signals exhibited by the circuit of FIG. 9 in response to changes in the source supply voltage.
  • this invention provides a compact, resilient, electronic, digital data recorder having the inherent circuitry characteristics of re-establishing the recorded data state previously established just prior to a power failure upon the return of the source power supply.
  • the recorder excluding a novel arrangement of saturable magnetic cores within an incorporated digital counter, is amenable to solid state construction and the entire unit is operable in extremely adverse environments, such as are found in nuclear reactor applications, to provide a reliable and durable output function.
  • shut down rods Most nuclear reactors utilize three types of neutron absorber rods respectively known as shut down rods, part length rods and control rods. With each type of rod there is associated a number of rod banks, and within each bank there is contained a number of rod mechanisms.
  • An example of such a nuclear reactor rod system is more fully described in US. Pat. No. 3,654,607 to Andre Wavre et al entitled Signal Sequencing System," issued Apr. 4, 1972 and assigned to the assignee of the present invention.
  • the shut down rods are operable to be either driven full out" when the reactor is at full power or full in” when the power is shut down.
  • the control rods are moved either up or down incrementally in banks, with all the rods within a given bank being moved to the same level simultaneously; the level depending upon the power demand of the plant.
  • the part length rods act as verniers and are never entirely out of or in the reactive region, but are driven either up or down within a small range of steps.
  • the full length control rods are moved up and down within pressurized housings by magnetic jack drive mechanism more fully described in US. Pat. No. 3,158,766, issued to E. Frisch and assigned to the assignee of the present invention. It takes approximately 232 pulsed steps to cover the total distance of control rod travel, which amounts to approximately a total distance of 144 inches.
  • Other mechanisms generally exist for driving the part length rods to obtain their vernier control.
  • a control rod drive shaft position sensor normally located along the control rod housing is commonly provided for this purpose to sense the position of the control rod drive shafts which are affixedly coupled to the control rods. The position information thus obtained is then translated to actual control rod position.
  • An example of such a monitoring device can be found in the application to .l. A. Neuner, F. T. Thompson and L. Vercellotti entitled Digital Multiplex Position Indication and Transmission System, Ser. No. 320,792, filed Jan. 3, 1973, (WE. 44,067).
  • the present invention provides a resilient, electronic, data recorder having the inherent circuitry characteristics of re-establishing the recorded data state previously exhibited just prior to a power failure upon the return of the source power supply.
  • the entire recorder unit is designed to be operable in the extremely adverse environment of a reactor containment to provide reliable and durable output information which can be used for the comparisons required in nuclear applications.
  • the digital data recorder thus contemplated is generally illustrated in FIG. 1 as basically comprising a pulse conditioning circuit 10, an updown retentive counter 12 and a power control circuit 14.
  • the pulse conditioning circuit 10 will receive either an up or down control rod drive pulse from the relay contact closure 16 or 18 respectively, simulating discrete rod position movement demands.
  • the signals are processed by the pulse conditioning circuit 10 to a form compatible with the up-down retentive counter 12.
  • Zero detect circuitry forming a portion of the pulse conditioning unit 10, monitors the counters output, shown in binary coded form by reference character 20, and is responsive to the zero counter state to inhibit further reverse counting which could otherwise result in returning the counter to maximum count.
  • the up-down retentive counter 12 is basically constructed from high threshold integrated logic circuits in a toggle flip-flop configuration.
  • a block diagram of a one bit circuitry section of the counter is shown in FIG. 2.
  • the separate counter stages are synchronized by the up-down rod drive pulses emanating respectively from the relay outputs 16 and 18 shown as the input functions 21 in FIG. 2.
  • the up and down pulses 21 are supplied to a series of logic circuits which process the information conveyed to a form compatible with the digital counter output desired.
  • the output from the logic unit is then applied to a trigger circuit 25 which drives a multiple configuration of toggle flip-flops.
  • the toggle flip-flops basically comprise two stages of RS flip-flops.
  • a retentive circuit which provides the desired memory characteristics of this invention is formed as an integral part of the master section of each toggle flip-flop and employs the principle of either setting or resetting, upon power turn off or turn on, the RS flip-flops to their prepower failure state.
  • the set-reset decision is dependent upon the magnetic flux density existing within an inductive core located within a feedback loop of the master section of the flip-flop.
  • FIG. 3 A simplified circuitry schematic of a one bit section of the counter circuitry is illustrated in FIG. 3 with the counters three stages 22, 24 and 26 shown in more detail in FIGS. 4 and 5.
  • FIG. 6 provides a simplified schematic of the actual retentive circuit of the master section of one portion of the counter with the corresponding hysteresis loop of the inductor being illustrated in FIG. 7.
  • the figures in combination with the following description will provide a complete understanding of the operation of the circuits illustrated.
  • FIG. 3 The circuitry associated with a one bit section of the counter is illustrated in FIG. 3 and forms the basic building block of the counter, which comprises a plural arrangement of toggle flip-flops.
  • a toggle flip-flop is constructed from an arrangement of two RS flip-flops; the first forming the master and the second forming the slave stage.
  • the master stage is generally indicated in FIG. 3, by the NAND gates 42 and 44 and the slave stage is indicated by reference characters 34 and 38.
  • the memory characteristics of the circuit are essentially supplied by the inductive core L and its corresponding time constant associated with the feedback loop of the master stage.
  • NAND gates 32 and 36 form the triggering portion of the circuit previously identified in FIG. 2 by reference character 25 and function to assure that the master stage is responsive to the falling edge and the slave stage is responsive to the rising edge of the input pulse.
  • NAND gate 40 appearing at the output serves to provide output isolation and acts as the buffer 30 previously noted in FIG. 2, to prevent current drain on the circuit.
  • FIG. 4 illustrates a four hit counter output stage and is employed to form the first and second stages 22 and 24 of the counter 12.
  • the circuit illustrated in FIG. 3 supplies the basic building block for the individual counter output bit circuits 46, 48, 50 and 52, with the digital output bits 20 being identified by A, B, C and D, respectively.
  • NAND gates 54 form the logic circuitry previously identified by reference characters 23 in FIG. 2, and function to condition the inputs so that circuitry of the counter can provide the digital outputs in the desired form.
  • the diodes 56 OR the NAND gate outputs to the appropriate counter bit circuit inputs, while the NAND gates identified by reference character 58 monitor the output bits of the counter to identify the zero count state. The latter information is then conveyed to the pulse conditioning circuit at output terminal 60 for combination with the other counter monitoring outputs provided by the other two counter stages.
  • FIG. 5 illustrates the last stage of the counter previously identified by reference character 26 in FIG. 2, which provides a two bit output.
  • Circuits circuits 62 and 64 function in the same manner as the circuits previously described by reference characters 46, 48, 50 with 52, and the appropriate counter output bits taken at terminals 66 and 68.
  • the operation of the retentive memory cell which forms a portion of the feedback loop of the master section of the toggle flip-flop can best be understood by reference to the simplified schematic provided in FIG. 6 and the corresponding graphical illustration shown in FIG. 7.
  • the basic principle of operation is dependent upon a comparison to two time delays T and T corresponding to the time constants 1' and 7 associated with the toggle flip-flops.
  • 'r is a fixed time constant dependent upon the characteristic of the capacitor C, the resistor R and the internal pull up resistance associated with the reset input to NAND gate 42 in FIG. 6.
  • 1' is a time constant which varies depending upon the last output state 0 of the flip-flop. As will be appreciated by those skilled in the art 1', is governed by the state of the magnetic core generally associated with the inductor L.
  • the saturable magnetic core L is desirably constructed from a magnetic material having magnetic characteristics which provide a substantially rectangular hysteresis loop, such as the one illustrated in FIG. 7. Therefore, the output 0 will assume either of two stable states, high or low.
  • the following two examples which illustrate the two output states Q can assume, will completely describe the operation of the memory core in the event of a power failure.
  • the retentative characteristics provided by the magnetic core L within the feedback loop of the master section of the toggle flip-flop, retains the output established for each bit of the counter just prior to a source power failure and re-establishes this prior output state upon the resumption of the source power sup- PULSE CONDITIONING CIRCUIT
  • the pulse conditioning circuit previously identified by reference character 10 in FIG. 1 is shown in schematic circuitry form in FIG. 8.
  • the up and down pulses, simulating the rod position demand data, are respectively received at terminals and 72.
  • the resistor capacitive filter provided by resistors and capacitors 78 establish a sufficient time delay to avoid multiple counts which might otherwise occur due to contact bounce of the relays l6 and 18.
  • the zero inhibit is responsive to the zero counter state to prevent further down rod command pulses from entering the counter.
  • NAND gates 58 illustrated in FIG. 4 were described as the mechanism for monitoring the individual toggle flipflop circuits to identify when the zero state had been assumed by the circuits respective outputs.
  • the respective outputs 60 from the first two stages are then applied to the input terminal 60 of the pulse conditioning circuit illustrated in FIG. 8.
  • NANDgates 94 are used to monitor the last stage of the counter 12 to provide a corresponding output indicative of the zero state.
  • the respective monitoring outputs from the three stages of the counter are then applied to the input of NAND gate 96 which inhibits NAND gate 88 upon the occurrence of the zero state, effectively disconnecting the output from further down stepping the counter.
  • the pulse conditioning circuit modifies the input data pulses to a form compatible with the counter and effects the zero inhibit to prevent counter stepping, in reverse count, past the zero data output state.
  • the power control circuit illustrated in FIG 1 is schematically shown in FIG. 9 with a graphical illustration of the corresponding inputs and outputs provided in FIG. 10.
  • the circuit is designed to force the supply voltage furnished to the retentive counter to be switched on and off much faster than the shortest time constant of the counter in order to assure the retentiveness of the information maintained therein.
  • the input time constant of the circuit dependent upon the component values of resistor 102 and capacitors 98 and 100, controls the rise time of the input power supply voltage applied between terminals 118 and ground.
  • transistors 104 and 108 When the input supply voltage rises above the threshold voltage level governed by the diode drops appearing across transistors 104 and 108 and Zener 106, transistors 104 and 108 conduct, essentially grounding the collector of transistor 108, which, in turn, saturates transistor 110 and abruptly reverse biasesrtransistor 112. As transistor 110 abruptly transitions to its ON state, current is fed back to the base of transistor 104 forcing a sharp rising edge on the voltage displayed at output terminal 114. This output voltage is then applied to the supply voltage inputs of the recorder circuitry.
  • the Zener and transistors are chosen to supply a threshold voltage sufficient to support the working operation of each of the elements of the data recorder so that when the power supply reaches the threshold voltage level, upon turn on, an almost instantaneous operating voltage appears at the supply inputs to the data recorder circuitry.
  • the power control circuit supply the input supply voltage to each of the subunits of the recorder in order to assure minimum turn on and turn off times so as to prevent alteration of the data output state retained by the counter.
  • the power control circuit is provided for this purpose.
  • the individual element units described are amenable to solid state construction and are arranged in the configuration illustrated in FIG. 1 to exhibit the desired characteristics, in extremely adverse environments such as are found in nuclear reactor applications, to provide a reliable and durable output function.
  • a digital data recorder having an electronic counter responsive to a data input to provide a representative digital output exhibited by a plurality of bistable output bits, the counter including a plurality of toggle flip-flop output circuits corresponding to the plurality of output bits, each ofsaid toggle flip-flops including a master and a slave stage with the corresponding output bit being provided by the slave stage, the master stage including a variable reactance within a feedback loop in the master stage, the value of the variable reactance being dependent upon the stable state of the output bit to control and vary a time constant of the feedback loop in a manner to re-establish the output bit last exhibited by the slave stage prior to a failure of supply voltage power to the counter after the supply power has been resumed.
  • the digital data recorder of claim 1 wherein the master stage of said toggle flip-flop has an input from the supply voltage powering the counter and exhibits a separate fixed, predetermined, time constant independent of said variable reactance which controls the rise time of the supply voltage input and is substantially greater than the value of the time constant of the feedback loop controlled by the value of the variable reactance corresponding to one of the bistable states of the output bit of the slave stage and is substantially less than the value of the time constant of the feedback loop controlled by the value of the variable reactance corresponding to the other of the bistable states of the output bit of the slave stage.
  • variable reactance comprises an inductor wound on a saturable magnetic core exhibiting rectangular hysteresis with the saturable state of the core dependent upon 5.
  • said counter advances count in response to the data input in either a forward or reverse counting direction corresponding to the data input receiver, including means for inhibiting said counter from advancing count in reverse count past the counter bit output state representative of a zero data count.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • General Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Investigating Or Analyzing Materials By The Use Of Magnetic Means (AREA)
  • Monitoring And Testing Of Nuclear Reactors (AREA)
  • Measurement Of Resistance Or Impedance (AREA)
  • Control Of Electrical Variables (AREA)
US321910A 1973-01-08 1973-01-08 Digital data recorder Expired - Lifetime US3860914A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
US321910A US3860914A (en) 1973-01-08 1973-01-08 Digital data recorder
GB5999673A GB1460747A (en) 1973-01-08 1973-12-28 Digital data recorder
CA189,236A CA984471A (en) 1973-01-08 1973-12-31 Digital data recorder
DE2400112A DE2400112A1 (de) 1973-01-08 1974-01-03 Digitales datenaufzeichnungsgeraet
ES1974199301U ES199301Y (es) 1973-01-08 1974-01-07 Un registrador de datos digital.
BE1005628A BE809486A (fr) 1973-01-08 1974-01-08 Enregistreur d'information digitale

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US321910A US3860914A (en) 1973-01-08 1973-01-08 Digital data recorder

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US3860914A true US3860914A (en) 1975-01-14

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US321910A Expired - Lifetime US3860914A (en) 1973-01-08 1973-01-08 Digital data recorder

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US (1) US3860914A (de)
BE (1) BE809486A (de)
CA (1) CA984471A (de)
DE (1) DE2400112A1 (de)
ES (1) ES199301Y (de)
GB (1) GB1460747A (de)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4084232A (en) * 1977-02-24 1978-04-11 Honeywell Information Systems Inc. Power confidence system
USRE29642E (en) * 1973-10-19 1978-05-23 Ball Corporation Programmable automatic controller
US4228502A (en) * 1977-06-29 1980-10-14 Hitachi, Ltd. Electronic computer system
US4370549A (en) * 1979-04-20 1983-01-25 Olympus Optical Co., Ltd. Electronic counter circuit for tape recorder
US5958069A (en) * 1996-11-19 1999-09-28 Fujitsu Limited Apparatus for preventing malfunction at time of duplex unit failure
CN107833643A (zh) * 2017-10-16 2018-03-23 中核核电运行管理有限公司 全数字化棒位测量装置及其方法
CN113643834A (zh) * 2021-08-11 2021-11-12 华能山东石岛湾核电有限公司 高温气冷堆燃料球提升时间的组态实现系统及实现方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2176959B (en) * 1985-06-18 1989-07-19 Motorola Inc Cmos power-on detection circuit

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3003141A (en) * 1959-02-18 1961-10-03 Ibm Ring circuits
US3154671A (en) * 1962-03-22 1964-10-27 Honeywell Inc Electrical counting apparatus including saturable magnetic cores
US3214606A (en) * 1962-08-13 1965-10-26 Gen Motors Corp Retentive memory bistable multivibrator circuit with preferred starting means
US3408505A (en) * 1963-12-18 1968-10-29 C & K Components Inc Electronic timing via magnetic core shift circuitry
US3487381A (en) * 1964-11-14 1969-12-30 Philips Corp Reversible ring counters comprising bistable transductors

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3003141A (en) * 1959-02-18 1961-10-03 Ibm Ring circuits
US3154671A (en) * 1962-03-22 1964-10-27 Honeywell Inc Electrical counting apparatus including saturable magnetic cores
US3214606A (en) * 1962-08-13 1965-10-26 Gen Motors Corp Retentive memory bistable multivibrator circuit with preferred starting means
US3408505A (en) * 1963-12-18 1968-10-29 C & K Components Inc Electronic timing via magnetic core shift circuitry
US3487381A (en) * 1964-11-14 1969-12-30 Philips Corp Reversible ring counters comprising bistable transductors

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE29642E (en) * 1973-10-19 1978-05-23 Ball Corporation Programmable automatic controller
US4084232A (en) * 1977-02-24 1978-04-11 Honeywell Information Systems Inc. Power confidence system
US4228502A (en) * 1977-06-29 1980-10-14 Hitachi, Ltd. Electronic computer system
US4370549A (en) * 1979-04-20 1983-01-25 Olympus Optical Co., Ltd. Electronic counter circuit for tape recorder
US5958069A (en) * 1996-11-19 1999-09-28 Fujitsu Limited Apparatus for preventing malfunction at time of duplex unit failure
CN107833643A (zh) * 2017-10-16 2018-03-23 中核核电运行管理有限公司 全数字化棒位测量装置及其方法
CN107833643B (zh) * 2017-10-16 2019-05-24 中核核电运行管理有限公司 全数字化棒位测量装置及其方法
CN113643834A (zh) * 2021-08-11 2021-11-12 华能山东石岛湾核电有限公司 高温气冷堆燃料球提升时间的组态实现系统及实现方法

Also Published As

Publication number Publication date
BE809486A (fr) 1974-07-08
ES199301Y (es) 1975-11-16
DE2400112A1 (de) 1974-08-01
ES199301U (es) 1975-08-01
GB1460747A (en) 1977-01-06
CA984471A (en) 1976-02-24

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