US3484708A - Current driver with overload protection - Google Patents

Description

Dec. 16, 1969 L. ILLINGWORTH CURRENT DRIVER WITH OVERLOAD PROTECTION Filed March 21, 1967 DIRECT VOLTAGE SUPPLY I INVENTOR LEWIS ILLINGWORTH PULSE SOURCE ATTORNEY$ US. Cl. 33011 United States Patent ABSTRACT OF THE DISCLOSURE A current amplifier having a comparatively high degree of protection against overload damage has an output stage arranged to deliver to a load only the current a storage capacitor accumulates from a constant current source. So long as the storage capacitor is not discharged, the output current level corresponds to an input signal applied to an input control stage that operates the output stage.

BACKGROUND This invention relates to an electrical current amplifying circuit of relatively high pulse-current capability but of such limited sustained-current capability as to minimize circuit damage due to excessive operation. The invention is particularly useful in a memory-test current driver. This is an electrical supply for impressing on a magnetic core memory a controllable test current, generally in the form of a pulse having short rise and decay times.

Current drivers for memory-test operation, as Well as many other current amplifying circuits, generally have to produce current pulses adjustable to relatively large magnitudes. Further, the pulses should faithfully correspond in duration and in rise and fall times to a controlling input pulse. However, current drivers are likely to be subjected to overload conditions that call upon the circuit to produce an excessive average output current. This excessive operation often results in destructive damage to the circuit and/ or in like damage to the load. By way of example, memory-test current drivers are subject to overload by accidental application of a low resistance or short circuit across the output terminals by operation with input signals that call for excessively large and/01' excessively long output pulses, and by transients developed at the output terminals due to the large reactance of the load impedance. The relatively reactive, principally inductive, input impedance of magnetic core memories causes the latter condition to recur often.

In the prior art, protection against overload condi tions has involved considerable additional costs for protective circuitry. In addition, many prior overload-protected current drivers are still subject to damage under certain overload conditions.

Accordingly, it is an object of the present invention to provide a current-supplying circuit having improved overload protection. Further, the circuit should provide overload protection with a high degree of reliability under many different overload conditions.

A more particular object is to provide a transistor circuit of the above character capable of producing relatively large current pulses. The circuit should also be capable of producing such pulses with relatively short rise and fall times.

Another object is to provide a circuit of the above character which protects the load connected thereto from excessive current when the circuit is subjected to overload conditions.

It is also an object of the invention to provide a circuit of the above character of relatively simple and lowcost construction.

Other objects of the invention will in part be obvious and will in part appear hereinafter.

The invention accordingly comprises the features of construction, combination of elements, and arrangement of parts exemplified in the construction hereinafter set forth, and the scope of the invention is indicated in the claims.

SUMMARY OF THE INVENTION In the present current driver, the output current, both pulse and average, is limited. Further, avalanche breakdown of an output stage transistor is rendered essentially harmless. This multiple overload protection is attained automatically by supplying the output stage with the sum of a limited continuous current and a capacitively stored current. The continuous current is insufficient to damage the output stage components, and the quantity of stored charge in the capacitor is likewise insufficient to damage the circuit components, even during a rapid discharge.

On the other hand, the stored charge enables the output stage to produce current pulses having a magnitude considerably larger than the continuous current.

When the duration and/ or frequency of the pulses becomes excessive, the capacitively stored current is consumed and the output current from the driver decreases to a level limited by the continuous supply current. Until the capacitively stored current is largely exhausted, however, the driver maintains the output current at the level prescribed by the input signal it receives.

When an output transistor of the driver avalanches, the transistor in effect consumes the limited capacitively stored current without damage and is then limited to the continuous current, which is also insuificient to damage the transistor.

BRIEF DESCRIPTION OF THE DRAWINGS For a fuller understanding of the nature and object of the invention, references should be had to the following detailed description taken in connection with the accompanying drawing, which is a schematic representation of a current driver employing the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to the drawing, the current driver has an input control stage indicated generally at 10 comprising transistors 12 and 14. During normal operation, in response to an input signal from a pulse source 18, the input stage causes an output stage 16 to apply a current waveform corresponding to the input signal waveform to an electrical load 20. Where the driver is used for memory-test purposes, the load is a magnetic core memory.

The driver also has a current-supplying stage 22 in which a transistor 26 delivers a constant current in parallel to a storage capacitor 24 in the stage 22 and to the output stage 16. The control stage transistors 12 and 14 also draw a small part of this constant current.

The maximum current the output stage can deliver to the load, available when the storage capacitor 24 is charged, is the charge on the capacitor plus the larger part of the constant current from the transistor 26. However, when the storage capacitor is discharged, the output current is limited to the constant current from the supply stage 22.

The driver is arranged, by appropriate selection of component values, so that the storage capacitor 24 becomes discharged when the average output current approaches an excessive level. The output level can become excessive in many ways, including an avalanche breakdown of an output stage transistor, and an input signal of excessive magnitude calling on the output stage to produce excessive output current. In addition, although the driver can safely produce large output pulses by drawing on the charge in the capacitor 24, a rapid succession of such large pulses might damage an output stage transistor by causing excessive heating therein. Accordingly, a succession of pulses that causes an excessive average output current is also an overload condition against which the driver is protected.

More particularly, in the current-supplying stage 22, the direct voltage from an external supply 23 develops a fixed reference voltage across a diode 28, which generally comprises plural diodes in series to sum their individual forward voltage drops. This reference voltage causes the transistor 26 to deliver a known constant current at its collector 26b from the supply through a resistor 30 connected to its emitter 26a. The transistor 26 preferably is a low frequency transistor not subject to avalanche breakdown.

The input stage transistor 14 draws a small part of the constant current from the transistor 26. The balance passes through a diode 32, developing a substantially current-independent voltage drop thereacross, and is delivered in parallel to the storage capacitor 24, the input stage transistor 12, and the output stage 16.

With further reference to the drawing, the supply 23 also applies a positive direct voltage across an adjustable voltage divider 34 in the control stage 10. This voltage develops a relatively small positive voltage at the transistor 12 emitter 12a through a resistor 36 connected to the voltage divider tap 34a, A high-frequency bypass capacitor 38 is connected to ground from the tap.

In the interval between pulses from the illustrated source 18, the transistor 12 receives a small positive quiescent voltage at its base 120. The voltage divider 34 is adjusted so that this quiescent voltage at the transistor base biases the transistor 12 to the point where a further increase in its base voltage will cause it to operate on the linear portion of its operating characteristic. In this condition, the transistor 12 draws a small bias current from the transistor 26 through the diode 32 and a resistor 42 connected to the collector 12b. The purpose of maintaining the transistor 12 at this quiescent condition is to have it faithfully reproduce positive pulses from the source 18.

When the resistor 42 is equal to the resistor 44 connected to the emitter of transistor 14, transistor 14 draws essentially the same emitter current as the transistor 12 draws at its collector 1212. This is because the series combination of resistor 42 and diode 32 is in parallel with the series combination of resistor 44 and the emitter-base junction of transistor 14. Further, the forward voltage drop across the diode 32 is substantially equal to the forward voltage drop across the transistor 14 emitter-base junction. Therefore, the voltage across resistor 44 is equal to the voltage across resistor 42 and hence the currents in the two equal resistors are equal.

The transistor 14 is therefore also maintained at a quiescent condition where it draws a small emitter current and will operate on the linear portion of its characteristics with a further increase in the voltage between its base and emitter.

The illustrated pulse source 18 develops positive pulses, typically having the waveform 40, at the transistor base 12c. In response to such a pulse, the transistor 12 draws a collector current determined substantially exclusively by the Value of resistor 36 and the difference between the pulse voltage and the voltage at the tap 34a. This collector current develops an amplified voltage, across the resistor 42, with a waveform 43 that is the amplified inverse of the input waveform 40. The resultant voltage drop at the base of transistor 14 causes it to draw an emitter current through resistor 44 corresponding to the current in resistor 42.

The transistor 12 thus operates as a common-emitter amplifier and the transistor 14 as an emitter follower.

In the output stage 16, three transistors 50, 52 and 54, each having an emitter resisor 56, 58 and 60 respectively, are arranged in parallel. The voltage devel ped across th 4 resistor 44, less the drop across the diode 32, is applied across the series combination of the emitter resistor and the emitter-base junction of each output transistor.

The quiescent current in the resistor 44 is insufficient to cause the output transistors to draw more than a small, essentially negligible, current. However, in response to the voltage developed across the resistor 44 by a pulse from the source 18, each output transistor normally applies to the load 20 a substantial current with a waveform closely corresponding to the input waveform 40. Accordingly, the load receives a large current pulse equal to the sum of the currents from the three output transistors. The emitter resistors 56, 58, determine in part the magnitude of the current each transistor draws and they also equalize the load current between the three transistors 50, 52 and 54.

The current the output transistors apply to the load is drawn from the transistor 26 and from the storage capacitor 24. When the input pulses from the source 18 are of relatively small magnitude or are short relative to the spacing between them, i.e. have a low duty cycle, the output transistors draw a relatively small average current and the capacitor 24 remains essentially charged, i.e. the constant current from transistor 26 essentially fully recharges it in the intervals between successive input pulses.

Further, in this non-excessive operating condition, even though the charge on capacitor 24 fluctuates, and correspondingly, the voltage across it and the voltage applied to the output stage 16 fluctuate the output current applied to the load 20 remains essentially uniformly related to the magnitude of the input signal. This is because, so long as the capacitor 24 is not substantially entirely discharged, the voltage across the resistor 42, and therefore the voltage across the resistor 44, are directly proportional to the magnitude of the input signal. The voltage across each resistor 56, 58 and 60 then also depends directly on the input signal magnitude.

However, when the overload conditions discussed above cause the output transistors to draw a large average current, the capacitor 24 becomes increasingly discharged. The voltage across the capacitor 24 then drops to the point where the output transistors saturate. In this condition, the total output current from the driver is limited essentially to the constant current provided by the transistor 26. This current is insufiicient to damage the output transistors, even on a continuous basis. Hence, the driver can tolerate prolonged application of an overload condition without damage.

In addition, by drawing on the charge in the storage capacitor 24, the driver can produce output current pulses at least five times greater than the constant current the transistor 26 develops, so long as the duty cycle does not become excessive.

With further reference to the drawing, it was described above that the diode 32 develops a current-independent forward voltage drop essentially equal to the forward drop across the emitter-base junction of transistor 14. When both the diode and the transistor are of silicon semiconductor material, as preferred, the two forward voltage drops vary equally with temperature. This is desired, for it enables transistor 14 to have essentially the same quiescent current as transistor 12 over a wide range of operating temperatures. As a result, the waveform of the output current pulse corresponds closely to that of the input pulse. More specifically, with a lesser quiescent current in transistor 14, its emitter current waveform will not correspond faithfully to the input pulse waveform. And a quiescent current larger than in transistor 12 will retard recharging of capacitor 24.

It should also be noted that the base of each output transistor is connected, by way of resistor 44, to a more positive potential than is the emitter. For example, the, base of transistor 50 is connected through resistor 44 to the anode of diode 32, while the transistor base is con nected by Way of the resistor 56 to the cathode of this diode. This arrangement facilitates maintaining each output transistor at' a quiescent condition where it is substantially just off, ready to conduct without significant delay when the transistor 12 receives an input signal.

As indicated above, when a transient condition causes the load to impress a voltage between the driver output terminals 62 which causes at least one transistor to avalanche, that transistor will tend to draw such an excessive current that it will burn out. However, in the present driver, just as the output transistors are prevented from drawing excessive average current due to excessive input signals, the avalanched'output transistor will discharge the capacitor 24 without being damaged and is then constrained to the safe level of constant current that the transistor 26 produces. Thus, the driver is not damaged by avalanche in its output transistors. Likewise, the load does not receive a sustained excessive current and is not damaged.

The value of the storage capacitor 24 is accordingly selected so that its charge is insufficient to destroy an output transistor even during a rapid discharge of the capacitor. On the other hand, the capacitor is large enough to produce the longest output pulse desired at the required maximum output current level.

It will thus be seen that the objects set forth above, among those made apparent from the preceding description, are efficiently attained. It is intended that all matter contained in the above description or shown in the accompanying drawing shall be interpreted as illustrative and not in a limiting sense.

It is also to be understood that the following claims are intended to cover all of the generic and specific features of the invention herein described, and all statements of the scope of the invention which, as a matter of lan' guage, might be said to fall therebetween.

What is claimed is:

1. A current amplifying circuit that normally produces an output signal with a waveform corresponding to the waveform of an input signal applied thereto, said circuit comprising (A) a source (22) of limited current,

(B) a capacitor (24) connected to be charged with the current from said source,

(C) circuit means (10, 16) for summing said limited current and the charge on said capacitor, said sum having a waveform substantially corresponding to the waveform of said input signal, and

(D) terminals (62) connected to receive the output of said circuit means.

2. A circuit according to claim 1 in which said circuit means comprises a transistor (50) having its emittercollector path in series with said output terminals, and having the series combination of said emitter-collector path and said output terminals in parallel with said capacitor.

3. A circuit according to claim 1 (A) further comprising a semiconductor junction (32) in series between said source and said capacitor and connected to conduct said current with a substantially current-independent voltage drop thereacross, and

(B) in which said circuit means comprises 1) a resistor (44), (2) a first transistor (14) (a) having its emitter-collector path in series with said resistor, and (b) having the combination of its emittercollector path and said resistor in parallel with the series combination of said junction and said capacitor, and (3) a further transistor (50) (a) having its emitter-collector path in series with said output terminals and with the combination of its emitter-collector path 75 and said output terminals in parallel with said capacitor, and

(b) having its base in circuit with the emitter of said first transistor to receive a potential corresponding to the potential at the emitter of said first transistor.

4. A circuit according to claim 3 in which said voltage drop of said semiconductor junction and the voltage drop of the base-emitter junction of said first transistor vary substantially equally due to changes in the temperatures of said junction.

5. A current amplifying circuit according to claim 1 in which said source of limited current comprises a transistor arranged as a source of substantially constant current.

6. A current amplifying circuit according to claim 5 in which (A) said capacitor is connected in the path of the collector current of said transistor, and

(B) said circuit means is connected to the inter-connection of said capacitor and said source, thereby to deliver to said output terminals the sum of current from said source available at said interconnection and current drawn from said capacitor.

7. A current driver comprising (A) a first transistor (26),

(B) a first resistor (30) connected to the emitter of said first transistor,

(C) a first diode device (28) l (1) connected in parallel with the series combination of said first resistor and the emitterbase junction of said first transistor, and

(2) conducting current with a substantially current-independent voltage drop of such a polarity as to forward bias the emitter-base junction of said first transistor,

(D) a second diode device (32) connected with the collector of said first transistor and developing a current-independent voltage drop thereacross in response to collector current from said first transistor,

(E) a common return conductor,

(F) a capacitor (24) connected between said second diode device and saidcommon return conductor,

(G) a second resistor (44),

(H) a second transistor (14) r (1) having said second resistor connected be tween the emitter thereof and the collector of said first transistor,

(2) having the collector thereof in circuit with said common return conductor,

(I) a third resistor (56) (I an output terminal (62) (K) a third transistor (50) (1) arranged with said third resistor connected between the emitter thereof and the inter-connection of said capacitor and said second diode device, and

(2) having the collector thereof connected with said output terminal.

8. A current driver according to claim 7 further comprising (A) a fourth resistor (42),

(B) a fourth transistor (12) (1) arranged with said fourth resistor connected between the collector thereof and the interconnection of said capacitor and second diode device,

(2) having the collector thereof in circuit with the base of said second transistor to apply to said second transistor base a potential corresponding to the potential at the collector thereof.

9. A current driver according to claim 8 further comprising (A) a fifth resistor (36) connected to the emitter of said fourth transistor, and

(B) direct voltage supply means arranged to apply a biasing voltage between said return conductor and the end of said fifth resistor remote from said fourth transistor.

10. A current driver according to claim 8 (A) in which each of said second and fourth transistors are arranged to draw substantially the same quiescent current.

8 References Cited UNITED STATES PATENTS 2,980,845 4/1961 Thompson et al 323-22 3,277,386 10/1966 Miyazawa 307--202 NATHAN KAUFMAN, Primary Examiner US. Cl. X.R.

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