US3201603A

US3201603A - Switching circuits

Info

Publication number: US3201603A
Application number: US197229A
Authority: US
Inventors: Gerlach Albrecht
Original assignee: Clevite Corp
Current assignee: Clevite Corp
Priority date: 1961-05-31
Filing date: 1962-05-23
Publication date: 1965-08-17
Anticipated expiration: 1982-08-17
Also published as: DE1168964B; GB1009063A

Description

Aug. 17, 1965 A. GERLACH SWITCHING CIRCUITS Filed May 23. 1962 INVENTOR. ALBRECHT GERLACH ATTORNEY United States Patent a l Albrecht Gerlacil,

This invention relates to circuit arrangements for binary counters or pulse frequency dividers.

As is well-known, present day commercial electronic counters embody decade counters made up of a cascade of binary stages. Each binary stage is capable of assuming two stable conditions and, customarily, four such stages are interconnected and permutated to count input pulses up to 1'0 and then to re-cycle after each tenth pulse.

The individual binary stages as well as the circuit arrangements by which they are interconnected take a Wide variety of forms using diverse switching devices such as electron tubes, relays, transistors and the like.

The fundamental object of the present invention is to provide a switching circuit which is far less complex than known heretofore and in which each binary stage has only a single bistable element.

T he switching devices customarily are arranged in pairs, i.e., two to a stage, and interconnected in inverse relation as regards condition or the members of the pair. In other words, if one member of a pair is conductive the other is cut-oil. This leads to rather complex circuit configurations embodying relatively large numbers of components.

Stated generally, switching circuits according to the present invention comprise a plurality of bistable circuit elements each having a Thyratron characteristic and distinct stable conditions of conductivity and non-conductivity; and circuit means coupling the bistable elements in a cascade so constructed and arranged that a change in condition in one of the bistable elements causes a change in condition of a succeeding bistable element only when the change in condition in the first bistable element is from non-conductivity to conductivity.

Additional objects of the invention, its advantages, scope and the manner in which it may be practiced will be more readily apparent to persons conversant with the art from the following detailed description of an exemplary embodiment thereof taken in conjunction with the subjoined claims and the annexed drawing in which the single figure is a schematic wiring diagram of a decade counter embodying the present invention.

Before describing the circuit represented by the wiring diagram and its function, it is pointed out that thyratron characteristic as used herein is intended to denote the property of a circuit element which enables it, upon the application of a prescribed Voltage, to switch abruptly into a low impedance or conductive condition and, upon exceeding a certain critical current, to switch back to a high impedance or non-conductive condition. In the embodiment described hereinbelow by way of example the bistable element having a Thyratron characteristic is a two terminal device, viz., a four layer semiconductor diode (sometimes referred to as a Shockley Diode); it is to be understood, however, that other bistable devices can be used including devices having control electrodes, comparable to the grid of a Thyratron tube, and/ or other electrodes.

Referring now to the drawings, there is illustrated schematically the essential circuitry of a decade counter embodying the present invention. Inasmuch as the device consists of a plurality of substantially identical stages connecte in cascade, the circuit configuration repeats itself and, accordingly, has been sub-divided by broken lines A, B, C, I) and E into four substantially identical segments. Segments A-B, B-C, and C-D, in fact, are precisely identical and segment D-E varies only in one respect as appears hereinbelow.

To make clear the terms of reference, each of the stages proper of the cascade have been designated by Roman numerals, viz., I, II, III and IV, which are intended to designate the stages apart from the inter-stage coupling networks, as will more fully appear as this description proceeds. For the most part, only segment B-C of the circuitry, the distinctive features of segment D-E, and non-repetitive aspects of the diagram will be described in detail. To facilitate correlation between corresponding circuit components ot the various segments, a consistent system of reference designation has been employed using like Arabic numerals for like parts with Roman numeral suffixes appropriately applied to indicate the stage in which a particular component occurs.

tages I, II, Ill and IV, consist of respective current paths connected in parallel between a source of potential, represented in the diagram by conductor 1!) connected to the negative terminal of a battery 12 and a return line, reference or ground potential represented by a grounded conductor 14.

Taking Stage I as an example, the current path consists of a resistive impedance made up of a pair of seriesconnected resistors Il -I and R 1 connected in series with a bistable four layer diode S and a diode rectifier D I. Diode D l is polarized to offer low impedance to current ilow through the path when bistable diode S is conducting. In its reverse direction diode D -I otters high load impedance to pulses provided, in a manner hereinafter described, for switching the condition of the bistable component. Stage I is coupled in cascade to the succeeding stage, ll, by means of a coupling network having two branches. Gne branch consists of a diode rectifier D 4 and capacitor C -l connecting a point 16-1 between resistors R -I and R l of the preceding stage, I, to a point l8-II between the bistable diode 8-H and resistors R II and R E of the succeeding stage, II. The other branch of the coupling network consists of diode D 4 and capacitor C2-I connected in series from a point, 184, between the bistable diode S; and resistiveimpedance R l, R 4 of Stage I and a point, Zll-II, between the bistable diode S and diode rectifier D -II of Stage II.

The two coupling network branches are interconnected by a resistor R I, connecting a point, 224i, between diode 13 -1 and capacitor C I to point l8-l between the bistable diode and resistive impedance of Stage I, and by an additional resistor R41 connecting a point, 24-L between diode ID -I and capacitor (3 -1 of the second branch to point ill-II between the bistable diode and resistive impedance of Stage II.

Throughout the stages, resistors R and R preferably are of substantially equal magnitude and R of greater magnitude than either R or R individually for reasons which will appear presently.

Segment A-B of the schematic diagram may be regarded as a hypothetical stage inasmuch as it includes a switch S in a position occupied in Stages I to IV by a bistable diode S, and diode rectifier D With this exception segment A-B duplicates segment B-C of the diagram, already described.

Switch S and the hypothetical stage in which it is located is included to represent a pulse-source and facilitates description of the functioning of the circuit. In its open position, switch S epresents a bistable element in non-conducting condition; in its closed position switch S represents a bistable element in conducting condition. Opening and closing of switch S effectively generates will become l8 volts.

. 3 1 input pulses for operating the circuit as would ordinarily be applied at terminal 26.

A description of the operation of the circuit to the extent thus 'far described will facilitate explanation and understanding of the remainder. As previously mentioned input pulses to terminal 26 can be simlated by opening and closing of switch S Assuming that all four stages, I to IV, inclusive, are conductive and switch S is closed, upon opening of the switch there is no change in condition in any of the stages. When switch S is closed again, bistable diode becomes non-conductive. Upon re-opening of switch S there again is no change in the condition of any .of the stages but upon re-closing the switch, bistable diode S becomes conduc tive, and at the same time, bistable diode S becomes non-conductive. Thus, the circuit responds to alternate pulses, specifically, switching of one bistable element from conductive to non-conductive condition does not efiect the succeeding bistable element which changes condition only when the preceding'bistable element switches from a non-conductive to a conductive state.

The manner in which the circuit carries out this function is as follows. With switch S open, the upper tential drop through diode rectifier D -I and bistable diode S The left-hand plate of capacitor C is charged to the same potential as the lower plate of C through resistance R On closing switch S the potential at point 16 rises rapidly to a less negative potential'equal to about /2' the magnitude of the source 12, if R and R are of about the same magnitude. Thus, what is effectively a positive pulse is generated at point 16 and is transmitted through diode D and capacitor C to point 18-1. Consequently, point 18-I 'is temporarily more positive than the potential of return line 14, cuttingoff bistable diode S i.e., rendering it non-conductive.

Simultanebus1y,'with the positive surge at point 16 the potential at point 18 surges to the: magnitude of the source 12. However, this sudden potential increase does not affect the capacitor C because diode D is biased in the reverse direction by a pre-existing potential equal to the voltage; surge at 18.

To illustrate numerically the specific mode of operation of the circuitry thus far described assume that the potential of the return line 14 is zero and the magnitude of source 12 is 18 volts so that conductor 10 will have a potential of -l8 volts. Assuming further that all four stages I to IV, inclusive are initially conductive with switch S initially closed, upon opening of switch S the capacitor C becomes charged throughresistances R R and R and the potential of its upper plate current flows through diode D I and bistable diode 8;.

Since Stage I is conductive The voltage drop across diode D I will be approximately V 0.7 volt while the voltage drop across bistable diode S will be approximately 0.9 volt. (These are usual values for such devices.) The total voltage drop across diode D I' and bistable diode S will, accordingly, be approximately 1.6 volts. 'return line 14 is zero, the potential of the lower plate of capacitor C will be 1.6 volts, and the net, voltage across capacitor C will be 181.6 or 16.4 Volts.

Upon subsequent closing of switch S; the potential of point 16 becomes equal to /2 the magnitude of source Because'the potential of the 12 or,.9 volts if resistors R and R are of. equal size.

Simultaneously, diode D becomes conductive. As a 'result the potential of the upper plate of capacitor C also becomes -9 volts. However, as a result of'the inherent time lag of the capacitor C its charge does not charge for predetermined time after closure of switch S Accordingly, the lower plate of capacitor C will ing of bistable diode S to conduction.

increase by about the same amount (9 volts.) as the potential of the upper plate. Accordingly, the potential of the lower plate of capacitor C will momentarily increase from -1.6 volts to +7.4 volts. This potential which appears at terminal 18- is more positive than that of the return line and extinguishes conduction of bistable diode S The coupling network insures that neither the immediately succeeding bistable element S nor any of the subsequent stages, are switched non-conductive along with bistable diode S 7 This is because the upper plate of capacitor C I before cut-off of diode S was at approximately'zero potential; Consequently, diode D I was reversed-biased by the potential surge so that the positive pulse resulting at the connection point lh-I is blocked by the diode and coupling capacitor C I thus isolating diode S The positive pulse passing through the relatively high resistance R -I is insuificient to cutoff the following bistable diode.

When switch S is re-opened, negative pulses originate at

points

16 and 18. However, both diodes D and D .are'blocked for these pulses and inasmuch as resistance R is great in comparison'to resistances R and R the negative pulse after traversing path R R R C is inadequateto switch diode S; to conduction.

Reverting now to the description of the remainder of thecircuit illustrated, it is well-known that a cascade of four binary stages is capable of 15 permutations and, therefore, will count up to 15 pulses and then re-cycle. It is also well-known that four binary stages can be arranged to function as a decade counter, re-cycling after ten pulses, by various feedback arrangements.

In accordance with the present invention this is accomplished by a feedback network having two distinct feedback paths of substantially identical configuration, one of which feeds back from the final stage to the input of Stage II and the other from the final stage to the input of Stage III.

Each feedback path consists of respective parallel combinations of a diode rectifier and resistive impedance,

1?. R and D R each coupled in series with respective capacitors C C to Stage IV between bistable diode S and resistive impedance R A conductor 28 connects the opposite terminals of parallel combination 7 D R3 to the input of Stage III, viz., point 20-III bi- Stages II and III. As a result, instead of re-cycling from 15 to O, the'circuit is placed in a condition equivalent to binary '6 (ile.,' 0110).

In order to avoid coincidence between the normal ignition pulse and the cut-off pulses fed back to Stages II and III, circuit means are provided for delaying the switch- These means take the form of a resistance R connected in series between diode D -III andcapacitors C 'III in the coupling network between Stages III and IV and a capacitor C connecting a point between R and .Cg-III to ground potential. V

While a decade counter having four binary stages'has been described by way of example, it will be appreciated that counters of higher capacity can be constructed by adding additional stages. Thus, for example, a decade counting unit can be constructed having a cycle of 10 by usingten stages with provision made after 2 pulses to re-cycle to 000001 1000. corresponding to 24.

- While there have been described what at present are believed to be the preferred embodiments of this invention, it will be obvious to those skilled in the art that various changes and modifications may be made therein without departing from the invention, and it is aimed, therefore, to cover in the appended claims all such changes and modifications as fall within the true spirit and scope of the invention.

What is claimed and desired to be secured by United States Letters Patent is:

1. A switching circuit comprising: a plurality of current paths connected in parallel between a potential source and return, each of said current paths containing a bistable circuit element having a Thyratron characteristic and distinct stable conditions of conduction and nonconduction; circuit means coupling said current paths in casca e; and logic circuit means associated With the first said circuit means responsive to the switching of the bistable diode in one of said circuit paths only from a state of non-conduction to a state of conduction for effecting switching of the bistable diode in the next succeeding current path from a state of conduction to a state of non-conduction or from a state of non-conduction to a state of conduction depending upon the initial condition of the diode in said succeeding current path.

2. A switching circuit comprising:

a plurality of current paths connected in parallel between a potential source and return, each of said current paths containing resistive impedance means,

a bistable four-layer semiconductor diode adapted to be switched between conducting and nonconducting states, and

a rectifier element connected in series in the stated sequence between said potential source and return; and

circuit means coupling said current paths in cascade; and logic circuit means associated with the first said circuit means responsive to the switching of the bistable diode in one of said circuit paths only from a state or" non-conduction to a state of conduction for efiecting switching of the bistable diode in the next succeeding current path between states of conduction and non-conduction.

3. A switching circuit comprising:

a plurality of current paths connected in parallel between a potential source and return, each of said current paths being substantially identical in configuration and containing a first and a second resistive impedance,

a bistable tour-layer semiconductor diode, and

a diode rectifier connected in series in the staged sequence between said potential source and return,

the polarity of the diode rectifier being such as to present low impedance to current flow through said path when said bistable diode is in a conductive state; and

circuit means coupling said current paths in cascade so that a change in condition of the bistable diode in one of said current paths causes a change in condition of the bistable diode in a succeeding current path onl when the change in condition in the bistable diode in said one current path is from nonconductivity to conductivity, each said coupling circuit means including a first and a second branch each including a seriesconnected diode rectifier and capacitor,

said first branch connecting a point between said first and second resistive impedances of said one current path to a point between the bistable diode and resistive impedances of the succeeding current path,

said second branch connecting a point between the bistable diode and resistive impedances of said one current path to a point between the bistable diode and diode rectitier of said succeeding current path.

4. A switching circuit according to claim 3 wherein each said coupling circuit means includes:

a resistive impedance connecting a point between the diode rectifier and the capacitor of said first branch and a point between the bistable diode and the resistive irnpedances of said one current path and an additional resistive impedance connecting a point between the diode rectifier and capacitor of the sec- 0nd branch of said circuit means to a point between the bistable diode and the resistive impedances of said succeeding current path.

5. A switching circuit comprising:

a plurality of undirectional current paths connected in parallel between a potential source and return, each of said current paths being substantially identical in configuration and containing, connected in series in the stated sequence between the potential source and return;

a pair of resistive impedances of substantially equal magnitude,

a bistable four-layer semiconductor diode having a Thyratron characteristic and distinct stable conditions of conductivity and non-conductivity,

a diode rectifier polarized to present low impedance to current flow through said path when said bistable diode is in conductive condition;

and respective coupling circuit means between each of said current paths and a succeeding current path connecting said paths in cascade, each of said circuit means consisting of a first branch containing a diode and a capacitor,

one terminal of the diode being connected between the resistive impedances of said one current path, said capacitor being connected between the other terminal of said diode rectifier and a point between the bistable diode and the pair of resistive impedances of said succeeding current path, and

a second branch containing a diode rectifier and a capacitor, one terminal or" the diode rectifier being connected to a point between the bistable diode and the pair of resistive impedances of said one current path, said capacitor being connected between the other terminal of the diode rectifier and a point between the bistable diode and diode rectifier of said succeeding current path,

a resistive impedance, of greater magnitude than either of said pair of resistive impedances, connecting a point between the diode rectifier and the capacitor of said first branch to a point between the bistable diode and pair of resistive impedances of said one current path, and

an additional resistive impedance connecting a point between the diode rectifier and the capacitor of said second branch to a point between the bistable diode and pair of resistive impedances of said succeeding current path.

d. A decade counting circuit comprising:

a plurality of unidirectional current paths, each con stituting a binary counting stage, connected in parallel between a potential source and return, each of said binary stages being substantially identical in con figuration and containing, connected in series in the staged sequence between the potential source and return,

resistive impedance means,

a diode rectifier polarized to present low impedance to current flow through said path when said bistable diode is in conductive condition,

the resistive impedance means in said binary stages consisting, in all but the final stage, of a pair of series-connected resistances of substantially equal magnitude and, in the final stage, of a single resistance of substantially said magnitude;

so as to cause the counter to re cycle after a prededetermined'number of input pulses less than the total number of possible permutations of the cascade has been applied to the input of the first stage.

7. A decade counting circuit according to claim 6 including means in the coupling circuit between the penultimate and the final binary stage to delay change in condition of the bistable diode in the final stage from noncapacitor, one terminal of the diode being connected between the series-connected resistances of one said binary stages except the final stage, said capacitor being connected between the other terminal of the diode rectifier and a point between'the bistable diode and the resistive impedance means of the respective succeeding binary stage,

e a second branch containing a diode rectifier and a capacitor, one terminal of the diode rectifier being connected to a point between the bistable diode and resistive impedance means of one of said binary stages except the final stage, said capacitor being connected between the other terminal of said diode rectifier and a point between the bistable diode'and diode rectifier of the respective succeeding binary stage,

resistive impedance of greater magnitude than said series-connected resistances individually connecting a point between the diode rectifier of said first branch to a point between the bistable of the respective succeeding binary stage;

conducting to conducting.

8. A decade counting circuit according to claim 7 wherein there are four binary stages and said feedback network consistsof two individual fedback paths, each consisting of a parallel combination of a diode and resistor connected in series with a capacitor to a point between the bistable diode and resistive impedance means of the fourth binary stage, the other side of the respective diode-resistor parallel combination being connected to respective points between the bistable diode and resistive impedance means of the second'and third binary stage.

9. A decade counting circuit according to claim 8 wherein said delay means for retarding change of condition of the bistable diode in said final binary stage from non-conductive to conductive, consists of a resistive impedance connected in series in the second branch of the coupling circuit between said third and fourth binary stage 7 and a capacitor connected in parallel with the diode rectifier in said fourth binary stage between said second branchand the return line.

References Cited by the Examiner diode and resistive impedance means of a re- 30 I V V spective one of said binary stages, except the UNITED STATES PATENTS fi stage, and 2,503,662 4/50 Flowers 328-52 X an additional resistive impedance onne ing a 2,646,534 7/53 Manley 32852;5 X

point between the diode rectifier and Capacit r 2,798,983 7/57 Warman 32843 X of said second branch to a point between the U 3,021,450 2/62 Iiu 328-43 X bistable diode and resistive impedance means 3,105,912 10/63 Johnston 32843 JOHN W. HUCKERT, Primary Examiner.

ARTHUR GAUSS, Examiner.

and a feedback network coupling the output of said final binary stage to selected preceding binary stages 40

Claims

1. A SWITCHING CIRCUIT COMPRISING: A PLURALITY OF CURRENT PATHS CONNECTED IN PARALLEL BETWEEN A POTENTIAL SOURCE AND RETURN, EACH OF SAID CURRENT PATHS CONTAINING A BISTABLE CIRCUIT ELEMENT HAVING A THYRATRON CHARACTERISTIC AND DISTANCT STABLE CONDITIONS OF CONDUCTION AND NONCONDUCTION; CIRCUIT MEANS COUPLING SAID CURRENT PATHS IN CASCADE; AND LOGIC CIRCUIT MEANS ASSOCIATED WITH THE FIRST SAID CIRCUIT MEANS RESPONSIVE TO THE SWITCHING OF THE BISTABLE DIODE IN ONE OF SAID CIRCUIT PATHS ONLY FROM A