US20250100102A1

US20250100102A1 - Wafer double-side polishing apparatus and method of evaluating the same

Info

Publication number: US20250100102A1
Application number: US18/816,134
Authority: US
Inventors: Hyung Rak LEE
Original assignee: SK Siltron Co Ltd
Current assignee: SK Siltron Co Ltd
Priority date: 2023-09-27
Filing date: 2024-08-27
Publication date: 2025-03-27
Also published as: CN119704036A; KR102752000B1

Abstract

A wafer double-side polishing apparatus is disclosed. The wafer double-side polishing apparatus includes an upper plate and a lower plate facing each other, polishing pads respectively disposed at a lower portion of the upper plate and at an upper portion of the lower plate, a first gear disposed in a central region of an upper surface of the lower plate, a second gear disposed in a peripheral region of the upper surface of the lower plate, and carriers disposed between the polishing pads while being engaged between the first gear and the second gear. The upper plate includes a plurality of slurry supply holes extending in a vertical direction. Each of the carriers includes at least one wafer accommodation hole. The sum of cross-sectional areas of the wafer accommodation holes of the carriers is 32 to 34% of the cross-sectional area of the lower plate.

Description

CROSS-REFERENCE TO RELATED PATENT APPLICATIONS

This application claims the benefit of Korean Patent Application No. 10-2023-0130523, filed on Sep. 27, 2023, which is hereby incorporated by reference as if fully set forth herein.

BACKGROUND OF THE INVENTION

Field of the Invention

The present disclosure relates to a wafer double-side polishing apparatus and a method of evaluating the same, and more particularly to a wafer double-side polishing apparatus capable of securing high flatness of a wafer after polishing of the wafer and a method of evaluating the same.

Discussion of the Related Art

A typical silicon wafer is manufactured through an ingot growth process of producing an ingot, a slicing process of slicing the ingot, thereby obtaining a wafer having a thin disc shape, a lapping process of removing, through mechanical treatment, damage remaining at the wafer due to the slicing, a polishing process of polishing the wafer to have a mirror surface, and a cleaning process of mirror-polishing the polished wafer and removing an abrasive or foreign matter attached to the wafer.
The polishing process may be divided into double-side polishing of polishing the wafer by a small thickness to remove surface defects and to make the wafer have better flatness, and final polishing of finely polishing the wafer by a thickness of about 1 μm to reduce roughness and, as such, to make the wafer have a mirror surface.
The wafer double-side polishing apparatus includes a lower plate with a pad attached to an upper surface thereof, an upper plate with a pad attached to a lower surface thereof, and a carrier installed between the upper plate and the lower plate and configured to support a wafer mounted thereon.
The wafer is loaded in a hole formed in the carrier. The upper plate moves downwards, thereby applying a pressure to the wafer. In this state, the upper plate and the lower plate rotate at a predetermined rotation ratio under the condition that slurry is supplied and, as such, may perform chemical-mechanical polishing.
The flatness of the polished wafer may be varied in accordance with the kind and distribution of the supplied slurry, the kind of the pads, etc.
In addition, the supply and distribution of the slurry may influence shape variation of the wafer as well as flatness of the wafer. For this reason, when the slurry is non-uniformly supplied, settlement of polishing by-products may be increased in a thin area of a slurry layer, thereby causing non-uniformity of wafer polishing by the polishing pads. As a result, it may be impossible to obtain a wafer having high flatness.
In order to solve such a problem, a scheme of supplying slurry at the lower plate may be taken into consideration. In this case, slurry is pushed upwards through a pressurization method and, as such, a wafer, which is being polished, may be pushed upwards, thereby resulting in non-uniform polishing of the wafer.

SUMMARY OF THE INVENTION

Accordingly, the present disclosure is directed to a wafer double-side polishing apparatus and a method of evaluating the same that substantially obviate one or more problems due to limitations and disadvantages of the related art.
It is an object of the present disclosure to provide a wafer double-side polishing apparatus capable of securing high flatness of a wafer after polishing of the wafer and a method of evaluating the same.
Objects of the present disclosure are not limited to the above-described object, and other objects of the present disclosure not yet described will be more clearly understood by those skilled in the art from the following detailed description.
To achieve these objects and other advantages and in accordance with the purpose of the disclosure, as embodied and broadly described herein, a wafer double-side polishing apparatus includes an upper plate and a lower plate facing each other, polishing pads respectively disposed at a lower portion of the upper plate and at an upper portion of the lower plate, a first gear disposed in a central region of an upper surface of the lower plate and a second gear disposed in a peripheral region of the upper surface of the lower plate, and carriers disposed between the polishing pads while being engaged between the first gear and the second gear, wherein the upper plate includes a plurality of slurry supply holes extending in a vertical direction, wherein each of the carriers includes at least one wafer accommodation hole, and wherein a sum of cross-sectional areas of the wafer accommodation holes of the carriers is 32 to 34% of a cross-sectional area of the lower plate.
The carriers may have a same shape, and the at least one wafer accommodation hole of each carrier may include three wafer accommodation holes. The carriers may include five carriers engaged between the first gear and the second gear.
The carriers may have a same shape, and the at least one wafer accommodation hole of each carrier may include four wafer accommodation holes. The carriers may include four carriers engaged between the first gear and the second gear.
Slurry supplied to the slurry supply holes may include silica particles having a size of 40 to 100 nanometers.
A pH of the slurry may be 11 or more.
A particle concentration of the slurry may be 1 to 1.5%.
Each of the polishing pads may have a hardness of 83 to 93 HRC.
Each of the polishing pads may have a compressiveness of 0.7 to 3.1%.
Wafers may be accommodated in the wafer accommodation holes of the carriers, respectively, and the lower plate and the upper plate may be pressurized by force of 100 to 160 g/cm².
In another aspect of the present disclosure, a wafer double-side polishing apparatus evaluation method includes: preparing a wafer double-side polishing apparatus including an upper plate and a lower plate facing each other, polishing pads respectively disposed at a lower portion of the upper plate and at an upper portion of the lower plate, a first gear disposed in a central region of an upper surface of the lower plate, a second gear disposed in a peripheral region of the upper surface of the lower plate, and carriers disposed between the polishing pads while being engaged between the first gear and the second gear, the upper plate including a plurality of slurry supply holes extending in a vertical direction, each of the carriers including at least one wafer accommodation hole; accommodating wafers in the wafer accommodation holes of the carriers, respectively, supplying slurry through the slurry supply holes, and polishing the wafers by friction thereof with the polishing pads disposed thereover and thereunder; and comparing a B/A value with a global backside ideal plane range (GBIR), wherein “A” is a cross-sectional area of the lower plate, “B” is a sum of cross-sectional areas of the wafer accommodation holes formed at the carriers, and “GBIR” represents a height difference between a highest portion and a lowest portion of a surface of each wafer.
Carriers each formed with wafer accommodation holes and lower plates configured to support corresponding ones of the carriers and to satisfy different B/A values of 25%, 31%, 33%, and 35%, together with the corresponding carriers, respectively, may be prepared.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the disclosure and along with the description serve to explain the principle of the disclosure. In the drawings:

FIG. 1 is a side view of a wafer double-side polishing apparatus according to an embodiment of the present disclosure;

FIG. 2 is a perspective view corresponding to FIG. 1 ;

FIGS. 3 and 4 which are plan views showing embodiments of disposition of carriers and wafers on a lower plate of FIG. 1 ;

FIG. 5 shows a method of evaluating a wafer double-side polishing apparatus in accordance with an embodiment of the present disclosure; and

FIG. 6 shows flatness of a wafer having a diameter of 300 mm when the ratio of the sum of cross-sectional areas of wafer accommodation holes in a horizontal direction to the cross-sectional area of the lower plate is varied.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, embodiments will be described in detail with reference to the annexed drawings for better understanding.
However, it will be apparent that the embodiments may be modified in various ways and the scope of the embodiments should not be construed as being limited to the following description. Thus, the embodiments are provided to ensure more perfect comprehension of the embodiments by one of ordinary skill in the art.
In addition, it will be understood that relative terms used hereinafter such as “first”, “second”, “on/above/over” and “under/below/beneath” may be construed only to distinguish one element from another element without necessarily requiring or involving a certain physical or logical relation or sequence between the elements.
A wafer double-side polishing apparatus according to the present disclosure is intended to provide a wafer having high flatness through a double-side polishing process performed by adjusting a ratio between a horizontal cross-section of wafer accommodation holes and a cross-section of a lower plate, thereby adjusting a ratio between a slurry supply area and the entire area of a wafer (an area in which supply of slurry is blocked).
FIG. 1 is a side view of a wafer double-side polishing apparatus according to an embodiment of the present disclosure. FIG. 2 is a perspective view corresponding to FIG. 1 .
Referring to FIGS. 1 and 2 , a wafer double-side polishing apparatus 1000 includes a lower plate 100 and an upper plate 200 disposed to face each other. Polishing pads 120 and 220 may be disposed at an upper portion of the lower plate 100 and a lower portion of the upper plate 200, respectively.
A first gear 400, which is a sun gear, may be provided in a central region of an upper surface of the lower plate 100, and a second gear 500, which is an internal gear, may be provided in a peripheral region of the upper surface of the lower plate 100.
A plurality of carriers 300 having the same shape may be provided between the polishing pads 120 and 220. The carriers 300 may be engaged between the first gear 400 and the second gear 500.
A plurality of slurry supply holes 210 may be provided at the upper plate 200. At least one wafer accommodation hole, preferably, a plurality of wafer accommodation holes, may be disposed at each carrier 300.
Slurry, which is supplied through the slurry supply holes 210 of the upper plate 200, may be a liquid with fine particles suspended therein. For example, the particles may include silica particles, and the silica particles may have a size of 40 to 100 nanometers. Here, when it is assumed that the particles have a circular shape, the above-described size means a diameter, and when it is assumed that the particles have a hexahedral shape, the above-described size means a length of each side.
In addition, a total pH of the slurry may be 11 or more and, as such, the slurry may exhibit a basic property. The concentration of particles in the slurry may be 1 to 1.5%.
In the wafer double-side polishing apparatus according to the present disclosure, the sum of cross-sectional areas of the wafer accommodation holes in a horizontal direction may be 32 to 34% of the cross-sectional area of the lower plate. That is, referring to FIGS. 3 and 4 which are plan views showing embodiments of disposition of the carriers and the wafers on the lower plate of FIG. 1 , it may be seen that, when the cross-sectional area of the lower plate is A, and the sum of the cross-sectional areas of the wafer accommodation holes formed at the plurality of carriers to accommodate wafers is B, the ratio of B to A may be 0.32 to 0.34 (B/A=0.32 to 0.34).
Each carrier 300 included in the wafer double-side polishing apparatus 1000 shown in FIG. 2 includes one wafer accommodation hole and five slurry holes respectively having different sizes. In the embodiments shown in FIGS. 3 and 4 , a plurality of wafer accommodation holes is provided at each of a plurality of carriers. In detail, in the embodiment of FIG. 3 , five carriers are disposed on the lower plate, and three wafer accommodation holes are provided at each carrier. On the other hand, in the embodiment of FIG. 4 , four carriers are disposed on the lower plate, and four wafer accommodation holes are provided at each carrier.
Even when the number of carriers provided on the lower plate and the number of wafer accommodation holes formed at each carrier are varied, the sum of the cross-sectional areas of the wafer accommodation holes in the horizontal direction may be fixed to 32 to 34% of the cross-sectional area of the lower plate.
FIG. 5 shows a method of evaluating a wafer double-side polishing apparatus in accordance with an embodiment of the present disclosure. This method is a method of evaluating the wafer double-side polishing apparatus according to the above-described embodiment.
In the wafer double-side polishing apparatus evaluation method according to this embodiment, the wafer double side polishing apparatus shown in FIGS. 1 and 2 is evaluated.
First, a wafer double-side polishing apparatus is prepared. In detail, an upper plate and a lower plate facing each other, polishing pads to be disposed at a lower portion of the upper plate and an upper portion of the lower plate, respectively, a first gear to be disposed in a central region of an upper surface of the lower plate, a second gear to be disposed in a peripheral region of the upper surface of the lower plate, and a carrier to be disposed between the polishing pads while being engaged with the first gear and the second gear are prepared (S110).
In this case, the carrier may be provided in plural, and the plural carriers may have the same shape.
In addition, each carrier may include at least one wafer accommodation hole configured to accommodate a wafer therein. In addition, a plurality of slurry supply holes extending in a vertical direction may be provided at the upper plate.
In this case, the above-described wafer double-side polishing apparatus may be provided in plural and, as such, a plurality of wafer double-side polishing apparatuses respectively having different B/A values may be prepared.
Subsequently, wafers are subjected to double-side polishing using the above-described wafer double-side polishing apparatuses (S120). In detail, the wafers respectively accommodated in the wafer insertion holes of the carriers are polished in accordance with friction thereof with the polishing pads disposed thereover and thereunder. In this case, opposite surfaces of each wafer may be chemically and mechanically polished in accordance with action of slurry supplied through the slurry supply holes. That is, irregularities, curvatures, or the like formed at portions of the wafer surfaces after a thin film deposition process or an etching process may be removed through mechanical friction between the wafer surfaces and the polishing pads, and the slurry supplied during the mechanical friction may chemically polish the surfaces of the wafer.
For the polishing pads, a product having a hardness of 83 to 93 Hardness Rockwell C-scale (HRC) may be used. In addition, the polishing pads may have a compressiveness of 0.7 to 3.1%. That is, when it is assumed that each polishing pad has a thickness of 100 before pressurization of the upper plate and the lower plate, the polishing pad may be compressed to a thickness of 96.9 to 99.3 after pressurization. In this case, the upper plate and the lower plate may be pressurized by force of 100 to 160 g/cm².
Thereafter, each B/A value is compared with a global backside ideal plane range (GBIR) (S130).
Here, “A” is the cross-sectional area of the lower plate, and “B” is the sum of the cross-sectional areas of the wafer accommodation holes formed at the plurality of carriers. In addition, “GBIR” is an indicator representing flatness of the wafer after double-side polishing, and, in detail, represents a height difference between a highest portion and a lowest portion of the surface (upper surface or lower surface) of the wafer.
FIG. 6 shows flatness of a wafer having a diameter of 300 mm when the ratio of the sum of the cross-sectional areas of the wafer accommodation holes in the horizontal direction to the cross-sectional area of the lower plate is varied, that is, results of comparison of the B/A value and the global backside ideal plane range (GBIR) in step S130.
FIG. 6 shows global backside ideal plane ranges (GBIRs) and thickness profiles of wafers when the ratio of the sum B of the cross-sectional areas of the wafer accommodation holes in the horizontal direction to the cross-sectional area A of the lower plate is varied to be 25%, 31%, 33%, and 35%, respectively.
When the B/A value is varied to be 25%, 31%, 33%, and 35%, the GBIR may be varied to be 182 nm, 110 nm, 78 nm, and 89 nm, respectively.
In addition, as shown in FIG. 6 , the thickness profile of the wafer may be upwardly convex when the B/A value is 25% and 31%, may be downwardly concave when the B/A value is 35%, and may be close to a flat shape when the B/A value is 33%. Accordingly, when the B/A value is 33%, it may be possible to enhance flatness of the wafer without varying a polishing time or a supply amount of slurry.
Accordingly, in the wafer double side polishing apparatus evaluation method according to the present disclosure, it was evaluated that, when the B/A value is 32 to 34%, a wafer machined to have a flat surface may be obtained (S140), and the double-side polishing apparatus associated with such a wafer was determined as an optimum example.
That is, slurry may flow downwards from the slurry supply holes of the upper plate in a region other than the wafer accommodation hole in which the wafer is disposed. That is, the slurry performing the above-described chemical polishing action may flow downwards from the surface of the wafer being polished to a space beside the wafer. In this case, the ratio of the space beside the wafer, to which the slurry flows downwards, to the cross-sectional area A of the lower plate may be represented by (100−B)/A. Accordingly, when (100−B)/A is small, that is, the ratio of B/A is great, supply of the slurry may be blocked by the surface of the wafer and, as such, may be reduced. In this case, the wafer may be polished without presence of the slurry and, as such, a central portion thereof may be excessively polished. In a converse case, the slurry may be excessively supplied and, as such, the central portion of the wafer may be insufficiently polished.
That is, when the B/A value is 25%, the wafer, in particular, the central portion thereof, may be insufficiently polished, as shown in FIG. 6 . Although not shown, when the B/A value is more than 41%, supply of the slurry may be reduced and, as such, the wafer, in particular, the central portion thereof, may be excessively polished.
When the B/A value is 32 to 34%, it may be possible to vary the number of carriers or the number of wafer accommodation holes in each carrier in the wafer double-side polishing apparatus, as shown in FIGS. 3 and 4 , without varying the sizes of the upper and lower plates.
As apparent from the above description, in the wafer double-side polishing apparatus and the evaluation method thereof according to the present disclosure, it may be possible to enhance flatness of the wafer subjected to double-side polishing without varying a polishing time or a supply amount of slurry, by setting the ratio of the sum B of the cross-sectional areas of the wafer accommodation holes in the horizontal direction to the cross-sectional area A of the lower plate to 32 to 34%.
Although the foregoing description has been given mainly in conjunction with embodiments, these embodiments are only illustrative without limiting the disclosure. Those skilled in the art to which the present disclosure pertains can appreciate that various modifications and applications illustrated in the foregoing description may be possible without changing essential characteristics of the embodiments. Therefore, the above-described embodiments should be understood as exemplary rather than limiting in all aspects. In addition, the scope of the present disclosure should also be interpreted by the claims below rather than the above detailed description. All modifications or alterations as would be derived from the equivalent concept intended to be included within the scope of the present disclosure should also be interpreted as falling within the scope of the disclosure.

Claims

What is claimed is:

1. A wafer double-side polishing apparatus comprising:

an upper plate and a lower plate facing each other;

polishing pads respectively disposed at a lower portion of the upper plate and at an upper portion of the lower plate;

a first gear disposed in a central region of an upper surface of the lower plate and a second gear disposed in a peripheral region of the upper surface of the lower plate; and

carriers disposed between the polishing pads while being engaged between the first gear and the second gear,

wherein the upper plate comprises a plurality of slurry supply holes extending in a vertical direction,

wherein each of the carriers comprises at least one wafer accommodation hole, and

wherein a sum of cross-sectional areas of the wafer accommodation holes of the carriers is 32 to 34% of a cross-sectional area of the lower plate.

2. The wafer double-side polishing apparatus according to claim 1, wherein:

the carriers have a same shape, and the at least one wafer accommodation hole of each carrier comprises three wafer accommodation holes; and

the carriers comprise five carriers engaged between the first gear and the second gear.

3. The wafer double-side polishing apparatus according to claim 1, wherein:

the carriers have a same shape, and the at least one wafer accommodation hole of each carrier comprises four wafer accommodation holes; and

the carriers comprise four carriers engaged between the first gear and the second gear.

4. The wafer double-side polishing apparatus according to claim 1, wherein slurry supplied to the slurry supply holes comprises silica particles having a size of 40 to 100 nanometers.

5. The wafer double-side polishing apparatus according to claim 2, wherein slurry supplied to the slurry supply holes comprises silica particles having a size of 40 to 100 nanometers.

6. The wafer double-side polishing apparatus according to claim 3, wherein slurry supplied to the slurry supply holes comprises silica particles having a size of 40 to 100 nanometers.

7. The wafer double-side polishing apparatus according to claim 4, wherein a pH of the slurry is 11 or more.

8. The wafer double-side polishing apparatus according to claim 4, wherein a particle concentration of the slurry is 1 to 1.5%.

9. The wafer double-side polishing apparatus according to claim 4, wherein each of the polishing pads has a hardness of 83 to 93 HRC.

10. The wafer double-side polishing apparatus according to claim 4, wherein each of the polishing pads has a compressiveness of 0.7 to 3.1%.

11. The wafer double-side polishing apparatus according to claim 1, wherein wafers are accommodated in the wafer accommodation holes of the carriers, respectively, and the lower plate and the upper plate are pressurized by force of 100 to 160 g/cm².

12. The wafer double-side polishing apparatus according to claim 2, wherein wafers are accommodated in the wafer accommodation holes of the carriers, respectively, and the lower plate and the upper plate are pressurized by force of 100 to 160 g/cm².

13. The wafer double-side polishing apparatus according to claim 3, wherein wafers are accommodated in the wafer accommodation holes of the carriers, respectively, and the lower plate and the upper plate are pressurized by force of 100 to 160 g/cm².

14. A wafer double-side polishing apparatus evaluation method comprising:

preparing a wafer double-side polishing apparatus comprising an upper plate and a lower plate facing each other, polishing pads respectively disposed at a lower portion of the upper plate and at an upper portion of the lower plate, a first gear disposed in a central region of an upper surface of the lower plate, a second gear disposed in a peripheral region of the upper surface of the lower plate, and carriers disposed between the polishing pads while being engaged between the first gear and the second gear, the upper plate comprising a plurality of slurry supply holes extending in a vertical direction, each of the carriers comprising at least one wafer accommodation hole;

accommodating wafers in the wafer accommodation holes of the carriers, respectively, supplying slurry through the slurry supply holes, and polishing the wafers by friction thereof with the polishing pads disposed pads disposed thereover and thereunder; and

comparing a B/A value with a global backside ideal plane range (GBIR),

wherein “A” is a cross-sectional area of the lower plate, “B” is a sum of cross-sectional areas of the wafer accommodation holes formed at the carriers, and “GBIR” represents a height difference between a highest portion and a lowest portion of a surface of each wafer.

15. The wafer double-side polishing apparatus evaluation method according to claim 14, wherein carriers each formed with wafer accommodation holes and lower plates configured to support corresponding ones of the carriers and to satisfy different B/A values of 25%, 31%, 33%, and 35%, together with the corresponding carriers, respectively, are prepared.

16. The wafer double-side polishing apparatus evaluation method according to claim 14, wherein:

carriers having a same shape, each of the carriers having three wafer accommodation holes, are prepared; and

the carriers comprise five carries engaged between the first gear and the second gear.

17. The wafer double-side polishing apparatus evaluation method according to claim 14, wherein:

carriers having a same shape, each of the carriers having four wafer accommodation holes, are prepared; and

the carriers comprise four carries engaged between the first gear and the second gear.

18. The wafer double-side polishing apparatus evaluation method according to claim 14, wherein, in the polishing, the lower plate and the upper plate are pressurized by force of 100 to 160 g/cm².

19. The wafer double-side polishing apparatus evaluation method according to claim 14, wherein, in the polishing, the slurry supplied to the slurry supply holes comprises silica particles having a size of 40 to 100 nanometers, a pH of the slurry is 11 or more, and a particle concentration of the slurry is 1 to 1.5%.

20. The wafer double-side polishing apparatus evaluation method according to claim 14, wherein polishing pads each having a hardness of 83 to 93 HRC and a compressiveness of 0.7 to 3.1% are prepared.