US20220392747A1 - Atomic layer etching and smoothing of refractory metals and other high surface binding energy materials - Google Patents
Atomic layer etching and smoothing of refractory metals and other high surface binding energy materials Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/3244—Gas supply means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32715—Workpiece holder
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32917—Plasma diagnostics
- H01J37/32926—Software, data control or modelling
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- H10P50/267—
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- H10P50/283—
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
- H01J2237/32—Processing objects by plasma generation
- H01J2237/33—Processing objects by plasma generation characterised by the type of processing
- H01J2237/334—Etching
- H01J2237/3341—Reactive etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
Definitions
- ALE Atomic Layer Etch
- Etch processes that yield smooth, in at least some cases extremely smooth, etch front and line edge for refractory metals and other high surface binding energy materials, and in some cases improved selectivity to surrounding materials, are disclosed.
- Certain Atomic Layer Etch (ALE) processes have been demonstrated on refractory metals such as Mo, Ta and Ru, and could be used to process a variety of materials composed of grains. While ALE can be used for directional pattern transfer to produce smooth metal lines, it can also be applied for other purposes. For example, it is desired for both reliability and device electrical performance, to provide conformal liners (e.g., diffusion barrier or adhesion promoting layer) that are continuous, smooth and atomically thin. If, for example, an as-deposited liner is thicker and/or rougher than desired as deposited, ALE etchback may be utilized to appropriately thin and smooth the liner at the same time, thereby providing the desired result.
- conformal liners e.g., diffusion barrier or adhesion promoting layer
- a method of etching a refractory metal or other high surface binding energy (high EO) material on a substrate is provided.
- the method can include providing a substrate comprising an exposed refractory metal/high EO surface, exposing the refractory metal/high EO surface to a modification gas to modify the surface and form a modified refractory metal/high EO surface, and exposing the modified refractory metal/high EO surface to an energetic particle to preferentially remove the modified refractory metal/high EO surface relative to an underlying unmodified refractory metal/high EO surface.
- the exposed refractory metal/high EO surface after removing the modified refractory metal/high EO surface is as smooth or smoother than the substrate surface before exposing the substrate surface to the modification gas.
- the smoothness of the refractory metal/high EO surface may be maintained or increased by the method, for example by more than 10% RMS, more than 20%, more than 30%, more than 40%, more than 50%, more than 60%, more than 70%, 75% or more, more than 80%, or more than 90% RMS, on the order of an order of magnitude increase in smoothness.
- the refractory metal/high EO surface may be a refractory metal selected from the group of Nb, Mo, Ta, W, Re, Ru, Rh, Os, Ir, Ti, V, Cr, Zr and Hf.
- the refractory metal may be selected from the group of Mo, Ta and Ru.
- the modification gas may include O 2 , or another oxygen-containing gas.
- the modification gas may include Cl 2 , or another chlorine-containing gas.
- the modification gas may include a mixture of O 2 , or another oxygen-containing gas and Cl 2 , or another chlorine containing gas.
- the energetic particle may be an inert ion plasma, such as an Ar plasma.
- a modification gas mixture selective to refractory metal may be used.
- the refractory metal/high EO may be a material selected from the group of oxides such as Al 2 O 3 , In 2 O 3 , MgO, SnO, Ta 2 O 5 , TiO 2 and ZrO 2 ; carbides such as BC, SiC and WC; nitrides such as BN, TaN, TiN; sulfides such as ZnS and MoS 2 ; and superconductors such as YBCO.
- oxides such as Al 2 O 3 , In 2 O 3 , MgO, SnO, Ta 2 O 5 , TiO 2 and ZrO 2
- carbides such as BC, SiC and WC
- nitrides such as BN, TaN, TiN
- sulfides such as ZnS and MoS 2
- superconductors such as YBCO.
- the substrate surface may be smoothened for semiconductor or non-semiconductor processing applications.
- the apparatus may include a process chamber comprising a showerhead and a substrate support for holding the substrate having a material, a plasma generator, and a controller having at least one processor and a memory.
- the at least one processor and the memory may be communicatively connected with one another, the at least one processor may be at least operatively connected with flow-control hardware, and the memory may store machine-readable instructions for etching a refractory metal/high EO on a substrate, the instructions comprising: providing a substrate comprising an exposed refractory metal/high EO surface; exposing the refractory metal/high EO surface to a modification gas to modify the surface and form a modified refractory metal/high EO surface; and exposing the modified refractory metal surface to an energetic particle to preferentially remove the modified refractory metal/high EO surface relative to an underlying unmodified refractory metal/high EO surface.
- the exposed refractory metal/high EO surface after removing the
- FIG. 1 shows two example schematic illustrations of an ALE cycle in accordance with embodiments of this disclosure.
- FIG. 2 depicts SEM images of, on the left, an incoming substrate surface with visible damage, roughness, or grain boundaries that are all reduced by ALE, on the right, in accordance with an embodiment of this disclosure.
- FIGS. 3 A-B present data showing a comparison of the ALE results obtained for Ru smoothing in accordance with an embodiment of this disclosure compared to other etch processes and chemistries.
- FIG. 4 depicts SEM images showing the high selectivity of an ALE process in accordance with an embodiment of this disclosure that has been demonstrated with Mo utilizing an O 2 /Cl 2 modification chemistry.
- FIG. 5 shows a plot of data demonstrating that Cl 2 and O 2 modification mixture chemistries show 10-20 times faster etch rate of Mo blanket films compared to Cl 2 only or O 2 -only modification chemistries in accordance with embodiments of this disclosure.
- FIG. 6 depicts a flow chart of a method of etching a refractory metal or other high E O material on a substrate in accordance with embodiments this disclosure.
- FIG. 7 schematically shows a cross-sectional view of an inductively coupled plasma etching apparatus appropriate for implementing certain embodiments herein.
- FIG. 8 depicts a semiconductor process cluster architecture with various modules that is appropriate for implementing certain embodiments herein.
- Etching processes often involve exposing a material to be etched to a combination of etching gases to remove the material. However, such removal may in some cases etch more than desired, or result in an undesirable feature profile. As feature sizes shrink, there is a growing need for atomic scale processing.
- RIE reactive ion etch
- Etch processes that yield smooth, in at least some cases extremely smooth (e.g., up to 50% or more, 60% or more, 70% or more, 75% or more, 80% or more, or 90% or more root mean square (RMS) smoother than pre-etch surface roughness) etch front and line edge for refractory metals and other high surface binding energy materials, and in some cases improved selectivity to surrounding materials, are disclosed.
- Certain Atomic Layer Etch (ALE) processes have been demonstrated on refractory metals such as Mo, Ta and Ru, and could be used to process a variety of materials composed of grains. While ALE can be used for directional pattern transfer to produce smooth metal lines, it can also be applied for other purposes.
- conformal liners e.g., diffusion barrier or adhesion promoting layer
- ALE etchback may be utilized to appropriately thin and smooth the liner at the same time, thereby providing the desired result.
- ALE is a multi-step process used in advanced semiconductor manufacturing (e.g. technology node ⁇ 10 nm) for the blanket removal or pattern-definition etching of ultra-thin layers of material with atomic scale in-depth resolution and control.
- ALE is a technique that removes thin layers of material using sequential self-limiting reactions. Examples of atomic layer etch techniques are described in U.S. Pat. Nos. 8,883,028 and 8,808,561, which are herein incorporated by reference for purposes of describing example atomic layer etch and etching techniques.
- an ALE cycle is the minimum set of operations used to perform an etch process one time, such as etching a monolayer.
- the result of one cycle is that at least some of a film layer on a substrate surface is etched.
- an ALE cycle includes a modification operation to form a modified layer, followed by a removal operation to remove or etch only this modified layer.
- the cycle may include certain ancillary operations such as sweeping, or purging, one of the reactants or byproducts.
- a cycle contains one instance of a unique sequence of operations.
- an ALE cycle may include the following operations: (i) delivery of a modification gas, (ii) purging of the reactant gas from the chamber, (iii) delivery of a removal gas and an optional plasma, and (iv) purging of the chamber.
- etching may be performed nonconformally, including such that the resulting surface may be smoother, including much smoother, than the starting surface.
- FIG. 1 shows two example schematic illustrations of an ALE cycle.
- Diagrams 171 a - 171 e show a generic ALE cycle.
- the substrate is provided.
- the surface of the substrate is modified.
- the next step is prepared.
- the modified layer is being etched.
- the modified layer is removed.
- diagrams 172 a - 172 e show an example of an ALE cycle for etching a refractory metal film.
- an exposed Ru film surface on a substrate is provided, which includes many Ru metal atoms.
- modification gas for example including oxygen gas
- oxygen gas introduced to the substrate modifies the Ru metal surface of the substrate.
- the schematic in 172 b shows that some modification gas is adsorbed onto the surface of the substrate as an example.
- oxygen is depicted in FIG. 1
- a suitable oxygen-containing compound that forms volatile species with the metal atom may be used.
- chlorine or suitable chlorine-containing gas that forms volatile species with the metal atom may be used, or a combination of oxygen and chlorine gases, or suitable oxygen- and chlorine-containing gases, may be used to advantage with particular refractory metals, as further described below.
- the modification gas is purged from the chamber.
- a removal gas such as an inert gas including nitrogen, argon, neon, helium, or combinations thereof, for example argon
- a plasma is introduced with a plasma, forming argon ions (energetic particles) as indicated by the Ar + plasma species and arrows, and anisotropic ion bombardment is performed to remove the modified refractory metal surface of the substrate.
- a bias is applied to the substrate to attract ions toward it.
- the chamber is purged and the byproducts are removed.
- a cycle may only partially etch about 0.1 nm to about 50 nm of material, or between about 0.1 nm and about 20 nm of material, or between about 0.1 nm and about 2 nm of material, or between about 0.1 nm and about 5 nm of material, or between about 0.2 nm and about 50 nm of material, or between about 0.2 nm and about 5 nm of material.
- the amount of material etched in a cycle may depend on the purpose of etching in a self-limiting manner.
- a cycle of ALE may remove less than a monolayer of material.
- ALE process conditions such as chamber pressure, substrate temperature, plasma power, frequency, and type, and bias power, depend on the material to be etched, the composition of the gases used to modify the material to be etched, the material underlying the material to be etched, and the composition of gases used to remove the modified material.
- ALE involves splitting the etch process into two (or more) separate operations: modification (operation A) and removal (operation B).
- modification operation modifies the surface layer so that it can be removed easily during the removal operation.
- a thin layer of material is removed per cycle, where a cycle includes modification and removal, and the cycle can be repeated until the desired depth is reached.
- Synergy means that favorable etching occurs due to interaction of operations A and B.
- operations A and B are separated in either space or time.
- ALE synergy is calculated by:
- EPC etch per cycle
- a and B are contributions to the EPC from the stand-alone modification and removal operations, respectfully, measured as reference points by performing these operations independently.
- Synergy is a test that captures many aspects of ALE behavior, and is well-suited to compare different ALE conditions or systems. It is an underlying mechanism for why etching in operation B stops after reactants from operation A are consumed. It is therefore responsible for the self-limiting behavior in ALE benefits such as aspect ratio independence, uniformity, smoothness, and selectivity.
- Disclosed embodiments are structured to achieve an ALE process with high synergy—the ideal being an ALE process with synergy being 100%. This ideal may not be possible to achieve in all cases given practical considerations such as the accessible range of process conditions, wafer throughput requirements, etc. However, tolerance for synergy less than the ideal of 100% will depend on the application and the technology node, and presumably each successive technology generation will demand higher levels of ideality.
- Disclosed embodiments for designing an ALE process with high synergy is based on achieving a hierarchical relationship between energies that characterize an overall ALE process and the energy barriers that are overcome to achieve etch with synergy close to 100%.
- E O , E mod , and E des are determined by properties of the material to be etched and the reactant.
- E O is the surface binding energy of the unmodified material and is the cohesive force that keeps atoms from being removed from the surface.
- E mod (sometimes Eats) is the adsorption barrier to modify the surface and arises from the need to dissociate reactants or reorganize surface atoms.
- E des is the desorption barrier, the energy used to remove a by-product from the modified surface.
- Disclosed embodiments are suitable for performing ALE of refractory metals, including Nb, Mo, Ta, W, Re, Ru, Rh, Os, Ir, Ti, V, Cr, Zr and Hf, in particular Mo, Ta and Ru. While W has long been integrated and studied in a semiconductor processing contexts, including our recent work on tungsten ALE removal and smoothing, ALE of other refractory metals has not to date been addressed to any significant extent. Anisotropic, or directional, ALE, in particular, is shown herein to provide advantageous smoothing, including extreme smoothing, results on refractory metals not previously studied to significant extent. Other high surface binding energy materials may also benefit from ALE processing as described.
- Refractory metals are good candidates for ALE because they have high E O .
- Atomic Layer Etching: Rethinking the Art of Etch Keren J. Kanarik and Richard A. Gottscho, Journal of Physical Chemistry Letters, 9 (16), pp. 4814-4821, 2018, incorporated by reference herein for its explanation of high E O materials relating to aspects and embodiments according to this disclosure.
- high E O materials are expected to do well in terms of high synergy and self-limiting ALE.
- Excellent candidate ALE elemental materials with E O >6 eV include C, along with refractory metals, such as W, Ta, Mo, Re, and Ru, for example.
- high surface binding energy (high E O ) materials include oxides such as Al 2 O 3 , In 2 O 3 , MgO, SnO, Ta 2 O 5 , TiO 2 and ZrO 2 ; carbides such as BC, SiC and WC; nitrides such as BN, TaN, TiN; sulfides such as ZnS and MoS 2 ; and superconductors such as YBCO. While materials with high E O (e.g., refractory metals and diamond) are known for resistance to heat, wear, and etching, the analysis indicates that when such materials are etched with ALE, it is more controllable (i.e., more ideal due to higher synergy).
- high E O refractory metals and diamond
- Embodiments can be used to develop new or improved unit or integrated processes as well as standalone or clustered hardware for semiconductor processing or other applications.
- the methodology can be implemented with appropriate computer software for offline use or embedded in a process tool for recipe development, process qualification, or process control.
- non-limiting examples are provided for ALE resulting in smoothing, in some cases unexpected extreme smoothing, of molybdenum (Mo), ruthenium (Ru) and Tantalum, for example by more than 10% RMS, more than 20%, more than 30%, more than 40%, or more than 50%, more than 60%, more than 70%, as much as 75% or more, 80% or more, or 90% RMS or more, on the order of an order of magnitude increase in smoothness (decrease in roughness) from the initial film surface roughness.
- Mo molybdenum
- Ru ruthenium
- Tantalum for example by more than 10% RMS, more than 20%, more than 30%, more than 40%, or more than 50%, more than 60%, more than 70%, as much as 75% or more,
- a metal surface can be recessed while maintaining or even decreasing the roughness of the pristine surface as deposited.
- High selectivity of a metal etch to mask to liner/filling dielectric materials can be achieved by manipulation of the modification gas chemistry.
- the chemistry can be selected to react with the metal line, while not modifying surrounding materials.
- the selectivity can be achieved between different metals, and between metals and semiconductor or dielectric materials.
- FIG. 2 depicts scanning electron microscope (SEM) images of, on the left, an incoming substrate surface with visible damage, roughness, or grain boundaries that are all reduced by ALE, on the right, in accordance with an embodiment of this disclosure.
- Suitable modification gas chemistry can react to form a volatile compound. Thermal desorption temperature measurements can usefully be referenced.
- Suitable modification gases can include O 2 , Cl 2 , BCl 3 , H 2 and CF 4 .
- O 2 has been shown to be effective for etching and smoothing C, and to provide extreme smoothing of Ru
- Cl 2 has been shown to be effective for etching and smoothing of Ta and W
- mixtures of Cl 2 and O 2 have been shown to be effective for etching and smoothing of Mo.
- BCl 3 , H 2 and CF 4 are effective with the he oxides.
- high synergy for example greater than 80%, or above 90%, enhances smoothing.
- Suitable conditions can be in the range of:
- Pressure about 50-100 mT, e.g., 50, 60, 70, 80, 90, or 100 mT; Power: no bias; source power about 100-1000 W, e.g., 100, 200, 300, 400, 500, 600, 700, 800, 900 or 1000 W; Temperature: material specific, set to avoid spontaneous etching e.g., about ⁇ 70 to 150° C., e.g., ⁇ 70, ⁇ 60, ⁇ 50, ⁇ 40, ⁇ 30, ⁇ 20, ⁇ 10, 0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 110, 120, 130, 140 or 150° C.; Time: about 0.1-5 seconds, e.g., 0.1, 0.2, 0.5, 1, 2, 3, 4 or 5 s.
- Operation B (removal): Pressure: about 0.5-20 mT, e.g., 0.5, 1, 2, 5, 10, 15, 20 mT
- Power bias about 10-150V, e,g., 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 11, 120, 130, 140, or 150V bias
- source power 100-1000 W, e.g., 100, 200, 300, 400, 500, 600, 700, 800, 900 or 1000 W
- Temperature material specific, set to avoid spontaneous etching e.g., about ⁇ 70 to 150° C., e.g., ⁇ 70, ⁇ 60, ⁇ 50, ⁇ 40, ⁇ 30, ⁇ 20, ⁇ 10, 0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 110, 120, 130, 140 or 150° C.
- Time about 0.1-10 seconds, e.g., 0.1, 0.2, 0.5, 1, 2, 3, 4, 5, 6, 7, 8, 9 or 10 s, for ion flux about
- FIGS. 3 A-B show a comparison of the ALE results obtained for Ru smoothing in accordance with an embodiment of this disclosure compared to other etch processes and chemistries.
- FIG. 3 A shows a plot of etch per cycle (EPC) as a function of Ar bias for a Ru substrate for O 2 /Ar ALE as described herein, compared to other etch processes and chemistries.
- FIG. 3 B shows SEM plot of the corresponding substrate surfaces, incoming, O 2 reactive ion etch (RIE) alone, Ar sputtering alone, and O 2 /Ar ALE. Both O 2 RIE and Ar sputtering alone resulted in rougher surfaces, while O 2 /Ar ALE resulted in a much smoother surface.
- RIE reactive ion etch
- this smoothening phenomenon may be due to high-synergy self-limiting ALE processes, and there could be multiple reasons why the smoothening is so extreme.
- ALE modification operation a small radius of curvature has higher reactivity which could preferentially etch sharp corners; a corner can bond to 2 to 3 modification gas atoms instead of 0 to 1 on flat or concave surfaces.
- inert ions in the absence of reactants can smooth surfaces by amorphization of the top ⁇ 1 nm of the surface, which promotes diffusion of surface atoms.
- diffusion is hindered by strong bonds of etch species (e.g., CO attached to the crystal structure of the material to be etched.
- the resulting ultra-smooth a nanoscopic metal films would be expected to have decreased electrical resistivity due to less electron scattering at its surface, and might be able to be etched very thin while still keeping continuous to make a better barrier metal taking up less volume in a tiny 3D feature.
- electrical resistivity due to less electron scattering at its surface
- Ta ALE in which an about 33% reduction in surface roughness has been achieved (1.04 to 0.7 nm RMS).
- Still another example relates to smoothing via a ALE process that can also achieve high selectivity.
- a Cl 2 /Ar ALE process maintains the initial Mo surface roughness prior to ALE.
- FIG. 5 shows that Cl 2 and O 2 modification mixture chemistries show 10-20 times faster etch rate of Mo blanket films compared to Cl 2 only or O 2 only modification chemistries.
- a 10% O 2 /90% Cl 2 modification chemistry provided a high degree (>400:1) of etch selectivity relative to SiO 2 dielectric (compared to just 10:1 for 100% Cl 2 modification chemistry).
- Such processes may be extended to other refractory metals or to other high surface binding energy (high E O ) materials to, depending on the specific metal and process conditions, provide ultra-smoothening with high etch rate and/or high selectivity with respect to a mask material (e.g., an ashable amorphous carbon hard mask).
- the chemistry could be a suitably chosen admixture of oxidizing/chlorinating species. For example, a very high O 2 /Cl 2 ratio or even 100% O 2 could be used for Ru; and a very low O 2 :Cl 2 ratio could be used for Mo (e.g., 10% O 2 /90% Cl 2 ).
- FIG. 6 shows a flow chart of a method of etching a refractory metal or other high E O material on a substrate in accordance with this disclosure.
- a substrate having an exposed refractory metal/high E O material surface is provided.
- the refractory metal/high E O surface is exposed to a modification gas to modify the surface and form a modified refractory metal surface.
- the modified refractory metal/high E O surface is exposed to an energetic particle to preferentially remove the modified refractory metal/high E O surface relative to an underlying unmodified refractory metal/high E O surface such that the exposed refractory metal/high E O surface after removing the modified refractory metal/high E O surface is as smooth or smoother than the substrate surface before exposing the substrate surface to the modification gas.
- the modification and removal operations may be followed by purging 605 , 609 of the process chamber, and are generally repeated until the desired level of etch and/or smoothness is achieved.
- ICP reactors which, in certain embodiments, may be suitable for atomic layer etching (ALE) operations are now described.
- ICP reactors have also described in U.S. Patent Application Publication No. 2014/0170853, filed Dec. 10, 2013, and titled “IMAGE REVERSAL WITH AHM GAP FILL FOR MULTIPLE PATTERNING,” hereby incorporated by reference in its entirety and for all purposes.
- ICP reactors are described herein, in some embodiments, it should be understood that capacitively coupled plasma reactors may also be used.
- FIG. 7 schematically shows a cross-sectional view of an inductively coupled plasma etching apparatus 700 appropriate for implementing certain embodiments herein, an example of which is a KiyoTM reactor, produced by Lam Research Corp. of Fremont, Calif.
- the inductively coupled plasma apparatus 700 includes an overall process chamber 701 structurally defined by chamber walls 701 and a window 711 .
- the chamber walls 701 may be fabricated from stainless steel or aluminum.
- the window 711 may be fabricated from quartz or other dielectric material.
- An optional internal plasma grid 750 divides the overall processing chamber 701 into an upper sub-chamber 702 and a lower sub-chamber 703 .
- plasma grid 750 may be removed, thereby utilizing a chamber space made of sub-chambers 702 and 703 .
- a chuck 717 is positioned within the lower sub-chamber 703 near the bottom inner surface.
- the chuck 717 is configured to receive and hold a semiconductor wafer 719 upon which the etching and deposition processes are performed.
- the chuck 717 can be an electrostatic chuck for supporting the wafer 719 when present.
- an edge ring (not shown) surrounds chuck 717 , and has an upper surface that is approximately planar with a top surface of a wafer 719 , when present over chuck 717 .
- the chuck 717 also includes electrostatic electrodes for chucking and dechucking the wafer.
- a filter and DC clamp power supply (not shown) may be provided for this purpose.
- Other control systems for lifting the wafer 719 off the chuck 717 can also be provided.
- the chuck 717 can be electrically charged using an RF power supply 723 .
- the RF power supply 723 is connected to matching circuitry 721 through a connection 727 .
- the matching circuitry 721 is connected to the chuck 717 through a connection 725 . In this manner, the RF power supply 723 is connected to the chuck 717 .
- Elements for plasma generation include a coil 733 is positioned above window 711 .
- a coil is not used in disclosed embodiments.
- the coil 733 is fabricated from an electrically conductive material and includes at least one complete turn.
- the example of a coil 733 shown in FIG. 7 includes three turns.
- the cross-sections of coil 733 are shown with symbols, and coils having an “X” extend rotationally into the page, while coils having a “ ⁇ ” extend rotationally out of the page.
- Elements for plasma generation also include an RF power supply 741 configured to supply RF power to the coil 733 .
- the RF power supply 741 is connected to matching circuitry 739 through a connection 745 .
- the matching circuitry 739 is connected to the coil 733 through a connection 743 .
- the RF power supply 741 is connected to the coil 733 .
- An optional Faraday shield 749 is positioned between the coil 733 and the window 711 .
- the Faraday shield 749 is maintained in a spaced apart relationship relative to the coil 733 .
- the Faraday shield 749 is disposed immediately above the window 711 .
- the coil 733 , the Faraday shield 749 , and the window 711 are each configured to be substantially parallel to one another.
- the Faraday shield may prevent metal or other species from depositing on the dielectric window of the plasma chamber 701 .
- Process gases may be flowed into the processing chamber 701 through one or more main gas flow inlets 760 positioned in the upper chamber 702 and/or through one or more side gas flow inlets 770 .
- similar gas flow inlets may be used to supply process gases to a capacitively coupled plasma processing chamber.
- a vacuum pump e.g., a one or two stage mechanical dry pump and/or turbomolecular pump 740 , may be used to draw process gases out of the process chamber 701 and to maintain a pressure within the process chamber 701 .
- the pump may be used to evacuate the chamber 701 during a purge operation of ALE.
- a valve-controlled conduit may be used to fluidically connect the vacuum pump to the processing chamber 701 so as to selectively control application of the vacuum environment provided by the vacuum pump. This may be done employing a closed-loop-controlled flow restriction device, such as a throttle valve (not shown) or a pendulum valve (not shown), during operational plasma processing. Likewise, a vacuum pump and valve controlled fluidic connection to the capacitively coupled plasma processing chamber may also be employed.
- one or more process gases may be supplied through the gas flow inlets 760 and/or 770 .
- process gas may be supplied only through the main gas flow inlet 760 , or only through the side gas flow inlet 770 .
- the gas flow inlets shown in the figure may be replaced more complex gas flow inlets, one or more showerheads, for example.
- the Faraday shield 749 and/or optional grid 750 may include internal channels and holes that allow delivery of process gases to the chamber 701 . Either or both of Faraday shield 749 and optional grid 750 may serve as a showerhead for delivery of process gases.
- a liquid vaporization and delivery system may be situated upstream of the chamber 701 , such that once a liquid reactant or precursor is vaporized, the vaporized reactant or precursor is introduced into the chamber 701 via a gas flow inlet 760 and/or 770 .
- Example liquid precursors include SiCl 4 and silicon amides.
- Radio frequency power is supplied from the RF power supply 741 to the coil 733 to cause an RF current to flow through the coil 733 .
- the RF current flowing through the coil 733 generates an electromagnetic field about the coil 733 .
- the electromagnetic field generates an inductive current within the upper sub-chamber 702 .
- the physical and chemical interactions of various generated ions and radicals with the wafer 719 selectively etch features of and deposit layers on the wafer.
- the inductive current acts on the gas present in the upper sub-chamber 702 to generate an electron-ion plasma in the upper sub-chamber 702 .
- the optional internal plasma grid 750 limits the amount of hot electrons in the lower sub-chamber 703 .
- the apparatus is designed and operated such that the plasma present in the lower sub-chamber 703 is an ion-ion plasma.
- Both the upper electron-ion plasma and the lower ion-ion plasma may contain positive and negative ions, though the ion-ion plasma will have a greater ratio of negative ions to positive ions.
- Volatile etching and/or deposition byproducts may be removed from the lower sub-chamber 703 through port 722 .
- the chuck 717 disclosed herein may operate at temperatures ranging between about ⁇ 200° C. and about 600° C. or between about ⁇ 20° C. and about 250° C. for processing a substrate to etch tantalum, the chuck 717 may be set at a temperature less than about 0° C. The temperature will depend on the process operation and specific recipe and the tool used.
- Chamber 701 may be coupled to facilities (not shown) when installed in a clean room or a fabrication facility.
- Facilities include plumbing that provide processing gases, vacuum, temperature control, and environmental particle control. These facilities are coupled to chamber 701 , when installed in the target fabrication facility.
- chamber 701 may be coupled to a transfer chamber that allows robotics to transfer semiconductor wafers into and out of chamber 701 using typical automation.
- a system controller 730 (which may include one or more physical or logical controllers) controls some or all of the operations of a processing chamber.
- the system controller 730 may include one or more memory devices and one or more processors.
- the apparatus includes a switching system for controlling flow rates and durations when disclosed embodiments are performed.
- the apparatus may have a switching time of up to about 500 ms, or up to about 750 ms. Switching time may depend on the flow chemistry, recipe chosen, reactor architecture, and other factors.
- a controller 730 is part of a system, which may be part of the above-described examples.
- Such systems can comprise semiconductor processing equipment, including a processing tool or tools, chamber or chambers, a platform or platforms for processing, and/or specific processing components (a wafer pedestal, a gas flow system, etc.).
- These systems may be integrated with electronics for controlling their operation before, during, and after processing of a semiconductor wafer or substrate.
- the electronics may be referred to as the “controller,” which may control various components or subparts of the system or systems.
- the controller 730 may be programmed to control any of the processes disclosed herein, including the delivery of processing gases, temperature settings (e.g., heating and/or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positional and operation settings, wafer transfers into and out of a tool and other transfer tools and/or load locks connected to or interfaced with a specific system.
- temperature settings e.g., heating and/or cooling
- pressure settings e.g., vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positional and operation settings
- RF radio frequency
- the controller 730 may be defined as electronics having various integrated circuits, logic, memory, and/or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like.
- the integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and/or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software).
- Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files), defining operational parameters for carrying out a particular process on or for a semiconductor wafer or to a system.
- the operational parameters may, in some embodiments, be part of a recipe defined by process engineers to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and/or dies of a wafer.
- the controller 730 may be a part of or coupled to a computer that is integrated with, coupled to the system, otherwise networked to the system, or a combination thereof.
- the controller may be in the “cloud” or all or a part of a fab host computer system, which can allow for remote access of the wafer processing.
- the computer may enable remote access to the system to monitor current progress of fabrication operations, examine a history of past fabrication operations, examine trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process.
- a remote computer e.g.
- a server can provide process recipes to a system over a network, which may include a local network or the Internet.
- the remote computer may include a user interface that enables entry or programming of parameters and/or settings, which are then communicated to the system from the remote computer.
- the controller 730 receives instructions in the form of data, which specify parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the controller is configured to interface with or control.
- the controller 730 may be distributed, such as by comprising one or more discrete controllers that are networked together and working towards a common purpose, such as the processes and controls described herein.
- An example of a distributed controller for such purposes would be one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) that combine to control a process on the chamber.
- example systems may include a plasma etch chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a clean chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an ALD chamber or module, an ALE chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing systems that may be associated or used in the fabrication and/or manufacturing of semiconductor wafers.
- PVD physical vapor deposition
- CVD chemical vapor deposition
- ALD atomic layer deposition
- ALE atomic layer deposition
- FIG. 8 depicts a semiconductor process cluster architecture with various modules that interface with a vacuum transfer module 838 (VTM).
- VTM vacuum transfer module
- the arrangement of transfer modules to “transfer” wafers among multiple storage facilities and processing modules may be referred to as a “cluster tool architecture” system.
- Airlock 830 also known as a loadlock or transfer module, is shown in VTM 838 with four processing modules 820 a - 820 d , which may be individual optimized to perform various fabrication processes.
- processing modules 820 a - 820 d may be implemented to perform substrate etching, deposition, ion implantation, wafer cleaning, sputtering, and/or other semiconductor processes.
- One or more of the substrate etching processing modules may be implemented as disclosed herein, i.e., for introducing a modification gas, for introducing a removal gas, and other suitable functions in accordance with the disclosed embodiments.
- Airlock 830 and process module 820 may be referred to as “stations.” Each station has a facet 836 that interfaces the station to VTM 838 . Inside each facet, sensors 1 - 18 are used to detect the passing of wafer 826 when moved between respective stations.
- Robot 822 transfers wafer 826 between stations.
- robot 822 has one arm, and in another embodiment, robot 822 has two arms, where each arm has an end effector 824 to pick wafers such as wafer 826 for transport.
- Front-end robot 832 in atmospheric transfer module (ATM) 840 , is used to transfer wafers 826 from cassette or Front Opening Unified Pod (FOUP) 834 in Load Port Module (LPM) 842 to airlock 830 .
- Module center 828 inside process module 820 is one location for placing wafer 826 .
- Aligner 844 in ATM 840 is used to align wafers.
- the robot 822 uses end effectors 824 on each of its arms. Once the wafer 826 has been processed, it is moved by robot 822 from the process modules 820 a - 820 d to an airlock module 830 . From here, the wafer 826 may be moved by the front-end robot 832 to one of the FOUPs 834 or to the aligner 844 .
- the computer controlling the wafer movement can be local to the cluster architecture, or can be located external to the cluster architecture in the manufacturing floor, or in a remote location and connected to the cluster architecture via a network.
- a controller as described above with respect to FIG. 7 may be implemented with the tool in FIG. 8 .
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Abstract
Etching a refractory metal or other high surface binding energy material on a substrate can maintain or increase the smoothness of the metal/high EO surface, in some cases produce extreme smoothing. A substrate having an exposed refractory metal/high EO surface is provided. The refractory metal/high EO surface is exposed to a modification gas to modify the surface and form a modified refractory metal/high EO surface. The modified refractory metal/high EO surface is exposed to an energetic particle to preferentially remove the modified refractory metal/high EO surface relative to an underlying unmodified refractory metal/high EO surface such that the exposed refractory metal/high EO surface after removing the modified refractory metal/high EO surface is as smooth or smoother than the substrate surface before exposing the substrate surface to the modification gas.
Description
- An Application Data Sheet is filed concurrently with this specification as part of the present application. Each application that the present application claims benefit of or priority to as identified in the concurrently filed Application Data Sheet is incorporated by reference herein in their entireties and for all purposes.
- Semiconductor fabrication processes include etching of various materials. As feature sizes shrink, there is a growing need for atomic scale processing such as Atomic Layer Etch (ALE).
- Etch processes that yield smooth, in at least some cases extremely smooth, etch front and line edge for refractory metals and other high surface binding energy materials, and in some cases improved selectivity to surrounding materials, are disclosed. Certain Atomic Layer Etch (ALE) processes have been demonstrated on refractory metals such as Mo, Ta and Ru, and could be used to process a variety of materials composed of grains. While ALE can be used for directional pattern transfer to produce smooth metal lines, it can also be applied for other purposes. For example, it is desired for both reliability and device electrical performance, to provide conformal liners (e.g., diffusion barrier or adhesion promoting layer) that are continuous, smooth and atomically thin. If, for example, an as-deposited liner is thicker and/or rougher than desired as deposited, ALE etchback may be utilized to appropriately thin and smooth the liner at the same time, thereby providing the desired result.
- According to various embodiments, a method of etching a refractory metal or other high surface binding energy (high EO) material on a substrate is provided. The method can include providing a substrate comprising an exposed refractory metal/high EO surface, exposing the refractory metal/high EO surface to a modification gas to modify the surface and form a modified refractory metal/high EO surface, and exposing the modified refractory metal/high EO surface to an energetic particle to preferentially remove the modified refractory metal/high EO surface relative to an underlying unmodified refractory metal/high EO surface. The exposed refractory metal/high EO surface after removing the modified refractory metal/high EO surface is as smooth or smoother than the substrate surface before exposing the substrate surface to the modification gas.
- The smoothness of the refractory metal/high EO surface may be maintained or increased by the method, for example by more than 10% RMS, more than 20%, more than 30%, more than 40%, more than 50%, more than 60%, more than 70%, 75% or more, more than 80%, or more than 90% RMS, on the order of an order of magnitude increase in smoothness.
- The refractory metal/high EO surface may be a refractory metal selected from the group of Nb, Mo, Ta, W, Re, Ru, Rh, Os, Ir, Ti, V, Cr, Zr and Hf. For example, the refractory metal may be selected from the group of Mo, Ta and Ru.
- The modification gas may include O2, or another oxygen-containing gas.
- The modification gas may include Cl2, or another chlorine-containing gas.
- The modification gas may include a mixture of O2, or another oxygen-containing gas and Cl2, or another chlorine containing gas.
- The energetic particle may be an inert ion plasma, such as an Ar plasma.
- A modification gas mixture selective to refractory metal may be used.
- The refractory metal/high EO may be a material selected from the group of oxides such as Al2O3, In2O3, MgO, SnO, Ta2O5, TiO2 and ZrO2; carbides such as BC, SiC and WC; nitrides such as BN, TaN, TiN; sulfides such as ZnS and MoS2; and superconductors such as YBCO.
- The substrate surface may be smoothened for semiconductor or non-semiconductor processing applications.
- An apparatus configured for processing a substrate is also provided. The apparatus may include a process chamber comprising a showerhead and a substrate support for holding the substrate having a material, a plasma generator, and a controller having at least one processor and a memory. The at least one processor and the memory may be communicatively connected with one another, the at least one processor may be at least operatively connected with flow-control hardware, and the memory may store machine-readable instructions for etching a refractory metal/high EO on a substrate, the instructions comprising: providing a substrate comprising an exposed refractory metal/high EO surface; exposing the refractory metal/high EO surface to a modification gas to modify the surface and form a modified refractory metal/high EO surface; and exposing the modified refractory metal surface to an energetic particle to preferentially remove the modified refractory metal/high EO surface relative to an underlying unmodified refractory metal/high EO surface. The exposed refractory metal/high EO surface after removing the modified refractory metal/high EO surface is as smooth or smoother than the substrate surface before exposing the substrate surface to the modification gas.
- These and other aspects of this disclosure are further described in the detailed description that follows, including with reference to the figures.
-
FIG. 1 shows two example schematic illustrations of an ALE cycle in accordance with embodiments of this disclosure. -
FIG. 2 depicts SEM images of, on the left, an incoming substrate surface with visible damage, roughness, or grain boundaries that are all reduced by ALE, on the right, in accordance with an embodiment of this disclosure. -
FIGS. 3A-B present data showing a comparison of the ALE results obtained for Ru smoothing in accordance with an embodiment of this disclosure compared to other etch processes and chemistries. -
FIG. 4 depicts SEM images showing the high selectivity of an ALE process in accordance with an embodiment of this disclosure that has been demonstrated with Mo utilizing an O2/Cl2 modification chemistry. -
FIG. 5 shows a plot of data demonstrating that Cl2 and O2 modification mixture chemistries show 10-20 times faster etch rate of Mo blanket films compared to Cl2 only or O2-only modification chemistries in accordance with embodiments of this disclosure. -
FIG. 6 depicts a flow chart of a method of etching a refractory metal or other high EO material on a substrate in accordance with embodiments this disclosure. -
FIG. 7 schematically shows a cross-sectional view of an inductively coupled plasma etching apparatus appropriate for implementing certain embodiments herein. -
FIG. 8 depicts a semiconductor process cluster architecture with various modules that is appropriate for implementing certain embodiments herein. - In the following description, numerous specific details are set forth to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail to not unnecessarily obscure the disclosed embodiments. While the disclosed embodiments will be described in conjunction with the specific embodiments, it will be understood that it is not intended to limit the disclosed embodiments.
- Etching processes often involve exposing a material to be etched to a combination of etching gases to remove the material. However, such removal may in some cases etch more than desired, or result in an undesirable feature profile. As feature sizes shrink, there is a growing need for atomic scale processing.
- Some reactive ion etch (RIE) regimes are known to improve line width roughness (LWR) of sidewalls, however rarely less than 2 nm. Moreover, at the etch front in RIE, stochastic behavior forming the selvage layer tends to roughen the surface on a similar scale to 5 nm. There are many proposed mechanisms for why RIE would roughen the surface, including stochastic effects, ion-scattering, and micro-masking. These mechanisms kinetically hinder flattening of the surface, which would be thermodynamically favorable due to lower surface tension.
- Smooth etch lines are increasingly desirable to help meet electric requirements for advanced semiconductor manufacturing. As feature size continues to shrink, the critical dimension of metals lines reaches the sub-10 nm regime. However metals have a crystalline grain structure. Reactive ion etching typically has a faster reaction rate at grain boundaries than on the crystalline grains themselves. This preferential etch at the metal grain boundaries generates line edge roughness that causes variation and increases resistivity of metal contact lines.
- Etch processes that yield smooth, in at least some cases extremely smooth (e.g., up to 50% or more, 60% or more, 70% or more, 75% or more, 80% or more, or 90% or more root mean square (RMS) smoother than pre-etch surface roughness) etch front and line edge for refractory metals and other high surface binding energy materials, and in some cases improved selectivity to surrounding materials, are disclosed. Certain Atomic Layer Etch (ALE) processes have been demonstrated on refractory metals such as Mo, Ta and Ru, and could be used to process a variety of materials composed of grains. While ALE can be used for directional pattern transfer to produce smooth metal lines, it can also be applied for other purposes. In this regard, it is desired for both reliability and device electrical performance, to provide conformal liners (e.g., diffusion barrier or adhesion promoting layer) that are continuous, smooth and atomically thin. If, for example, an as-deposited liner is thicker and/or rougher than desired as deposited, ALE etchback may be utilized to appropriately thin and smooth the liner at the same time, thereby providing the desired result.
- ALE is a multi-step process used in advanced semiconductor manufacturing (e.g. technology node <10 nm) for the blanket removal or pattern-definition etching of ultra-thin layers of material with atomic scale in-depth resolution and control. ALE is a technique that removes thin layers of material using sequential self-limiting reactions. Examples of atomic layer etch techniques are described in U.S. Pat. Nos. 8,883,028 and 8,808,561, which are herein incorporated by reference for purposes of describing example atomic layer etch and etching techniques.
- The concept of an “ALE cycle” is relevant to the discussion of various embodiments herein. Generally an ALE cycle is the minimum set of operations used to perform an etch process one time, such as etching a monolayer. The result of one cycle is that at least some of a film layer on a substrate surface is etched. Typically, an ALE cycle includes a modification operation to form a modified layer, followed by a removal operation to remove or etch only this modified layer. The cycle may include certain ancillary operations such as sweeping, or purging, one of the reactants or byproducts. Generally, a cycle contains one instance of a unique sequence of operations. As an example, an ALE cycle may include the following operations: (i) delivery of a modification gas, (ii) purging of the reactant gas from the chamber, (iii) delivery of a removal gas and an optional plasma, and (iv) purging of the chamber. In some embodiments, etching may be performed nonconformally, including such that the resulting surface may be smoother, including much smoother, than the starting surface.
-
FIG. 1 shows two example schematic illustrations of an ALE cycle. Diagrams 171 a-171 e show a generic ALE cycle. In 171 a, the substrate is provided. In 171 b, the surface of the substrate is modified. In 171 c, the next step is prepared. In 171 d, the modified layer is being etched. In 171 e, the modified layer is removed. Similarly, diagrams 172 a-172 e show an example of an ALE cycle for etching a refractory metal film. In 172 a, an exposed Ru film surface on a substrate is provided, which includes many Ru metal atoms. In 172 b, modification gas, for example including oxygen gas, introduced to the substrate modifies the Ru metal surface of the substrate. The schematic in 172 b shows that some modification gas is adsorbed onto the surface of the substrate as an example. Although oxygen is depicted inFIG. 1 , a suitable oxygen-containing compound that forms volatile species with the metal atom may be used. In other embodiments, chlorine or suitable chlorine-containing gas that forms volatile species with the metal atom, may be used, or a combination of oxygen and chlorine gases, or suitable oxygen- and chlorine-containing gases, may be used to advantage with particular refractory metals, as further described below. In 172 c, the modification gas is purged from the chamber. In 172 d, a removal gas such as an inert gas including nitrogen, argon, neon, helium, or combinations thereof, for example argon, is introduced with a plasma, forming argon ions (energetic particles) as indicated by the Ar+ plasma species and arrows, and anisotropic ion bombardment is performed to remove the modified refractory metal surface of the substrate. During this operation, a bias is applied to the substrate to attract ions toward it. In 172 e, the chamber is purged and the byproducts are removed. - A cycle may only partially etch about 0.1 nm to about 50 nm of material, or between about 0.1 nm and about 20 nm of material, or between about 0.1 nm and about 2 nm of material, or between about 0.1 nm and about 5 nm of material, or between about 0.2 nm and about 50 nm of material, or between about 0.2 nm and about 5 nm of material. The amount of material etched in a cycle may depend on the purpose of etching in a self-limiting manner. In some embodiments, a cycle of ALE may remove less than a monolayer of material.
- ALE process conditions, such as chamber pressure, substrate temperature, plasma power, frequency, and type, and bias power, depend on the material to be etched, the composition of the gases used to modify the material to be etched, the material underlying the material to be etched, and the composition of gases used to remove the modified material.
- ALE involves splitting the etch process into two (or more) separate operations: modification (operation A) and removal (operation B). For example, the modification operation modifies the surface layer so that it can be removed easily during the removal operation. A thin layer of material is removed per cycle, where a cycle includes modification and removal, and the cycle can be repeated until the desired depth is reached. Synergy means that favorable etching occurs due to interaction of operations A and B. In ALE, operations A and B are separated in either space or time.
- Favorable atomic layer etching occurs due to the interaction of operations A and B, and the following “ALE synergy” metric is used to quantify the strength and impact of the synergistic interaction. ALE synergy is calculated by:
-
- where EPC (“etch per cycle”) is the thickness of substrate material removed in one ALE cycle, typically averaged over many cycles, and A and B are contributions to the EPC from the stand-alone modification and removal operations, respectfully, measured as reference points by performing these operations independently.
- Synergy is a test that captures many aspects of ALE behavior, and is well-suited to compare different ALE conditions or systems. It is an underlying mechanism for why etching in operation B stops after reactants from operation A are consumed. It is therefore responsible for the self-limiting behavior in ALE benefits such as aspect ratio independence, uniformity, smoothness, and selectivity.
- Disclosed embodiments are structured to achieve an ALE process with high synergy—the ideal being an ALE process with synergy being 100%. This ideal may not be possible to achieve in all cases given practical considerations such as the accessible range of process conditions, wafer throughput requirements, etc. However, tolerance for synergy less than the ideal of 100% will depend on the application and the technology node, and presumably each successive technology generation will demand higher levels of ideality.
- Disclosed embodiments for designing an ALE process with high synergy is based on achieving a hierarchical relationship between energies that characterize an overall ALE process and the energy barriers that are overcome to achieve etch with synergy close to 100%.
- This relationship is as follows:
-
E mod <E des <E O - EO, Emod, and Edes are determined by properties of the material to be etched and the reactant.
- EO is the surface binding energy of the unmodified material and is the cohesive force that keeps atoms from being removed from the surface.
- Emod (sometimes Eats) is the adsorption barrier to modify the surface and arises from the need to dissociate reactants or reorganize surface atoms.
- Edes is the desorption barrier, the energy used to remove a by-product from the modified surface.
- Disclosed embodiments are suitable for performing ALE of refractory metals, including Nb, Mo, Ta, W, Re, Ru, Rh, Os, Ir, Ti, V, Cr, Zr and Hf, in particular Mo, Ta and Ru. While W has long been integrated and studied in a semiconductor processing contexts, including our recent work on tungsten ALE removal and smoothing, ALE of other refractory metals has not to date been addressed to any significant extent. Anisotropic, or directional, ALE, in particular, is shown herein to provide advantageous smoothing, including extreme smoothing, results on refractory metals not previously studied to significant extent. Other high surface binding energy materials may also benefit from ALE processing as described.
- Refractory metals are good candidates for ALE because they have high EO. As further explained in “Atomic Layer Etching: Rethinking the Art of Etch”, Keren J. Kanarik and Richard A. Gottscho, Journal of Physical Chemistry Letters, 9 (16), pp. 4814-4821, 2018, incorporated by reference herein for its explanation of high EO materials relating to aspects and embodiments according to this disclosure. As explained therein, high EO materials are expected to do well in terms of high synergy and self-limiting ALE. Excellent candidate ALE elemental materials with EO>6 eV include C, along with refractory metals, such as W, Ta, Mo, Re, and Ru, for example. Other high surface binding energy (high EO) materials include oxides such as Al2O3, In2O3, MgO, SnO, Ta2O5, TiO2 and ZrO2; carbides such as BC, SiC and WC; nitrides such as BN, TaN, TiN; sulfides such as ZnS and MoS2; and superconductors such as YBCO. While materials with high EO (e.g., refractory metals and diamond) are known for resistance to heat, wear, and etching, the analysis indicates that when such materials are etched with ALE, it is more controllable (i.e., more ideal due to higher synergy).
- Embodiments can be used to develop new or improved unit or integrated processes as well as standalone or clustered hardware for semiconductor processing or other applications. The methodology can be implemented with appropriate computer software for offline use or embedded in a process tool for recipe development, process qualification, or process control. In the following discussion, non-limiting examples are provided for ALE resulting in smoothing, in some cases unexpected extreme smoothing, of molybdenum (Mo), ruthenium (Ru) and Tantalum, for example by more than 10% RMS, more than 20%, more than 30%, more than 40%, or more than 50%, more than 60%, more than 70%, as much as 75% or more, 80% or more, or 90% RMS or more, on the order of an order of magnitude increase in smoothness (decrease in roughness) from the initial film surface roughness.
- Within one ALE cycle the reaction rate on the surface has been found to have been equalized, without differentiating grain boundaries from grains. This leads to technical advantages, including:
- 1) A metal surface can be recessed while maintaining or even decreasing the roughness of the pristine surface as deposited.
- 2) High selectivity of a metal etch to mask to liner/filling dielectric materials can be achieved by manipulation of the modification gas chemistry. The chemistry can be selected to react with the metal line, while not modifying surrounding materials. The selectivity can be achieved between different metals, and between metals and semiconductor or dielectric materials.
- Results show that ALE can produce an even smoother surface than that on which etching began. Unexpectedly, the effect can be particularly dramatic, producing extreme smoothing, for example more than 50% RMS, more than 60%, more than 70%, more than 75%, more than 80%, or more than 90%; such as for the 75% smoothening after 100 cycles of Ru ALE using O2 as the modification gas and Ar plasma for removal (0.8 nm RMS roughness to 0.2 nm), as seen in
FIG. 2 .FIG. 2 depicts scanning electron microscope (SEM) images of, on the left, an incoming substrate surface with visible damage, roughness, or grain boundaries that are all reduced by ALE, on the right, in accordance with an embodiment of this disclosure. - Suitable modification gas chemistry can react to form a volatile compound. Thermal desorption temperature measurements can usefully be referenced. Suitable modification gases can include O2, Cl2, BCl3, H2 and CF4. For example, O2 has been shown to be effective for etching and smoothing C, and to provide extreme smoothing of Ru; Cl2 has been shown to be effective for etching and smoothing of Ta and W; and mixtures of Cl2 and O2 have been shown to be effective for etching and smoothing of Mo. And BCl3, H2 and CF4 are effective with the he oxides.
- In many instances, high synergy, for example greater than 80%, or above 90%, enhances smoothing.
- Suitable conditions can be in the range of:
- For operation A (modification):
- Pressure: about 50-100 mT, e.g., 50, 60, 70, 80, 90, or 100 mT;
Power: no bias; source power about 100-1000 W, e.g., 100, 200, 300, 400, 500, 600, 700, 800, 900 or 1000 W;
Temperature: material specific, set to avoid spontaneous etching e.g., about −70 to 150° C., e.g., −70, −60, −50, −40, −30, −20, −10, 0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 110, 120, 130, 140 or 150° C.;
Time: about 0.1-5 seconds, e.g., 0.1, 0.2, 0.5, 1, 2, 3, 4 or 5 s.
Operation B (removal):
Pressure: about 0.5-20 mT, e.g., 0.5, 1, 2, 5, 10, 15, 20 mT
Power: bias about 10-150V, e,g., 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 11, 120, 130, 140, or 150V bias; source power 100-1000 W, e.g., 100, 200, 300, 400, 500, 600, 700, 800, 900 or 1000 W;
Temperature: material specific, set to avoid spontaneous etching e.g., about −70 to 150° C., e.g., −70, −60, −50, −40, −30, −20, −10, 0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 110, 120, 130, 140 or 150° C.;
Time: about 0.1-10 seconds, e.g., 0.1, 0.2, 0.5, 1, 2, 3, 4, 5, 6, 7, 8, 9 or 10 s, for ion flux about 2×1016/cm2*S at 50 eV. - Additional data is presented in
FIGS. 3A-B , showing a comparison of the ALE results obtained for Ru smoothing in accordance with an embodiment of this disclosure compared to other etch processes and chemistries.FIG. 3A shows a plot of etch per cycle (EPC) as a function of Ar bias for a Ru substrate for O2/Ar ALE as described herein, compared to other etch processes and chemistries.FIG. 3B shows SEM plot of the corresponding substrate surfaces, incoming, O2 reactive ion etch (RIE) alone, Ar sputtering alone, and O2/Ar ALE. Both O2 RIE and Ar sputtering alone resulted in rougher surfaces, while O2/Ar ALE resulted in a much smoother surface. - While this disclosure is not limited by any particular theory of operation, it is believed this smoothening phenomenon may be due to high-synergy self-limiting ALE processes, and there could be multiple reasons why the smoothening is so extreme. In the ALE modification operation, a small radius of curvature has higher reactivity which could preferentially etch sharp corners; a corner can bond to 2 to 3 modification gas atoms instead of 0 to 1 on flat or concave surfaces. Furthermore, in the ALE removal operation inert ions in the absence of reactants can smooth surfaces by amorphization of the top ˜1 nm of the surface, which promotes diffusion of surface atoms. In contrast, in RIE, diffusion is hindered by strong bonds of etch species (e.g., CO attached to the crystal structure of the material to be etched.
- The resulting ultra-smooth a nanoscopic metal films would be expected to have decreased electrical resistivity due to less electron scattering at its surface, and might be able to be etched very thin while still keeping continuous to make a better barrier metal taking up less volume in a tiny 3D feature. In addition to the evident semiconductor processing applications, there may also be applications beyond the semiconductor industry.
- Another example is Ta ALE in which an about 33% reduction in surface roughness has been achieved (1.04 to 0.7 nm RMS).
- Still another example relates to smoothing via a ALE process that can also achieve high selectivity. Such a process has been demonstrated with Mo utilizing an O2/Cl2 modification chemistry, as described and depicted in
FIGS. 4 and 5 .FIG. 4 shows that a Cl2/Ar ALE process maintains the initial Mo surface roughness prior to ALE.FIG. 5 shows that Cl2 and O2 modification mixture chemistries show 10-20 times faster etch rate of Mo blanket films compared to Cl2 only or O2 only modification chemistries. Also, a 10% O2/90% Cl2 modification chemistry provided a high degree (>400:1) of etch selectivity relative to SiO2 dielectric (compared to just 10:1 for 100% Cl2 modification chemistry). - Such processes may be extended to other refractory metals or to other high surface binding energy (high EO) materials to, depending on the specific metal and process conditions, provide ultra-smoothening with high etch rate and/or high selectivity with respect to a mask material (e.g., an ashable amorphous carbon hard mask). The chemistry could be a suitably chosen admixture of oxidizing/chlorinating species. For example, a very high O2/Cl2 ratio or even 100% O2 could be used for Ru; and a very low O2:Cl2 ratio could be used for Mo (e.g., 10% O2/90% Cl2).
-
FIG. 6 shows a flow chart of a method of etching a refractory metal or other high EO material on a substrate in accordance with this disclosure. At 601 a substrate having an exposed refractory metal/high EO material surface is provided. At 603 the refractory metal/high EO surface is exposed to a modification gas to modify the surface and form a modified refractory metal surface. At 607 the modified refractory metal/high EO surface is exposed to an energetic particle to preferentially remove the modified refractory metal/high EO surface relative to an underlying unmodified refractory metal/high EO surface such that the exposed refractory metal/high EO surface after removing the modified refractory metal/high EO surface is as smooth or smoother than the substrate surface before exposing the substrate surface to the modification gas. The modification and removal operations may be followed by purging 605, 609 of the process chamber, and are generally repeated until the desired level of etch and/or smoothness is achieved. - Apparatus
- Inductively coupled plasma (ICP) reactors which, in certain embodiments, may be suitable for atomic layer etching (ALE) operations are now described. Such ICP reactors have also described in U.S. Patent Application Publication No. 2014/0170853, filed Dec. 10, 2013, and titled “IMAGE REVERSAL WITH AHM GAP FILL FOR MULTIPLE PATTERNING,” hereby incorporated by reference in its entirety and for all purposes. Although ICP reactors are described herein, in some embodiments, it should be understood that capacitively coupled plasma reactors may also be used.
-
FIG. 7 schematically shows a cross-sectional view of an inductively coupledplasma etching apparatus 700 appropriate for implementing certain embodiments herein, an example of which is a Kiyo™ reactor, produced by Lam Research Corp. of Fremont, Calif. The inductively coupledplasma apparatus 700 includes anoverall process chamber 701 structurally defined bychamber walls 701 and awindow 711. Thechamber walls 701 may be fabricated from stainless steel or aluminum. Thewindow 711 may be fabricated from quartz or other dielectric material. An optionalinternal plasma grid 750 divides theoverall processing chamber 701 into anupper sub-chamber 702 and alower sub-chamber 703. In most embodiments,plasma grid 750 may be removed, thereby utilizing a chamber space made of 702 and 703. Asub-chambers chuck 717 is positioned within thelower sub-chamber 703 near the bottom inner surface. Thechuck 717 is configured to receive and hold asemiconductor wafer 719 upon which the etching and deposition processes are performed. Thechuck 717 can be an electrostatic chuck for supporting thewafer 719 when present. In some embodiments, an edge ring (not shown) surroundschuck 717, and has an upper surface that is approximately planar with a top surface of awafer 719, when present overchuck 717. Thechuck 717 also includes electrostatic electrodes for chucking and dechucking the wafer. A filter and DC clamp power supply (not shown) may be provided for this purpose. Other control systems for lifting thewafer 719 off thechuck 717 can also be provided. Thechuck 717 can be electrically charged using anRF power supply 723. TheRF power supply 723 is connected to matchingcircuitry 721 through aconnection 727. The matchingcircuitry 721 is connected to thechuck 717 through aconnection 725. In this manner, theRF power supply 723 is connected to thechuck 717. - Elements for plasma generation include a
coil 733 is positioned abovewindow 711. In some embodiments, a coil is not used in disclosed embodiments. Thecoil 733 is fabricated from an electrically conductive material and includes at least one complete turn. The example of acoil 733 shown inFIG. 7 includes three turns. The cross-sections ofcoil 733 are shown with symbols, and coils having an “X” extend rotationally into the page, while coils having a “●” extend rotationally out of the page. Elements for plasma generation also include anRF power supply 741 configured to supply RF power to thecoil 733. In general, theRF power supply 741 is connected to matchingcircuitry 739 through aconnection 745. The matchingcircuitry 739 is connected to thecoil 733 through aconnection 743. In this manner, theRF power supply 741 is connected to thecoil 733. Anoptional Faraday shield 749 is positioned between thecoil 733 and thewindow 711. TheFaraday shield 749 is maintained in a spaced apart relationship relative to thecoil 733. TheFaraday shield 749 is disposed immediately above thewindow 711. Thecoil 733, theFaraday shield 749, and thewindow 711 are each configured to be substantially parallel to one another. The Faraday shield may prevent metal or other species from depositing on the dielectric window of theplasma chamber 701. - Process gases (e.g. chlorine, argon, oxygen, etc.) may be flowed into the
processing chamber 701 through one or more main gas flow inlets 760 positioned in theupper chamber 702 and/or through one or more sidegas flow inlets 770. Likewise, though not explicitly shown, similar gas flow inlets may be used to supply process gases to a capacitively coupled plasma processing chamber. A vacuum pump, e.g., a one or two stage mechanical dry pump and/orturbomolecular pump 740, may be used to draw process gases out of theprocess chamber 701 and to maintain a pressure within theprocess chamber 701. For example, the pump may be used to evacuate thechamber 701 during a purge operation of ALE. A valve-controlled conduit may be used to fluidically connect the vacuum pump to theprocessing chamber 701 so as to selectively control application of the vacuum environment provided by the vacuum pump. This may be done employing a closed-loop-controlled flow restriction device, such as a throttle valve (not shown) or a pendulum valve (not shown), during operational plasma processing. Likewise, a vacuum pump and valve controlled fluidic connection to the capacitively coupled plasma processing chamber may also be employed. - During operation of the apparatus, one or more process gases may be supplied through the gas flow inlets 760 and/or 770. In certain embodiments, process gas may be supplied only through the main gas flow inlet 760, or only through the side
gas flow inlet 770. In some cases, the gas flow inlets shown in the figure may be replaced more complex gas flow inlets, one or more showerheads, for example. TheFaraday shield 749 and/oroptional grid 750 may include internal channels and holes that allow delivery of process gases to thechamber 701. Either or both ofFaraday shield 749 andoptional grid 750 may serve as a showerhead for delivery of process gases. In some embodiments, a liquid vaporization and delivery system may be situated upstream of thechamber 701, such that once a liquid reactant or precursor is vaporized, the vaporized reactant or precursor is introduced into thechamber 701 via a gas flow inlet 760 and/or 770. Example liquid precursors include SiCl4 and silicon amides. - Radio frequency power is supplied from the
RF power supply 741 to thecoil 733 to cause an RF current to flow through thecoil 733. The RF current flowing through thecoil 733 generates an electromagnetic field about thecoil 733. The electromagnetic field generates an inductive current within theupper sub-chamber 702. The physical and chemical interactions of various generated ions and radicals with thewafer 719 selectively etch features of and deposit layers on the wafer. - If the plasma grid is used such that there is both an
upper sub-chamber 702 and alower sub-chamber 703, the inductive current acts on the gas present in theupper sub-chamber 702 to generate an electron-ion plasma in theupper sub-chamber 702. The optionalinternal plasma grid 750 limits the amount of hot electrons in thelower sub-chamber 703. In some embodiments, the apparatus is designed and operated such that the plasma present in thelower sub-chamber 703 is an ion-ion plasma. - Both the upper electron-ion plasma and the lower ion-ion plasma may contain positive and negative ions, though the ion-ion plasma will have a greater ratio of negative ions to positive ions. Volatile etching and/or deposition byproducts may be removed from the
lower sub-chamber 703 throughport 722. Thechuck 717 disclosed herein may operate at temperatures ranging between about −200° C. and about 600° C. or between about −20° C. and about 250° C. for processing a substrate to etch tantalum, thechuck 717 may be set at a temperature less than about 0° C. The temperature will depend on the process operation and specific recipe and the tool used. -
Chamber 701 may be coupled to facilities (not shown) when installed in a clean room or a fabrication facility. Facilities include plumbing that provide processing gases, vacuum, temperature control, and environmental particle control. These facilities are coupled tochamber 701, when installed in the target fabrication facility. Additionally,chamber 701 may be coupled to a transfer chamber that allows robotics to transfer semiconductor wafers into and out ofchamber 701 using typical automation. - In some embodiments, a system controller 730 (which may include one or more physical or logical controllers) controls some or all of the operations of a processing chamber. The
system controller 730 may include one or more memory devices and one or more processors. In some embodiments, the apparatus includes a switching system for controlling flow rates and durations when disclosed embodiments are performed. In some embodiments, the apparatus may have a switching time of up to about 500 ms, or up to about 750 ms. Switching time may depend on the flow chemistry, recipe chosen, reactor architecture, and other factors. - In some implementations, a
controller 730 is part of a system, which may be part of the above-described examples. Such systems can comprise semiconductor processing equipment, including a processing tool or tools, chamber or chambers, a platform or platforms for processing, and/or specific processing components (a wafer pedestal, a gas flow system, etc.). These systems may be integrated with electronics for controlling their operation before, during, and after processing of a semiconductor wafer or substrate. The electronics may be referred to as the “controller,” which may control various components or subparts of the system or systems. Thecontroller 730, depending on the processing parameters and/or the type of system, may be programmed to control any of the processes disclosed herein, including the delivery of processing gases, temperature settings (e.g., heating and/or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positional and operation settings, wafer transfers into and out of a tool and other transfer tools and/or load locks connected to or interfaced with a specific system. - Broadly speaking, the
controller 730 may be defined as electronics having various integrated circuits, logic, memory, and/or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and/or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files), defining operational parameters for carrying out a particular process on or for a semiconductor wafer or to a system. The operational parameters may, in some embodiments, be part of a recipe defined by process engineers to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and/or dies of a wafer. - The
controller 730, in some implementations, may be a part of or coupled to a computer that is integrated with, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller may be in the “cloud” or all or a part of a fab host computer system, which can allow for remote access of the wafer processing. The computer may enable remote access to the system to monitor current progress of fabrication operations, examine a history of past fabrication operations, examine trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process. In some examples, a remote computer (e.g. a server) can provide process recipes to a system over a network, which may include a local network or the Internet. The remote computer may include a user interface that enables entry or programming of parameters and/or settings, which are then communicated to the system from the remote computer. In some examples, thecontroller 730 receives instructions in the form of data, which specify parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the controller is configured to interface with or control. Thus as described above, thecontroller 730 may be distributed, such as by comprising one or more discrete controllers that are networked together and working towards a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes would be one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) that combine to control a process on the chamber. - Without limitation, example systems may include a plasma etch chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a clean chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an ALD chamber or module, an ALE chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing systems that may be associated or used in the fabrication and/or manufacturing of semiconductor wafers.
- As noted above, depending on the process step or steps to be performed by the tool, the controller might communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and/or load ports in a semiconductor manufacturing factory.
-
FIG. 8 depicts a semiconductor process cluster architecture with various modules that interface with a vacuum transfer module 838 (VTM). The arrangement of transfer modules to “transfer” wafers among multiple storage facilities and processing modules may be referred to as a “cluster tool architecture” system.Airlock 830, also known as a loadlock or transfer module, is shown inVTM 838 with four processing modules 820 a-820 d, which may be individual optimized to perform various fabrication processes. By way of example, processing modules 820 a-820 d may be implemented to perform substrate etching, deposition, ion implantation, wafer cleaning, sputtering, and/or other semiconductor processes. One or more of the substrate etching processing modules (any of 820 a-820 d) may be implemented as disclosed herein, i.e., for introducing a modification gas, for introducing a removal gas, and other suitable functions in accordance with the disclosed embodiments.Airlock 830 and process module 820 may be referred to as “stations.” Each station has afacet 836 that interfaces the station toVTM 838. Inside each facet, sensors 1-18 are used to detect the passing ofwafer 826 when moved between respective stations. -
Robot 822transfers wafer 826 between stations. In one embodiment,robot 822 has one arm, and in another embodiment,robot 822 has two arms, where each arm has anend effector 824 to pick wafers such aswafer 826 for transport. Front-end robot 832, in atmospheric transfer module (ATM) 840, is used to transferwafers 826 from cassette or Front Opening Unified Pod (FOUP) 834 in Load Port Module (LPM) 842 toairlock 830.Module center 828 inside process module 820 is one location for placingwafer 826.Aligner 844 inATM 840 is used to align wafers. - In an exemplary processing method, a wafer is placed in one of the
FOUPs 834 in theLPM 842. Front-end robot 832 transfers the wafer from theFOUP 834 to analigner 844, which allows thewafer 826 to be properly centered before it is etched or processed. After being aligned, thewafer 826 is moved by the front-end robot 832 into anairlock 830. Because airlock modules have the ability to match the environment between an ATM and a VTM, thewafer 826 is able to move between the two pressure environments without being damaged. From theairlock module 830, thewafer 826 is moved byrobot 822 throughVTM 838 and into one of the process modules 820 a-320 d. In order to achieve this wafer movement, therobot 822 usesend effectors 824 on each of its arms. Once thewafer 826 has been processed, it is moved byrobot 822 from the process modules 820 a-820 d to anairlock module 830. From here, thewafer 826 may be moved by the front-end robot 832 to one of theFOUPs 834 or to thealigner 844. - It should be noted that the computer controlling the wafer movement can be local to the cluster architecture, or can be located external to the cluster architecture in the manufacturing floor, or in a remote location and connected to the cluster architecture via a network. A controller as described above with respect to
FIG. 7 may be implemented with the tool inFIG. 8 . - Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of this disclosure and the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and apparatus of the present embodiments. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein.
Claims (21)
1. A method of etching a refractory metal or other high surface binding energy (high EO) material on a substrate, the method comprising:
providing a substrate comprising an exposed refractory metal/high EO surface;
exposing the refractory metal/high EO surface to a modification gas to modify the surface and form a modified refractory metal/high EO surface; and
exposing the modified refractory metal/high EO surface to an energetic particle to preferentially remove the modified refractory metal/high EO surface relative to an underlying unmodified refractory metal/high EO surface;
wherein the exposed refractory metal/high EO surface after removing the modified refractory metal/high EO surface is as smooth or smoother than the substrate surface before exposing the substrate surface to the modification gas.
2. The method of claim 1 , wherein the smoothness of the refractory metal/high EO surface is maintained.
3. The method of claim 1 , wherein the smoothness of the refractory metal/high EO surface is increased.
4. The method of claim 3 , wherein the smoothness of the refractory metal/high EO surface is increased by more than 10% RMS, more than 20%, more than 30%, more than 40%, more than 50%, more than 60%, more than 70%, 75% or more, more than 80%, or more than 90% RMS, on the order of an order of magnitude increase in smoothness.
5. The method of claim 1 , wherein the refractory metal/high EO surface is a refractory metal selected from the group consisting of Nb, Mo, Ta, W, Re, Ru, Rh, Os, Ir, Ti, V, Cr, Zr and Hf.
6. The method of claim 5 , wherein the refractory metal is selected from the group consisting of Mo, Ta and Ru.
7. The method of claim 6 , wherein the refractory metal is Ru.
8. The method of claim 6 , wherein the refractory metal is Ta.
9. The method of claim 6 , wherein the refractory metal is Mo.
10. The method of claim 1 , wherein the modification gas comprises O2 or other oxygen-containing gas.
11. The method of claim 1 , wherein the modification gas comprises Cl2 or other chlorine-containing gas.
12. The method of claim 1 , wherein the modification gas comprises a mixture of O2 or other oxygen-containing gas, and Cl2 or other chlorine-containing gas.
13. The method of claim 7 , wherein the modification gas comprises O2 or other oxygen-containing gas.
14. The method of claim 9 , wherein the modification gas comprises a mixture of O2 or other oxygen-containing gas, and Cl2 or other chlorine-containing gas.
15. The method of claim 9 , wherein the modification gas comprises a mixture of about 10-20% O2 and about 90-80% Cl2.
16. The method of claim 1 , wherein the energetic particle is an inert ion plasma.
17. The method of claim 16 , wherein the plasma is an Ar plasma.
18. The method of claim 12 , wherein the modification gas mixture is selective to refractory metal.
19. The method of claim 1 , wherein the refractory metal/high EO is a material selected from the group consisting of oxides such as Al2O3, In2O3, MgO, SnO, Ta2O5, TiO2 and ZrO2; carbides such as BC, SiC and WC; nitrides such as BN, TaN, TiN; sulfides such as ZnS and MoS2; and superconductors such as YBCO.
20. The method of claim 1 , wherein the substrate surface is smoothened for non-semiconductor processing applications.
21. An apparatus for processing a substrate, the apparatus comprising:
a process chamber comprising a showerhead and a substrate support for holding the substrate having a material,
a plasma generator, and
a controller having at least one processor and a memory,
wherein the at least one processor and the memory are communicatively connected with one another,
the at least one processor is at least operatively connected with flow-control hardware, and
the memory stores machine-readable instructions for etching a refractory metal/high EO on a substrate, the instructions comprising:
providing a substrate comprising an exposed refractory metal/high EO surface;
exposing the refractory metal/high EO surface to a modification gas to modify the surface and form a modified refractory metal/high EO surface; and
exposing the modified refractory metal surface to an energetic particle to preferentially remove the modified refractory metal/high EO surface relative to an underlying unmodified refractory metal/high EO surface;
wherein the exposed refractory metal/high EO surface after removing the modified refractory metal/high EO surface is as smooth or smoother than the substrate surface before exposing the substrate surface to the modification gas.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11721558B2 (en) | 2016-12-19 | 2023-08-08 | Lam Research Corporation | Designer atomic layer etching |
| US12444651B2 (en) | 2009-08-04 | 2025-10-14 | Novellus Systems, Inc. | Tungsten feature fill with nucleation inhibition |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9972504B2 (en) | 2015-08-07 | 2018-05-15 | Lam Research Corporation | Atomic layer etching of tungsten for enhanced tungsten deposition fill |
| US11921427B2 (en) | 2018-11-14 | 2024-03-05 | Lam Research Corporation | Methods for making hard masks useful in next-generation lithography |
| KR102731166B1 (en) | 2018-12-20 | 2024-11-18 | 램 리써치 코포레이션 | Dry development of resists |
| TWI869221B (en) | 2019-06-26 | 2025-01-01 | 美商蘭姆研究公司 | Photoresist development with halide chemistries |
| CN116705595A (en) | 2020-01-15 | 2023-09-05 | 朗姆研究公司 | Underlayer for photoresist adhesion and dose reduction |
| KR20220149611A (en) * | 2020-03-06 | 2022-11-08 | 램 리써치 코포레이션 | Atomic Layer Etching of Molybdenum |
| KR102601038B1 (en) | 2020-07-07 | 2023-11-09 | 램 리써치 코포레이션 | Integrated dry processes for patterning radiation photoresist patterning |
| JP7526361B2 (en) * | 2020-09-03 | 2024-07-31 | アプライド マテリアルズ インコーポレイテッド | Selective anisotropic metal etching |
| US20230107357A1 (en) | 2020-11-13 | 2023-04-06 | Lam Research Corporation | Process tool for dry removal of photoresist |
| KR102765372B1 (en) * | 2021-11-16 | 2025-02-11 | 세메스 주식회사 | Apparatus and method for processing substrate |
| WO2023183129A1 (en) * | 2022-03-22 | 2023-09-28 | Lam Research Corporation | Fast atomic layer etch |
| KR20240006268A (en) * | 2022-07-06 | 2024-01-15 | 에스케이스페셜티 주식회사 | Atomic layer etching method of metal oxide layer |
| WO2024263088A1 (en) * | 2023-06-19 | 2024-12-26 | Alixlabs Ab | Cyclic surface conditioning method and surface preparation method for epitaxial material growth |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040209476A1 (en) * | 2003-04-17 | 2004-10-21 | Applied Materials, Inc. | Method of fabricating a magneto-resistive random access memory (MRAM) device |
| US20060016781A1 (en) * | 2004-07-26 | 2006-01-26 | Kenichi Kuwabara | Dry etching method |
| US20160308112A1 (en) * | 2015-04-20 | 2016-10-20 | Lam Research Corporation | Dry plasma etch method to pattern mram stack |
Family Cites Families (150)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3798056A (en) | 1972-04-05 | 1974-03-19 | Bell Telephone Labor Inc | Electroless plating process |
| JPH061769B2 (en) | 1983-08-10 | 1994-01-05 | 株式会社日立製作所 | Alumina film patterning method |
| US4756794A (en) | 1987-08-31 | 1988-07-12 | The United States Of America As Represented By The Secretary Of The Navy | Atomic layer etching |
| JPH03133128A (en) | 1989-10-19 | 1991-06-06 | Res Dev Corp Of Japan | Digital etching |
| JPH03263827A (en) | 1990-03-14 | 1991-11-25 | Yasuhiro Horiike | Digital etching apparatus |
| JPH06151382A (en) | 1992-11-11 | 1994-05-31 | Toshiba Corp | Dry etching method |
| JPH06326060A (en) | 1993-05-12 | 1994-11-25 | Hitachi Ltd | Working method of surface of solid |
| US6022806A (en) | 1994-03-15 | 2000-02-08 | Kabushiki Kaisha Toshiba | Method of forming a film in recess by vapor phase growth |
| GB2322235B (en) | 1995-10-19 | 2000-09-27 | Massachusetts Inst Technology | Metals removal process |
| EP0895282A3 (en) | 1997-07-30 | 2000-01-26 | Canon Kabushiki Kaisha | Method of preparing a SOI substrate by using a bonding process, and SOI substrate produced by the same |
| US6323132B1 (en) | 1998-01-13 | 2001-11-27 | Applied Materials, Inc. | Etching methods for anisotropic platinum profile |
| JP2002510146A (en) | 1998-01-13 | 2002-04-02 | アプライド マテリアルズ インコーポレイテッド | Etching method for anisotropic platinum profile |
| US6177353B1 (en) | 1998-09-15 | 2001-01-23 | Infineon Technologies North America Corp. | Metallization etching techniques for reducing post-etch corrosion of metal lines |
| US6143082A (en) | 1998-10-08 | 2000-11-07 | Novellus Systems, Inc. | Isolation of incompatible processes in a multi-station processing chamber |
| US8696875B2 (en) | 1999-10-08 | 2014-04-15 | Applied Materials, Inc. | Self-ionized and inductively-coupled plasma for sputtering and resputtering |
| US6458694B2 (en) | 2000-01-24 | 2002-10-01 | Ebara Corporation | High energy sputtering method for forming interconnects |
| JP3662472B2 (en) | 2000-05-09 | 2005-06-22 | エム・エフエスアイ株式会社 | Substrate surface treatment method |
| US6677242B1 (en) | 2000-08-12 | 2004-01-13 | Applied Materials Inc. | Integrated shallow trench isolation approach |
| US6527855B2 (en) | 2000-10-10 | 2003-03-04 | Rensselaer Polytechnic Institute | Atomic layer deposition of cobalt from cobalt metallorganic compounds |
| US20020058409A1 (en) | 2000-11-16 | 2002-05-16 | Ching-Te Lin | Elimination of overhang in liner/barrier/seed layers using post-deposition sputter etch |
| KR100401655B1 (en) * | 2001-01-18 | 2003-10-17 | 주식회사 컴텍스 | A smart process with alumina dielectric layer formation using ALE and a manufacturing method of unibond type SOI wafer |
| US6448192B1 (en) | 2001-04-16 | 2002-09-10 | Motorola, Inc. | Method for forming a high dielectric constant material |
| WO2002091461A2 (en) | 2001-05-04 | 2002-11-14 | Tokyo Electron Limited | Ionized pvd with sequential deposition and etching |
| US6635965B1 (en) | 2001-05-22 | 2003-10-21 | Novellus Systems, Inc. | Method for producing ultra-thin tungsten layers with improved step coverage |
| US7589017B2 (en) | 2001-05-22 | 2009-09-15 | Novellus Systems, Inc. | Methods for growing low-resistivity tungsten film |
| US7141494B2 (en) | 2001-05-22 | 2006-11-28 | Novellus Systems, Inc. | Method for reducing tungsten film roughness and improving step coverage |
| US7955972B2 (en) | 2001-05-22 | 2011-06-07 | Novellus Systems, Inc. | Methods for growing low-resistivity tungsten for high aspect ratio and small features |
| US7005372B2 (en) | 2003-01-21 | 2006-02-28 | Novellus Systems, Inc. | Deposition of tungsten nitride |
| US8110489B2 (en) | 2001-07-25 | 2012-02-07 | Applied Materials, Inc. | Process for forming cobalt-containing materials |
| US7049226B2 (en) | 2001-09-26 | 2006-05-23 | Applied Materials, Inc. | Integration of ALD tantalum nitride for copper metallization |
| US7115516B2 (en) | 2001-10-09 | 2006-10-03 | Applied Materials, Inc. | Method of depositing a material layer |
| US6664122B1 (en) | 2001-10-19 | 2003-12-16 | Novellus Systems, Inc. | Electroless copper deposition method for preparing copper seed layers |
| US7690324B1 (en) | 2002-06-28 | 2010-04-06 | Novellus Systems, Inc. | Small-volume electroless plating cell |
| AU2003223472A1 (en) | 2002-05-14 | 2003-12-02 | Tokyo Electron Limited | PLASMA ETCHING OF Cu-CONTAINING LAYERS |
| US6841943B2 (en) | 2002-06-27 | 2005-01-11 | Lam Research Corp. | Plasma processor with electrode simultaneously responsive to plural frequencies |
| US6884730B2 (en) | 2002-07-02 | 2005-04-26 | Headway Technologies, Inc. | Method of etching a film of magnetic material and method of manufacturing a thin-film magnetic head |
| WO2004009861A2 (en) | 2002-07-19 | 2004-01-29 | Asm America, Inc. | Method to form ultra high quality silicon-containing compound layers |
| TWI303090B (en) | 2002-08-13 | 2008-11-11 | Lam Res Corp | Method for in-situ monitoring of patterned substrate processing using reflectometry |
| US6933239B2 (en) | 2003-01-13 | 2005-08-23 | Applied Materials, Inc. | Method for removing conductive residue |
| WO2004095551A1 (en) | 2003-03-31 | 2004-11-04 | Tokyo Electron Limited | Method and apparatus for multilayer photoresist dry development |
| JP2004332045A (en) | 2003-05-07 | 2004-11-25 | Renesas Technology Corp | Dry etching method for multilayer material |
| US6844258B1 (en) | 2003-05-09 | 2005-01-18 | Novellus Systems, Inc. | Selective refractory metal and nitride capping |
| US7371688B2 (en) | 2003-09-30 | 2008-05-13 | Air Products And Chemicals, Inc. | Removal of transition metal ternary and/or quaternary barrier materials from a substrate |
| US7341946B2 (en) | 2003-11-10 | 2008-03-11 | Novellus Systems, Inc. | Methods for the electrochemical deposition of copper onto a barrier layer of a work piece |
| US20050233555A1 (en) | 2004-04-19 | 2005-10-20 | Nagarajan Rajagopalan | Adhesion improvement for low k dielectrics to conductive materials |
| US7829152B2 (en) | 2006-10-05 | 2010-11-09 | Lam Research Corporation | Electroless plating method and apparatus |
| US7115522B2 (en) | 2004-07-09 | 2006-10-03 | Kabushiki Kaisha Toshiba | Method for manufacturing semiconductor device |
| CN100576474C (en) | 2004-07-20 | 2009-12-30 | 应用材料股份有限公司 | Atomic layer deposition of tantalum-containing materials using tantalum precursor TAIMATA |
| US7196955B2 (en) | 2005-01-12 | 2007-03-27 | Hewlett-Packard Development Company, L.P. | Hardmasks for providing thermally assisted switching of magnetic memory elements |
| US7235492B2 (en) | 2005-01-31 | 2007-06-26 | Applied Materials, Inc. | Low temperature etchant for treatment of silicon-containing surfaces |
| JP4860219B2 (en) | 2005-02-14 | 2012-01-25 | 東京エレクトロン株式会社 | Substrate processing method, electronic device manufacturing method, and program |
| US7214626B2 (en) | 2005-08-24 | 2007-05-08 | United Microelectronics Corp. | Etching process for decreasing mask defect |
| US20070087581A1 (en) | 2005-09-09 | 2007-04-19 | Varian Semiconductor Equipment Associates, Inc. | Technique for atomic layer deposition |
| DE102006001253B4 (en) | 2005-12-30 | 2013-02-07 | Advanced Micro Devices, Inc. | A method of forming a metal layer over a patterned dielectric by wet-chemical deposition with an electroless and a power controlled phase |
| US20070238301A1 (en) | 2006-03-28 | 2007-10-11 | Cabral Stephen H | Batch processing system and method for performing chemical oxide removal |
| US7795148B2 (en) | 2006-03-28 | 2010-09-14 | Tokyo Electron Limited | Method for removing damaged dielectric material |
| US7368393B2 (en) | 2006-04-20 | 2008-05-06 | International Business Machines Corporation | Chemical oxide removal of plasma damaged SiCOH low k dielectrics |
| US7416989B1 (en) | 2006-06-30 | 2008-08-26 | Novellus Systems, Inc. | Adsorption based material removal process |
| KR100905278B1 (en) | 2007-07-19 | 2009-06-29 | 주식회사 아이피에스 | Thin film deposition apparatus, thin film deposition method and gap-fill method of semiconductor device |
| KR101330707B1 (en) | 2007-07-19 | 2013-11-19 | 삼성전자주식회사 | Method of forming Semiconducotr Device |
| US8481423B2 (en) | 2007-09-19 | 2013-07-09 | International Business Machines Corporation | Methods to mitigate plasma damage in organosilicate dielectrics |
| US9059116B2 (en) | 2007-11-29 | 2015-06-16 | Lam Research Corporation | Etch with pulsed bias |
| US7772114B2 (en) | 2007-12-05 | 2010-08-10 | Novellus Systems, Inc. | Method for improving uniformity and adhesion of low resistivity tungsten film |
| JP5759177B2 (en) | 2008-02-08 | 2015-08-05 | ラム リサーチ コーポレーションLam Research Corporation | Plasma processing apparatus, method for processing semiconductor substrate, and axis perpendicular displacement bellows unit |
| US8247030B2 (en) | 2008-03-07 | 2012-08-21 | Tokyo Electron Limited | Void-free copper filling of recessed features using a smooth non-agglomerated copper seed layer |
| US9048088B2 (en) | 2008-03-28 | 2015-06-02 | Lam Research Corporation | Processes and solutions for substrate cleaning and electroless deposition |
| US7948044B2 (en) | 2008-04-09 | 2011-05-24 | Magic Technologies, Inc. | Low switching current MTJ element for ultra-high STT-RAM and a method for making the same |
| US8252194B2 (en) | 2008-05-02 | 2012-08-28 | Micron Technology, Inc. | Methods of removing silicon oxide |
| US7943527B2 (en) | 2008-05-30 | 2011-05-17 | The Board Of Trustees Of The University Of Illinois | Surface preparation for thin film growth by enhanced nucleation |
| US8058170B2 (en) | 2008-06-12 | 2011-11-15 | Novellus Systems, Inc. | Method for depositing thin tungsten film with low resistivity and robust micro-adhesion characteristics |
| US8551885B2 (en) | 2008-08-29 | 2013-10-08 | Novellus Systems, Inc. | Method for reducing tungsten roughness and improving reflectivity |
| WO2011013255A1 (en) | 2009-07-31 | 2011-02-03 | 株式会社 東芝 | Nonvolatile storage device |
| US8124531B2 (en) | 2009-08-04 | 2012-02-28 | Novellus Systems, Inc. | Depositing tungsten into high aspect ratio features |
| US9034768B2 (en) | 2010-07-09 | 2015-05-19 | Novellus Systems, Inc. | Depositing tungsten into high aspect ratio features |
| US20110139748A1 (en) | 2009-12-15 | 2011-06-16 | University Of Houston | Atomic layer etching with pulsed plasmas |
| US8227344B2 (en) | 2010-02-26 | 2012-07-24 | Tokyo Electron Limited | Hybrid in-situ dry cleaning of oxidized surface layers |
| US8709551B2 (en) | 2010-03-25 | 2014-04-29 | Novellus Systems, Inc. | Smooth silicon-containing films |
| KR101626954B1 (en) | 2010-03-29 | 2016-06-03 | 삼성전자주식회사 | Method for manufacturing capacitor of semiconductor device and capacitor of semiconductor device manufactured thereby |
| US8728956B2 (en) | 2010-04-15 | 2014-05-20 | Novellus Systems, Inc. | Plasma activated conformal film deposition |
| US9373500B2 (en) | 2014-02-21 | 2016-06-21 | Lam Research Corporation | Plasma assisted atomic layer deposition titanium oxide for conformal encapsulation and gapfill applications |
| KR101340793B1 (en) | 2010-07-09 | 2013-12-11 | 노벨러스 시스템즈, 인코포레이티드 | Depositing tungsten into high aspect ratio features |
| WO2012023537A1 (en) | 2010-08-19 | 2012-02-23 | 株式会社 アルバック | Dry etching method and method of manufacturing semiconductor device |
| US8546263B2 (en) | 2011-04-27 | 2013-10-01 | Applied Materials, Inc. | Method of patterning of magnetic tunnel junctions |
| US8617411B2 (en) | 2011-07-20 | 2013-12-31 | Lam Research Corporation | Methods and apparatus for atomic layer etching |
| US9666414B2 (en) | 2011-10-27 | 2017-05-30 | Applied Materials, Inc. | Process chamber for etching low k and other dielectric films |
| US8808561B2 (en) | 2011-11-15 | 2014-08-19 | Lam Research Coporation | Inert-dominant pulsing in plasma processing systems |
| US20130129922A1 (en) | 2011-11-21 | 2013-05-23 | Qualcomm Mems Technologies, Inc. | Batch processing for electromechanical systems and equipment for same |
| US8633115B2 (en) | 2011-11-30 | 2014-01-21 | Applied Materials, Inc. | Methods for atomic layer etching |
| US8883028B2 (en) | 2011-12-28 | 2014-11-11 | Lam Research Corporation | Mixed mode pulsing etching in plasma processing systems |
| JP2013235912A (en) | 2012-05-08 | 2013-11-21 | Tokyo Electron Ltd | Method for etching substrate to be processed and plasma etching device |
| JP2014049466A (en) | 2012-08-29 | 2014-03-17 | Tokyo Electron Ltd | Etching processing method and substrate processing apparatus |
| US9177780B2 (en) | 2012-10-02 | 2015-11-03 | Applied Materials, Inc. | Directional SiO2 etch using plasma pre-treatment and high-temperature etchant deposition |
| TWI595112B (en) | 2012-10-23 | 2017-08-11 | 蘭姆研究公司 | Subsaturated Atomic Layer Deposition and Conformal Film Deposition |
| JP6035117B2 (en) | 2012-11-09 | 2016-11-30 | 東京エレクトロン株式会社 | Plasma etching method and plasma etching apparatus |
| JP5918108B2 (en) | 2012-11-16 | 2016-05-18 | 東京エレクトロン株式会社 | Plasma processing method and plasma processing apparatus |
| US9362133B2 (en) | 2012-12-14 | 2016-06-07 | Lam Research Corporation | Method for forming a mask by etching conformal film on patterned ashable hardmask |
| US20140349469A1 (en) | 2013-05-22 | 2014-11-27 | Qualcomm Mems Technologies, Inc. | Processing for electromechanical systems and equipment for same |
| SG11201509673SA (en) | 2013-06-17 | 2016-01-28 | Applied Materials Inc | Method for copper plating through silicon vias using wet wafer back contact |
| JP6170754B2 (en) | 2013-06-18 | 2017-07-26 | 株式会社日立国際電気 | Semiconductor device manufacturing method, substrate processing apparatus, and program |
| JP6242095B2 (en) | 2013-06-28 | 2017-12-06 | 株式会社日立国際電気 | Cleaning method, semiconductor device manufacturing method, substrate processing apparatus, and program |
| US9362163B2 (en) | 2013-07-30 | 2016-06-07 | Lam Research Corporation | Methods and apparatuses for atomic layer cleaning of contacts and vias |
| JP6347695B2 (en) | 2013-11-20 | 2018-06-27 | 東京エレクトロン株式会社 | Method for etching a layer to be etched |
| US9435049B2 (en) | 2013-11-20 | 2016-09-06 | Lam Research Corporation | Alkaline pretreatment for electroplating |
| US10265742B2 (en) * | 2013-11-25 | 2019-04-23 | Applied Materials, Inc. | Method for in-situ chamber clean using carbon monoxide (CO) gas utlized in an etch processing chamber |
| US9620382B2 (en) | 2013-12-06 | 2017-04-11 | University Of Maryland, College Park | Reactor for plasma-based atomic layer etching of materials |
| FR3017241B1 (en) * | 2014-01-31 | 2017-08-25 | Commissariat Energie Atomique | PLASMA ETCHING PROCESS |
| US9257638B2 (en) | 2014-03-27 | 2016-02-09 | Lam Research Corporation | Method to etch non-volatile metal materials |
| US20150345029A1 (en) * | 2014-05-28 | 2015-12-03 | Applied Materials, Inc. | Metal removal |
| US9773683B2 (en) | 2014-06-09 | 2017-09-26 | American Air Liquide, Inc. | Atomic layer or cyclic plasma etching chemistries and processes |
| US10047438B2 (en) | 2014-06-10 | 2018-08-14 | Lam Research Corporation | Defect control and stability of DC bias in RF plasma-based substrate processing systems using molecular reactive purge gas |
| US9768033B2 (en) | 2014-07-10 | 2017-09-19 | Tokyo Electron Limited | Methods for high precision etching of substrates |
| FR3023971B1 (en) | 2014-07-18 | 2016-08-05 | Commissariat Energie Atomique | METHOD FOR FORMING SPACERS OF A GRID OF A TRANSISTOR |
| US10049921B2 (en) | 2014-08-20 | 2018-08-14 | Lam Research Corporation | Method for selectively sealing ultra low-k porous dielectric layer using flowable dielectric film formed from vapor phase dielectric precursor |
| US9520294B2 (en) | 2014-08-29 | 2016-12-13 | Applied Materials, Inc. | Atomic layer etch process using an electron beam |
| US9240315B1 (en) | 2014-10-10 | 2016-01-19 | Applied Materials, Inc. | CVD oxide surface pre-conditioning by inductively coupled O2 plasma |
| US9609730B2 (en) | 2014-11-12 | 2017-03-28 | Lam Research Corporation | Adjustment of VUV emission of a plasma via collisional resonant energy transfer to an energy absorber gas |
| US10170324B2 (en) | 2014-12-04 | 2019-01-01 | Lam Research Corporation | Technique to tune sidewall passivation deposition conformality for high aspect ratio cylinder etch |
| WO2016100873A1 (en) | 2014-12-18 | 2016-06-23 | The Regents Of The University Of Colorado, A Body Corporate | Novel methods of atomic layer etching (ale) using sequential, self-limiting thermal reactions |
| US9576811B2 (en) | 2015-01-12 | 2017-02-21 | Lam Research Corporation | Integrating atomic scale processes: ALD (atomic layer deposition) and ALE (atomic layer etch) |
| KR102510737B1 (en) | 2015-03-30 | 2023-03-15 | 도쿄엘렉트론가부시키가이샤 | Atomic layer etching method |
| US9870899B2 (en) | 2015-04-24 | 2018-01-16 | Lam Research Corporation | Cobalt etch back |
| US9892935B2 (en) | 2015-05-28 | 2018-02-13 | International Business Machines Corporation | Limiting electronic package warpage with semiconductor chip lid and lid-ring |
| SG10201604524PA (en) | 2015-06-05 | 2017-01-27 | Lam Res Corp | ATOMIC LAYER ETCHING OF GaN AND OTHER III-V MATERIALS |
| US9449843B1 (en) | 2015-06-09 | 2016-09-20 | Applied Materials, Inc. | Selectively etching metals and metal nitrides conformally |
| US9922839B2 (en) | 2015-06-23 | 2018-03-20 | Lam Research Corporation | Low roughness EUV lithography |
| US20160381060A1 (en) | 2015-06-23 | 2016-12-29 | Veracode, Inc. | Systems and methods for aggregating asset vulnerabilities |
| US9972504B2 (en) | 2015-08-07 | 2018-05-15 | Lam Research Corporation | Atomic layer etching of tungsten for enhanced tungsten deposition fill |
| US9620376B2 (en) | 2015-08-19 | 2017-04-11 | Lam Research Corporation | Self limiting lateral atomic layer etch |
| US9520821B1 (en) | 2015-08-19 | 2016-12-13 | Nidec Motor Corporation | System and method for optimizing flux regulation in electric motors |
| US10096487B2 (en) * | 2015-08-19 | 2018-10-09 | Lam Research Corporation | Atomic layer etching of tungsten and other metals |
| US9984858B2 (en) | 2015-09-04 | 2018-05-29 | Lam Research Corporation | ALE smoothness: in and outside semiconductor industry |
| CN108352316B (en) | 2015-11-10 | 2023-03-24 | 乔治洛德方法研究和开发液化空气有限公司 | Etching reactant and plasma-free oxide etching method using the same |
| WO2017099718A1 (en) | 2015-12-08 | 2017-06-15 | Intel Corporation | Atomic layer etching of transition metals by halogen surface oxidation |
| US9735024B2 (en) | 2015-12-28 | 2017-08-15 | Asm Ip Holding B.V. | Method of atomic layer etching using functional group-containing fluorocarbon |
| US10727073B2 (en) | 2016-02-04 | 2020-07-28 | Lam Research Corporation | Atomic layer etching 3D structures: Si and SiGe and Ge smoothness on horizontal and vertical surfaces |
| US9991128B2 (en) | 2016-02-05 | 2018-06-05 | Lam Research Corporation | Atomic layer etching in continuous plasma |
| WO2017147254A1 (en) | 2016-02-23 | 2017-08-31 | Tokyo Electron Limited | Method and system for atomic layer etching |
| US10256108B2 (en) | 2016-03-01 | 2019-04-09 | Lam Research Corporation | Atomic layer etching of AL2O3 using a combination of plasma and vapor treatments |
| US10269566B2 (en) | 2016-04-29 | 2019-04-23 | Lam Research Corporation | Etching substrates using ale and selective deposition |
| US9865484B1 (en) * | 2016-06-29 | 2018-01-09 | Applied Materials, Inc. | Selective etch using material modification and RF pulsing |
| US9837312B1 (en) | 2016-07-22 | 2017-12-05 | Lam Research Corporation | Atomic layer etching for enhanced bottom-up feature fill |
| US10566212B2 (en) | 2016-12-19 | 2020-02-18 | Lam Research Corporation | Designer atomic layer etching |
| US10692724B2 (en) | 2016-12-23 | 2020-06-23 | Lam Research Corporation | Atomic layer etching methods and apparatus |
| US10559461B2 (en) | 2017-04-19 | 2020-02-11 | Lam Research Corporation | Selective deposition with atomic layer etch reset |
| US9997371B1 (en) | 2017-04-24 | 2018-06-12 | Lam Research Corporation | Atomic layer etch methods and hardware for patterning applications |
| US10832909B2 (en) | 2017-04-24 | 2020-11-10 | Lam Research Corporation | Atomic layer etch, reactive precursors and energetic sources for patterning applications |
| US10494715B2 (en) | 2017-04-28 | 2019-12-03 | Lam Research Corporation | Atomic layer clean for removal of photoresist patterning scum |
| US10796912B2 (en) | 2017-05-16 | 2020-10-06 | Lam Research Corporation | Eliminating yield impact of stochastics in lithography |
| US10763083B2 (en) | 2017-10-06 | 2020-09-01 | Lam Research Corporation | High energy atomic layer etching |
| US20190131130A1 (en) | 2017-10-31 | 2019-05-02 | Lam Research Corporation | Etching metal oxide substrates using ale and selective deposition |
-
2019
- 2019-03-15 CN CN201980024060.8A patent/CN111937122A/en active Pending
- 2019-03-15 WO PCT/US2019/022520 patent/WO2019190781A1/en not_active Ceased
- 2019-03-15 US US16/976,737 patent/US11450513B2/en active Active
- 2019-03-15 KR KR1020247006335A patent/KR20240029787A/en not_active Ceased
- 2019-03-15 EP EP19778362.4A patent/EP3776636B1/en active Active
- 2019-03-15 KR KR1020207031392A patent/KR102642011B1/en active Active
-
2022
- 2022-08-19 US US17/821,107 patent/US20220392747A1/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040209476A1 (en) * | 2003-04-17 | 2004-10-21 | Applied Materials, Inc. | Method of fabricating a magneto-resistive random access memory (MRAM) device |
| US20060016781A1 (en) * | 2004-07-26 | 2006-01-26 | Kenichi Kuwabara | Dry etching method |
| US20160308112A1 (en) * | 2015-04-20 | 2016-10-20 | Lam Research Corporation | Dry plasma etch method to pattern mram stack |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US12444651B2 (en) | 2009-08-04 | 2025-10-14 | Novellus Systems, Inc. | Tungsten feature fill with nucleation inhibition |
| US11721558B2 (en) | 2016-12-19 | 2023-08-08 | Lam Research Corporation | Designer atomic layer etching |
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| US20210005425A1 (en) | 2021-01-07 |
| EP3776636B1 (en) | 2025-05-07 |
| CN111937122A (en) | 2020-11-13 |
| KR20200128185A (en) | 2020-11-11 |
| WO2019190781A1 (en) | 2019-10-03 |
| KR102642011B1 (en) | 2024-02-27 |
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| US11450513B2 (en) | 2022-09-20 |
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| EP3776636A1 (en) | 2021-02-17 |
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