US20210286732A1

US20210286732A1 - Multi-way cache memory access

Info

Publication number: US20210286732A1
Application number: US16/817,609
Authority: US
Inventors: Bassam S. Kamand; Waleed Younis; Ramon ZUNIGA; Jagadish Rongali
Original assignee: Shenzhen Goodix Technology Co Ltd
Current assignee: Shenzhen Goodix Technology Co Ltd
Priority date: 2020-03-13
Filing date: 2020-03-13
Publication date: 2021-09-16
Anticipated expiration: 2040-03-13
Also published as: CN114072776A; CN114072776B; EP3977294B1; EP3977294A1; US20220066942A1; CN117950725A; CN117950725B; US11176051B2; US11544199B2; EP3977294A4; WO2021180186A1

Abstract

A cache memory is disclosed. The cache memory includes an instruction memory portion having a plurality of instruction memory locations configured to store instruction data encoding a plurality of CPU instructions. The cache memory also includes a tag memory portion having a plurality of tag memory locations configured to store tag data encoding a plurality of RAM memory address ranges the CPU instructions are stored in. The instruction memory portion includes a single memory circuit having an instruction memory array and a plurality of instruction peripheral circuits communicatively connected with the instruction memory array. The tag memory portion includes a plurality of tag memory circuits, where each of the tag memory circuits includes a tag memory array, and a plurality of tag peripheral circuits communicatively connected with the tag memory array.

Description

CROSS-REFERENCES TO RELATED APPLICATIONS

Field of the Invention

The present application generally pertains to generating cache memory, and more particularly to cache memory architectures which use low area.

BACKGROUND OF THE INVENTION

Cache memories are used in computer systems to reduce instruction access time for frequently used instructions. Central Processing Unit (CPU) executable instructions are stored in RAM, and are available for access by the CPU, as needed. Some, but not all, instructions, for example recently used instructions, are additionally stored in the cache memory. Because the cache memory is faster than RAM, the cache memory is preferred, and is used if the instruction needed by the CPU is stored therein. If the instruction needed by the CPU is not stored in the cache memory, the instruction is retrieved from the RAM.
Conventional cache memories require large amounts of die area to implement. Improved cache memories requiring less area are needed in the art.

BRIEF SUMMARY OF THE INVENTION

One inventive aspect is a cache memory. The cache memory includes an instruction memory portion having a plurality of instruction memory locations configured to store instruction data encoding a plurality of CPU instructions. The cache memory also includes a tag memory portion having a plurality of tag memory locations configured to store tag data encoding a plurality of RAM memory address ranges the CPU instructions are stored in. The instruction memory portion includes a single memory circuit having an instruction memory array and a plurality of instruction peripheral circuits communicatively connected with the instruction memory array. The tag memory portion includes a plurality of tag memory circuits, where each of the tag memory circuits includes a tag memory array, and a plurality of tag peripheral circuits communicatively connected with the tag memory array.
Another inventive aspect is a computer system. The computer system includes a CPU configured to execute CPU instructions, a RAM configured to store first representations of the CPU instructions, and a cache memory. The cache memory includes an instruction memory portion having a plurality of instruction memory locations configured to store instruction data encoding a plurality of CPU instructions. The cache memory also includes a tag memory portion having a plurality of tag memory locations configured to store tag data encoding a plurality of RAM memory address ranges the CPU instructions are stored in. The instruction memory portion includes a single memory circuit having an instruction memory array and a plurality of instruction peripheral circuits communicatively connected with the instruction memory array. The tag memory portion includes a plurality of tag memory circuits, where each of the tag memory circuits includes a tag memory array, and a plurality of tag peripheral circuits communicatively connected with the tag memory array.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic flowchart illustrating

FIG. 2 is a schematic illustration of a cache memory according to some embodiments.

FIG. 3 illustrates a timing diagram schematically illustrating certain timing relationships for various operations of a cache memory.

FIG. 4 is a schematic illustration of a comparison circuit, which is configured to identify which of the M ways has the instruction requested by a CPU.

FIG. 5 illustrates a timing diagram schematically illustrating certain timing relationships for various operations of a cache memory and a comparison circuit.

FIG. 6 is a schematic illustration of an instruction memory portion of a cache memory according to some embodiments.

FIG. 7 illustrates a timing diagram schematically illustrating certain timing relationships for various operations instruction of a memory portion of a cache memory.

FIG. 8 illustrates a timing diagram schematically illustrating another embodiment of certain timing relationships for various operations of a cache memory.

FIG. 9 is a chart illustrating cache memory area and power improvement achieved using an embodiment of a cache memory using inventive aspects discussed herein as compared with a traditional cache memory.

DETAILED DESCRIPTION OF THE INVENTION

Particular embodiments of the invention are illustrated herein in conjunction with the drawings.
Various details are set forth herein as they relate to certain embodiments. However, the invention can also be implemented in ways which are different from those described herein. Modifications can be made to the discussed embodiments by those skilled in the art without departing from the invention. Therefore, the invention is not limited to particular embodiments disclosed herein.
FIG. 1 is a schematic illustration of a computer system 100. Computer system 100 includes CPU 110, random access memory (RAM) 120, and cache memory 130.
The information stored in a cache memory 130 includes instructions which the CPU 110 may need for executing a software application. The information stored in the cache memory 130 also includes information for each particular instruction identifying a portion or address range of the RAM 120 the particular instruction is stored in. The identifying information is called a tag. Other information may additionally be stored in the cache memory, as understood by those of skill in the art.
As understood by those of skill in the art, in computer systems, cache memories may be subdivided into multiple ways, where each way is independently written and read. To fetch an instruction from the cache memory, the CPU provides an address to the cache memory. The CPU address includes a tag portion and an index portion. In some embodiments, the CPU address may additionally include other information, such as an offset, as understood by those of skill in the art.
In a conventional cache memory, the index portion of the CPU address is used to read one instruction and its corresponding tag from each of the ways. Accordingly, a number of instructions corresponding to the number of ways, along with each of their corresponding tags, are read from the cache memory based on the index portion of the CPU address.
In the conventional cache memory, the tags associated with the instructions are each compared to the tag portion of the CPU address. If one of the tags matches the tag portion of the CPU address, the instruction corresponding with the matching tag is provided to the CPU as the instruction requested by the CPU. If none of the tags match the tag portion of the CPU address, the instruction requested by the CPU is not located in the cache memory, and must, instead, be retrieved from RAM.
FIG. 2 is a schematic illustration of a cache memory 200 according to some embodiments. Cache memory 200 may be used in computer system 100 as cache memory 130. Cache memory 200 includes M ways 230, where each way includes a tag memory portion 210 and an instruction memory portion 220.
In some embodiments, the ways of cache memory 200 include one or more other memory portions, as understood by those of skill in the art. For example, in some embodiments, each way includes a valid bit portion, where each bit in the valid bit portion indicates whether a particular instruction is valid, as understood by those of skill in the art.
Instruction memory portion 220 is written with data corresponding with CPU instructions. In addition, tag memory portion 210 is written with data corresponding with portions or address ranges of the RAM the instructions are stored in.
Instruction memory portion 220 is a single memory circuit, despite being abstractly or conceptually segmented into the M ways. Accordingly, instruction memory portion 220 includes an array of memory cells which receives signals from and provides signals to a number of peripheral circuits which are used to access the memory cells for writing and for reading instruction information. As understood by those of skill in the art, the peripheral circuits may include, for example, an address decoder, sense amplifiers, a column multiplexer, and output buffers. In some embodiments, the peripheral circuits may include one or more other circuits. The memory cells are each constituent to a particular one of the ways. The peripheral circuits, however, may each receive signals from or provide signals to memory cells of all of the ways.
Tag memory portion 210 includes a single memory circuit for each of the ways. Accordingly each way includes an array of memory cells which receives signals from and provides signals to a number of peripheral circuits which are used to access the memory cells for writing and for reading tag information. As understood by those of skill in the art, the peripheral circuits may include, for example, an address decoder, sense amplifiers, a column multiplexer, and output buffers. In some embodiments, the peripheral circuits may include one or more other circuits. The memory cells and the peripheral circuits are each constituent to a particular one of the ways.
Cache memory 200 is structured so that, to fetch an instruction therefrom, the CPU (e.g. CPU 110) provides an address to the cache memory 200. The CPU address includes a tag portion and an index portion. In some embodiments, the CPU address may additionally include other information, such as an offset, as understood by those of skill in the art.
The index portion of the CPU address identifies a memory location in each of the tag memory portions 210(0) to 210(M−1) of the M ways. The M tag memory portions 210(0) to 210(M−1) are each associated with a memory location in a corresponding one of the instruction memory portions 220(0) to 220(M−1) of the M ways. The association of the M tag memory portions 210(0) to 210(M−1) and the instruction memory portions 220(0) to 220(M−1) of the M ways is instantiated in hardware at least by each of the M tag memory portions 210(0) to 210(M−1) and its associated instruction memory portion 220(0) to 220(M−1) having an address partially or wholly identified by the index portion of the CPU address.
The M tag memory portions 210(0) to 210(M−1) identified by the index portion of the CPU address are read to retrieve M tags. The M tags are each compared with the tag portion of the CPU address. If one of the M tags matches the tag portion of the CPU address, the way having the matching tag is identified. If none of the tags matches the tag portion of the CPU address, the instruction requested by the CPU is not located in the cache memory, and must be retrieved from RAM.
The index portion of the CPU address is then used to read an instruction from the instruction memory portion 220(x) of the identified way. The instruction read from the instruction memory portion 220(x) of the identified way is returned to the CPU as the instruction requested by the CPU.
FIG. 3 illustrates a timing diagram 300 schematically illustrating certain timing relationships for various operations of cache memory 200. Timing diagram 300 illustrates CPU clock waveform 310, tag clock waveform 320, instruction clock waveform 330, and instruction waveform 340. The illustrated waveforms correspond with clocks generated by clock generation circuits understood by those of skill in the art.
CPU clock waveform 310 illustrates a representation of a CPU clock used by the CPU 110. As understood by those of skill in the art, the CPU clock represented by CPU clock waveform 310 may be used by CPU 110, for example, to receive input data, to execute instructions, and to generate output data. CPU 110 may use the CPU clock represented by CPU clock waveform 310 to additionally perform other operations. CPU 110 may use additional clocks (not shown).
Tag clock waveform 320 illustrates a representation of a tag clock used by tag memory portion 210. The tag clock represented by tag clock waveform 320 may be used by tag memory portion 210, for example, for writing and reading tag data to and from tag memory portion 210.
Instruction clock waveform 330 illustrates a representation of an instruction clock used by instruction memory portion 220. The instruction clock represented by instruction clock waveform 330 may be used by instruction memory portion 220, for example, for writing and reading instruction data to and from instruction memory portion 220.
Instruction waveform 340 illustrates a representation of instruction data. The instruction data encodes instructions which are executable by CPU 110, and which are provided to CPU 110 by cache memory 200, for example, for execution by CPU 110.
As illustrated in FIG. 3, during a first portion of a CPU clock period, the tag clock is active (high). While the tag clock is active, the M tag memory portions 210(0) to 210(M−1) identified by the index portion of the CPU address are read to retrieve M tags. In addition, while the tag clock is active, the M tags are each compared with the tag portion of the CPU address. If one of the M tags matches the tag portion of the CPU address, the way having the matching tag is identified.
During a second, subsequent, portion of the CPU clock period, the instruction clock is active (high). During the second portion of the CPU clock period, the index portion of the CPU address is used to perform a read operation on the instruction memory portion 220(x) of the identified way to read an instruction therefrom. Once read, the instruction read from the instruction memory portion 220(x) of the identified way is returned to the CPU 110 as the instruction requested by the CPU 110.
Timing diagram 300 schematically illustrates an embodiment of certain timing relationships for CPU clock waveform 310, tag clock waveform 320, instruction clock waveform 330, and instruction waveform 340. Alternative timing relationships may alternatively be used. For example, the phase relationship between CPU clock waveform 310 and either or both of tag clock waveform 320 and instruction clock waveform 330 may be modified. Additionally or alternatively, in some embodiments, the active states of either or both of tag clock waveform 320 and instruction clock waveform 330 are low.
FIG. 4 is a schematic illustration of a comparison circuit 400, which is configured to identify which of the M ways has the instruction requested by the CPU 110. Comparison circuit 400 includes tag comparators 410(0) to 410(M−1) and tri-state driver arrays 420(0) to 420(M−1). In some embodiments, alternative comparison circuits are used.
As illustrated, comparison circuit 400 receives the tag portion of the CPU address at bus CPUTAG. In addition, comparison circuit receives M tags at tag busses TAG(0) to TAG(M−1). Each of the M tags is generated as the result of reading one of the tag memory portions 210(0) to 210(M−1) of the M ways.
Each of tag comparators 410(0) to 410(M−1) is configured to compare one of the M tags with the tag portion of the CPU address at bus CPUTAG. At most one of the M tags matches the tag portion of the CPU address.
Tri-state driver arrays 420(0) to 420(M−1) each have data inputs which receive data identifying one of the M ways. The data inputs of each of the tri-state driver arrays 420(0) to 420(M−1) are connected to one of the way identification busses WAY(0) to WAY(M−1). In addition, tri-state driver arrays 420(0) to 420(M−1) each receive an indication of whether a particular one of the M tags at tag busses TAG(0) to TAG(M−1) matches the tag portion of the CPU address at bus CPUTAG.
The tri-state driver arrays receiving indications that the particular one of the M tags associated therewith does not match the tag portion of the CPU address at bus CPUTAG have outputs which are tri-stated, and are high impedance. The tri-state driver receiving the indication that the particular one of the M tags associated therewith does match the tag portion of the CPU address at bus CPUTAG, outputs data at way bus WAY(X) indicating the particular way identified at its data input.
Accordingly, the tri-state driver arrays 420(0) to 420(M−1) perform a multiplexing function which passes data identifying the particular way having tag data matching the tag portion of the CPU address. As understood by those of skill in the art, alternative circuits performing the multiplexing function may alternatively be used.
FIG. 5 illustrates a timing diagram 500 schematically illustrating certain timing relationships for various operations of cache memory 200 and comparison circuit 400. Timing diagram 500 illustrates CPU clock waveform 510, tag clock waveform 520, tag data waveform 530, CPU tag data waveform 540, and way bus data waveform 550.
CPU clock waveform 510 illustrates a representation of a CPU clock used by the CPU 110, and has characteristics similar or identical to CPU clock waveform 310 of FIG. 3.
Tag clock waveform 520 illustrates a representation of a tag clock used by tag memory portion 210, and has characteristics similar or identical to tag clock waveform 320 of FIG. 3.
Tag data waveform 530 illustrates a representation of tag data identifying the M tags at tag busses TAG(0) to TAG(M−1).
CPU tag data waveform 540 illustrates a representation of the tag portion of the CPU address at bus CPUTAG.
Way bus data waveform 550 illustrates a representation of way identification data at way bus WAY(X).
During a first portion of a CPU clock period, the tag clock is active (high). In response to the tag clock being active, the M tag memory portions 210(0) to 210(M−1) identified by the index portion of the CPU address are read to retrieve M tags. The M tags are respectively represented by data at tag busses TAG(0) to TAG(M−1). In addition, while the tag clock is active, the M tags are each compared with the tag portion of the CPU address by comparators 410(0) to 410(M−1).
Furthermore, while the tag clock is active, tri-state driver arrays 420(0) to 420(M−1) each receive data identifying one of the M ways from the way identification busses WAY(0) to WAY(M−1). In addition, tri-state driver arrays 420(0) to 420(M−1) each receive an indication from a corresponding comparator 410 indicating whether a particular one of the M tags at tag busses TAG(0) to TAG(M−1) matches the tag portion of the CPU address at bus CPUTAG.
In addition, while the tag clock is active, the tri-state driver array receiving the indication that the particular one of the M tags associated therewith matches the tag portion of the CPU address at bus CPUTAG, outputs way identification data at way bus WAY(X) identifying the particular way identified at its data input.
Timing diagram 700 schematically illustrates an embodiment of certain timing relationships for CPU clock waveform 510, tag clock waveform 520, tag data waveform 530, CPU tag data waveform 540, and way bus data waveform 550. Alternative timing relationships may alternatively be used. For example, the phase relationship between CPU clock waveform 510 and tag clock waveform 520 may be modified. Additionally or alternatively, in some embodiments, the active state of tag clock waveform 520 is low.
FIG. 6 is a schematic illustration of an instruction memory portion 220 of a cache memory 200 according to some embodiments. Instruction memory portion 220 includes memory locations for instructions stored in all of the ways of cache memory 200. Accordingly, instruction memory portion 220 includes stores instructions in memory locations 220(0) to 220(M*L−1), where M is equal to the number of ways, and L is equal to the length (number of instruction memory locations) in each way.
As illustrated, instruction memory portion 220 receives an address. Instruction memory portion 220 is configured to be read so as to output the instruction stored in the memory location associated with the received address.
The received address includes a tag portion and an index portion.
The tag portion is generated by comparison circuit 400 and is the formed by the way data at way bus WAY(X) indicating the particular way identified as having tag data matching the tag portion of the CPU address.
The index portion of the received address is formed by the index portion of the CPU address.
FIG. 7 illustrates a timing diagram 700 schematically illustrating certain timing relationships for various operations instruction memory portion 220 of cache memory 200. Timing diagram 700 illustrates CPU clock waveform 710, instruction clock waveform 720, index data waveform 730, way data waveform 740, and instruction data waveform 750.
CPU clock waveform 710 illustrates a representation of a CPU clock used by the CPU 110, and has characteristics similar or identical to CPU clock waveform 310 of FIG. 3.
Instruction clock waveform 720 illustrates a representation of an instruction clock used by instruction memory portion 220, and has characteristics similar or identical to instruction clock waveform 320 of FIG. 3.
Index data waveform 730 illustrates a representation of the index portion of the CPU address at bus CPUTAG.
Way data waveform 740 illustrates a representation of way identification data at way bus WAY(X).
Instruction data waveform 750 illustrates a representation of the instruction read from instruction memory portion 220.
During a second portion of the CPU clock period, subsequent to the first portion of the CPU clock period discussed with reference to FIG. 5, the instruction clock is active (high). In response to the instruction clock being active, the way identification data and the index portion of the CPU address are used to read an instruction from the instruction memory portion 220. Once read, the instruction read from the instruction memory portion 220 is returned to the CPU 110 as the instruction requested by the CPU 110.
Timing diagram 700 schematically illustrates an embodiment of certain timing relationships for CPU clock waveform 710, instruction clock waveform 720, index data waveform 730, way data waveform 740, and instruction data waveform 750. Alternative timing relationships may alternatively be used. For example, the phase relationship between CPU clock waveform 710 and instruction clock waveform 720 may be modified. Additionally or alternatively, in some embodiments, the active state of instruction clock waveform 720 is low.
FIG. 8 illustrates a timing diagram 800 schematically illustrating another embodiment of certain timing relationships for various operations of cache memory 200. Timing diagram 800 illustrates CPU clock waveform 810, N×CPU clock waveform 810, tag clock waveform 820, instruction clock waveform 830, and instruction waveform 840. The illustrated waveforms correspond with clocks generated by clock generation circuits understood by those of skill in the art.
CPU clock waveform 810 illustrates a representation of a CPU clock used by the CPU 110. As understood by those of skill in the art, the CPU clock represented by CPU clock waveform 810 may be used by CPU 110, for example, to receive input data, to execute instructions, and to generate output data. CPU 110 may use the CPU clock represented by CPU clock waveform 810 to additionally perform other operations. CPU 110 may use additional clocks (not shown).
N×CPU clock waveform 815 illustrates a representation of a clock which has a frequency which is a multiple of the frequency of the CPU clock. In this embodiment, the frequency of the clock of N×CPU clock waveform 815 has a frequency which is three times the frequency of the CPU clock. The clock of N×CPU clock waveform 815 may be generated based on the CPU clock using circuits known to those of skill in the art.
Tag clock waveform 820 illustrates a representation of a tag clock used by tag memory portion 210. The tag clock represented by tag clock waveform 820 may be used by tag memory portion 210, for example, for writing and reading tag data to and from tag memory portion 210.
Instruction clock waveform 830 illustrates a representation of an instruction clock used by instruction memory portion 220. The instruction clock represented by instruction clock waveform 830 may be used by instruction memory portion 220, for example, for writing and reading instruction data to and from instruction memory portion 220.
Instruction waveform 840 illustrates a representation of instruction data. The instruction data encodes instructions which are executable by CPU 110, and which are provided to CPU 110 by cache memory 200, for example, for execution by CPU 110.
As illustrated in FIG. 8, during a first portion of a CPU clock period, the tag clock is active (high). While the tag clock is active, the M tag memory portions 210(0) to 210(M−1) identified by the index portion of the CPU address are read to retrieve M tags. In addition, while the tag clock is active, the M tags are each compared with the tag portion of the CPU address. If one of the M tags matches the tag portion of the CPU address, the way having the matching tag is identified.
During a second, subsequent, portion of the CPU clock period, the instruction clock is active (high). During the second portion of the CPU clock period, the index portion of the CPU address is used to perform a read operation on the instruction memory portion 220(x) of the identified way to read an instruction therefrom. Once read, the instruction read from the instruction memory portion 220(x) of the identified way is returned to the CPU 110 as the instruction requested by the CPU 110.
Timing diagram 800 schematically illustrates an embodiment of certain timing relationships for CPU clock waveform 810, N×CPU clock waveform 815, tag clock waveform 820, instruction clock waveform 830, and instruction waveform 840. Alternative timing relationships may alternatively be used. For example, the phase relationship between CPU clock waveform 810 and an of N×CPU clock waveform 815, tag clock waveform 820, and instruction clock waveform 830 may be modified. Additionally or alternatively, in some embodiments, the active states of either or both of tag clock waveform 820 and instruction clock waveform 830 are low.

Comparative Example

FIG. 9 is a chart illustrating cache memory area and power improvement achieved using an embodiment of a cache memory using inventive aspects discussed herein as compared with a traditional cache memory. The new and old cache memories are each 8 Kbyte 4-way running a 32 MHz CPU clock. The new cache memory uses a 3×CPU clock running at 96 MHz.
As illustrated in FIG. 9, the new cache memory uses 51% less area and 72% less power.
Though the present invention is disclosed by way of specific embodiments as described above, those embodiments are not intended to limit the present invention. Based on the methods and the technical aspects disclosed herein, variations and changes may be made to the presented embodiments by those of skill in the art without departing from the spirit and the scope of the present invention.

Claims

1. A cache memory, comprising:

an instruction memory portion, comprising a plurality of instruction memory locations configured to store instruction data encoding a plurality of CPU instructions; and

a tag memory portion, comprising a plurality of tag memory locations configured to store tag data encoding a plurality of RAM memory address ranges the CPU instructions are stored in,

wherein the instruction memory portion comprises a single memory circuit comprising an instruction memory array and a plurality of instruction peripheral circuits communicatively connected with the instruction memory array and configured to access the instruction memory array to cause the instruction memory array to be read and written, and

wherein the tag memory portion comprises a plurality of tag memory circuits, wherein each of the tag memory circuits comprises:

a tag memory array, and

a plurality of tag peripheral circuits communicatively connected with the tag memory array and configured to access the tag memory array to cause the tag memory array to be read and written,

wherein each tag memory array and each tag peripheral circuit is constituent to a particular one of the tag memory circuits.

2. The cache memory of claim 1, segmented into M ways, wherein each of the tag memory circuits of the tag memory portion is configured to store tag data of a separate one of the M ways, and wherein M is an integer.

3. The cache memory of claim 2, wherein the single memory circuit of the instruction memory portion is configured to store instruction data of each of the M ways.

4. The cache memory of claim 2, wherein tag memory locations of each of the tag memory circuits of the tag memory portion are configured to be read during a first time period, and wherein the read tag memory locations are each identified with an index portion of a CPU address.

5. The cache memory of claim 4, further comprising a comparison circuit configured to compare the tag data of each of the read tag memory locations with a tag portion of the CPU address.

6. The cache memory of claim 5, wherein the tag portion of the CPU address identifies a RAM memory address range in which a first representation of a particular CPU instruction is stored, wherein a second representation of the particular CPU instruction is stored in the instruction memory portion.

7. The cache memory of claim 5, further comprising a multiplexer circuit configured to provide tag address data to the instruction memory portion, wherein the provided tag address data identifies a particular way having tag data matching the tag portion of the CPU address.

8. The cache memory of claim 7, wherein an instruction memory location of the single memory circuit of the instruction memory portion is configured to be read during a second time period, wherein the second time period is subsequent to the first time period, and wherein the read instruction memory location is identified by a combination of the tag address data read during the first time period and the index portion of the CPU address.

9. The cache memory of claim 8, wherein the first time period and the second time period occur within a single clock cycle of a CPU clock period.

10. The cache memory of claim 9, wherein a sum of a duration of the first time period and a duration of the second time period is less than a duration of the single clock cycle of the CPU clock period.

11. A computer system, comprising:

a central processing unit (CPU) configured to execute CPU instructions;

a random access memory (RAM) configured to store first representations of the CPU instructions; and

a cache memory, comprising:

an instruction memory portion, comprising a plurality of instruction memory locations storing second representations of a subset of the CPU instructions; and

a tag memory portion, comprising a plurality of tag memory locations storing tag data encoding a plurality of RAM memory address ranges the first representations of the subset of CPU instructions are stored in,

a tag memory array, and

12. The computer system of claim 11, wherein the cache memory is segmented into M ways, wherein each of the tag memory circuits of the tag memory portion is configured to store tag data of a separate one of the M ways, and wherein M is an integer.

13. The computer system of claim 12, wherein the single memory circuit of the instruction memory portion is configured to store instruction data of each of the M ways.

14. The computer system of claim 12, wherein tag memory locations of each of the tag memory circuits of the tag memory portion are configured to be read during a first time period, and wherein the read tag memory locations are each identified with an index portion of a CPU address.

15. The computer system of claim 14, wherein the cache memory further comprises a comparison circuit configured to compare the tag data of each of the read tag memory locations with a tag portion of the CPU address.

16. The cache memory of claim 15, wherein the tag portion of the CPU address identifies a RAM memory address range in which a first representation of a particular CPU instruction is stored, wherein a second representation of the particular CPU instruction is stored in the instruction memory portion.

17. The computer system of claim 15, wherein the cache memory further comprises a multiplexer circuit configured to provide tag address data to the instruction memory portion, wherein the provided tag address data identifies a particular way having tag data matching the tag portion of the CPU address.

18. The computer system of claim 17, wherein an instruction memory location of the single memory circuit of the instruction memory portion is configured to be read during a second time period, wherein the second time period is subsequent to the first time period, and wherein the read instruction memory location is identified by a combination of the tag address data read during the first time period and the index portion of the CPU address.

19. The computer system of claim 18, wherein the first time period and the second time period occur within a single clock cycle of a CPU clock period.

20. The computer system of claim 19, wherein a sum of a duration of the first time period and a duration of the second time period is less than a duration of the single clock cycle of the CPU clock period.