[go: up one dir, main page]

US20210210464A1 - Package structure and method of manufacturing the same - Google Patents

Package structure and method of manufacturing the same Download PDF

Info

Publication number
US20210210464A1
US20210210464A1 US17/207,748 US202117207748A US2021210464A1 US 20210210464 A1 US20210210464 A1 US 20210210464A1 US 202117207748 A US202117207748 A US 202117207748A US 2021210464 A1 US2021210464 A1 US 2021210464A1
Authority
US
United States
Prior art keywords
die
encapsulant
connector
layer
package structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US17/207,748
Inventor
Chi-Yang Yu
Chin-Liang Chen
Chien-Hsun Lee
Kuan-Lin HO
Yu-Min LIANG
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority to US17/207,748 priority Critical patent/US20210210464A1/en
Publication of US20210210464A1 publication Critical patent/US20210210464A1/en
Priority to US18/786,606 priority patent/US20240387457A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135Double encapsulation or coating and encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565Moulds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293Organic, e.g. plastic
    • H01L23/295Organic, e.g. plastic containing a filler
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142Sealing arrangements between parts, e.g. adhesion promotors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386Geometry or layout of the interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20Structure, shape, material or disposition of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0655Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, the devices being individual devices of subclass H10D or integrated devices of class H10
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/11001Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11002Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for supporting the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13025Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/215Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/2901Shape
    • H01L2224/29016Shape in side view
    • H01L2224/29017Shape in side view being non uniform along the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29186Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/82005Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821Forming a build-up interconnect
    • H01L2224/82101Forming a build-up interconnect by additive methods, e.g. direct writing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1203Rectifying Diode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • H01L2924/143Digital devices
    • H01L2924/1433Application-specific integrated circuit [ASIC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • H01L2924/143Digital devices
    • H01L2924/1434Memory
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Definitions

  • FIG. 1A to FIG. 1F are schematic cross-sectional views illustrating a method of forming a package structure according to a first embodiment of the disclosure.
  • FIG. 2A to FIG. 2F are schematic cross-sectional views illustrating a method of forming a package structure according to a second embodiment of the disclosure.
  • FIG. 3A to FIG. 3F are schematic cross-sectional views illustrating a method of forming a package structure according to a third embodiment of the disclosure.
  • FIG. 4 is a schematic cross-sectional view illustrating a package structure according to some embodiments of the disclosure.
  • FIG. 5 is a schematic cross-sectional view illustrating a package structure according to some embodiments of the disclosure.
  • FIG. 6 is a flow chart illustrating a method of forming a package structure according to some embodiments of the disclosure.
  • first and first features are formed in direct contact
  • additional features may be formed between the second and first features, such that the second and first features may not be in direct contact
  • present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
  • spatially relative terms such as “beneath”, “below”, “lower”, “on”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the FIG.s.
  • the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the FIG.s.
  • the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
  • testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices.
  • the testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like.
  • the verification testing may be performed on intermediate structures as well as the final structure.
  • the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs.
  • FIG. 1A to FIG. 1F are schematic cross-sectional views illustrating a forming method of a package structure according to a first embodiment of the disclosure.
  • a carrier 10 is provided.
  • the carrier 10 may be a glass carrier, a ceramic carrier, or the like.
  • the carrier 10 has a de-bonding layer 11 formed thereon.
  • the de-bonding layer 11 is formed by, for example, a spin coating method.
  • the de-bonding layer 11 may be formed of an adhesive such as an Ultra-Violet (UV) glue, a Light-to-Heat Conversion (LTHC) glue, or the like, or other types of adhesives.
  • UV Ultra-Violet
  • LTHC Light-to-Heat Conversion
  • the de-bonding layer 11 is decomposable under the heat of light to thereby release the carrier 10 from the overlying structures that will be formed in subsequent steps.
  • a die 120 a and a die 20 b are attached side by side to the de-bonding layer 11 over the carrier 10 through an adhesive layer 12 such as a die attach film (DAF), silver paste, or the like.
  • the die 120 a and the die 20 b may respectively be an application-specific integrated circuit (ASIC) chip, an analog chip, a sensor chip, a wireless and radio frequency chip, a voltage regulator chip, a memory chip or the like.
  • the die 120 a and the die 20 b may be the same types of dies or the different types of dies.
  • the two dies 120 a and 20 b are two small die partitions with different function of a larger single die.
  • the size (refers to the height and/or the width) of the two dies 120 a and 20 b may be the same or different. In some embodiments, a gap 21 is existed between the two dies 120 a and 20 b.
  • the number of the dies attached to the carrier 10 is not limited to that is shown in FIG. 1A . In some other embodiments, one die or more than two dies are attached to the carrier 10 .
  • the two dies 120 a and 20 b have similar structures.
  • the die 120 a is taken for example.
  • the die 120 a includes a substrate 13 a, a pad 14 a, a passivation layer 15 a, conductive posts 19 a and a protection layer 18 a.
  • the substrate 13 is made of silicon or other semiconductor materials. Alternatively or additionally, the substrate 13 includes other elementary semiconductor materials such as germanium, gallium arsenic, or other suitable semiconductor materials. In some embodiments, the substrate 13 may further include other features such as various doped regions, a buried layer, and/or an epitaxy layer. Moreover, in some embodiments, the substrate 13 is made of an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. Furthermore, the substrate 13 may be a semiconductor on insulator such as silicon on insulator (SOI) or silicon on sapphire.
  • SOI silicon on insulator
  • the pads 14 a may be a part of an interconnection structure (not shown) and electrically connected to the devices (not shown) formed on the substrate 13 a.
  • the devices may be active devices, passive devices, or a combination thereof.
  • the devices are integrated circuit devices.
  • the passivation layer 15 a is formed over the substrate 13 a and covers a portion of the pads 14 a. A portion of the pads 14 a is exposed by the passivation layer 15 a and serves as an external connection of the die 120 a.
  • the passivation layer 15 a includes a first passivation layer 8 a and a second passivation layer 9 a on the first passivation layer 8 a.
  • the material of the first passivation layer 8 a and the material of the second passivation layer 9 a may be the same or different.
  • the second passivation layer 9 a is also referred as a post-passivation layer, and is optionally formed.
  • the conductive posts 19 a are formed on and electrically connected to the pads 14 a exposed by the passivation layer 15 a.
  • the conductive post 19 includes a first portion 16 a and a second portion 17 a.
  • the first portion 16 a is embedded in and laterally covered by the passivation layer 15 a.
  • the second portion 17 a is on the first portion 16 a and the passivation layer 15 a.
  • the second portion 17 a covers a portion of the top surface of the passivation layer 15 a.
  • the second portion 17 a is on the first portion 16 a and does not cover the top surface of the passivation layer 15 a.
  • the second portion 17 a is also referred as a connector.
  • the conductive posts 19 a include solder bumps, gold bumps, copper bumps, copper posts, copper pillars, or the like.
  • the protection layer 18 a is formed over the passivation layer 15 a and aside the connectors 17 a to cover the sidewalls of the connectors 17 a.
  • the passivation layer 15 a and the protection layer 18 a respectively include an insulating material such as silicon oxide, silicon nitride, polymer, or a combination thereof.
  • the polymer includes polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof or the like, for example.
  • the passivation layer 15 a and the protection layer 18 a are free of fillers.
  • the materials of the passivation layer 15 a and the protection layer 18 a may be the same or different.
  • the top surface of the protection layer 18 a is substantially level with the top surface of the connectors 17 a.
  • the die 20 b includes a substrate 13 b, a pad 14 b, a passivation layer 15 b, and a conductive post 19 b.
  • the passivation layer 15 b includes a first passivation layer 8 b and a second passivation layer 9 b.
  • the second passivation layer 9 b is also referred as a post-passivation layer and is optionally formed.
  • the conductive post 19 b includes a first portion 16 b and a second portion 17 b.
  • the second portion 17 b is also refereed as a connector.
  • the material and the structural characteristics of the substrate 13 b, the pad 14 b, the passivation layer 15 b, and the conductive post 19 b of the die 20 b are substantially the same as or different from those of the substrate 13 a, the pad 14 a, the passivation layer 15 a, the conductive post 19 a of the die 120 a .
  • the die 20 b differs from the die 120 a in that, no protection layer is formed aside the connectors 17 b . That is to say, the sidewalls of the connectors 17 b are not covered by a protection layer, but exposed.
  • the top surfaces of the connectors 17 a and the top surfaces of the connectors 17 b are substantially coplanar with each other, but the disclosure is not limited thereto. In some other embodiments, the top surfaces of the connectors 17 a and the top surfaces of the connectors 17 b may be not coplanar with each other.
  • the dies 120 a and 20 b respectively has a first sidewall 40 a and a second sidewall 40 b opposite to each other.
  • the first sidewall 40 a of the die 120 a or 20 b is the sidewall adjacent to another die 20 b or 120 a
  • the second sidewall 40 b of the die 120 a or 20 b is the sidewall far away from another die 20 b or 120 a.
  • the first sidewalls 40 a and the second sidewalls 40 b may be straight or inclined.
  • a first encapsulant material layer 22 is formed over the carrier 10 and on the die 20 b.
  • the first encapsulant material layer 22 fills in the gap 21 between the die 120 a and the die 20 b, at least encapsulates the first sidewalls 40 a of the dies 120 a and 20 b, the top surfaces and sidewalls of the connectors 17 b of the die 20 b, and a portion of top surface of the passivation layer 15 b of the die 20 b.
  • the top surface of the passivation layer 15 b is completely covered by the first encapsulant material layer 22 , but the disclosure is not limited thereto.
  • a portion of the top surface of the passivation layer 15 b at an edge (the edge adjacent to the second sidewall 40 b ) of the die 20 b may be not covered by the first encapsulant material layer 22 (shown as the dotted line A).
  • the top surface of the die 120 a, and the second sidewall 40 b of the die 20 b are not covered by the first encapsulant material layer 22 , but the disclosure is not limited thereto.
  • the first encapsulant material layer 22 may further extend to cover the top surface of the die 120 a or/and the sidewall 40 b of the die 20 b (shown as dotted line B).
  • the first encapsulant material layer 22 is formed of an underfill material, a molding underfill material, polymer, or a combination thereof.
  • the polymer includes polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof or the like.
  • PBO polybenzoxazole
  • PI polyimide
  • BCB benzocyclobutene
  • the first encapsulant material layer 22 includes polymer and a plurality of fillers 22 ′.
  • the filler 22 ′ may be a powdered inorganic material, the filler 22 ′ may be a single element, a compound such as nitride, or a combination thereof, e.g., silica, alumina, carbon, or aluminum nitride, or mixtures thereof.
  • the filler 22 ′ is fine filler whose particle size is very small.
  • the average particle size of the filler 22 ′ ranges from 0.1 ⁇ m to 10 ⁇ m, or even smaller than 0.1 ⁇ m, for example.
  • the first encapsulant material layer 22 may be free of filler.
  • the first encapsulant material layer 22 may be formed by a dispensing process, for example. In some embodiments, after the first encapsulant material layer 22 is dispensed in the gap 21 and on the die 20 b, a curing process is further performed.
  • the surface of the first encapsulant material layer 22 is unflat.
  • the first encapsulant material layer 22 may be tapered towards the die 20 b.
  • the surface of the first encapsulant material layer 22 may have a curved profile, an inclined profile, an arced profile, or a combination thereof.
  • the surface of the first encapsulant material layer 22 is higher than the top surface of the protection layer 18 a of the die 120 a.
  • a second encapsulant material layer 23 is formed over the carrier 10 and the dies 120 a and 20 b, so as to encapsulate the second sidewalls 40 b of the dies 120 a and 20 b, the top surface of the die 120 a and the top surface of the first encapsulant material layer 22 .
  • the material of the second encapsulant material layer 23 may be the same as or different from the material of the first encapsulant material layer 22 .
  • the first encapsulant material layer 22 and the second encapsulant material layer 23 comprise the same material with different physical characteristics (e.g. particle size).
  • the second encapsulant material layer 23 includes a molding compound, for example.
  • the second encapsulant material layer 23 is formed by a process different from that of the first encapsulant material layer 22 , such as a molding process.
  • the second encapsulant material layer 23 is a composite material including a polymer and a plurality of fillers 23 ′.
  • the filler 23 ′ may be a single element, a compound such as nitride, oxide, or a combination thereof.
  • the fillers 23 ′ may comprise silicon oxide, aluminum oxide, boron nitride, alumina, silica, and the like, for example.
  • the cross-section shape of the filler 22 ′ or 23 ′ may be circle, square, rectangle, or any other shape, and the disclosure is not limited thereto.
  • the particle size of the filler 23 ′ is larger than the particle size of the filler 22 ′, herein, the particle size of the filler 22 ′ or 23 ′ refers to the diameter, length, width or height of the filler 22 ′ or 23 ′.
  • the average particle size of the filler 23 ′ ranges from 3 ⁇ m to 30 ⁇ m, or even larger than 30 ⁇ m, for example.
  • the particle size is referred to the average particle size D50, and the average particle size D50 of the filler 23 ′ is larger than the average particle size D50 of the filler 22 ′.
  • a planarization process is performed, and a portion of the second encapsulant material layer 23 and a portion of the first encapsulant material layer 22 are removed, such that the connectors 17 a of the die 120 a and the connectors 17 b of the die 20 b are exposed, and a first encapsulant 22 a and a second encapsulant 23 a are formed.
  • ones of the connectors 17 a and the connectors 17 b at a higher level are removed during the planarization process, that is, portions of the connectors 17 a and a portion of the protection layer 18 a, or portions of the connectors 17 b are also removed during the planarization process.
  • the top surfaces of the connectors 17 a and the protection layer 18 a of the die 120 a, the top surfaces of the connectors 17 b of the die 20 b, the top surface of the first encapsulant 22 a, and the top surface of the second encapsulant 23 a are substantially coplanar with each other.
  • the planarization process includes a grinding process or a polishing process, such as a chemical mechanical polishing (CMP) process.
  • CMP chemical mechanical polishing
  • the top surface of the first encapsulant 22 a is more flat than the top surface of the second encapsulant 23 a.
  • the first encapsulant 22 a is disposed in the gap 21 between the dies 120 a and 20 b, and on the passivation layer 15 b of the die 20 b , encapsulating the first sidewalls 40 a of the dies 120 a and 20 b, and sidewalls of the connectors 17 b . That is to say, the connectors 17 b of the die 20 b are laterally covered by and in contact with the first encapsulant 22 a.
  • the second encapsulant 23 a is aside and laterally encapsulants the sidewall of the first encapsulant 22 a, and the second sidewalls of the dies 120 a and 20 b.
  • an interface 24 is existed between the first encapsulant 22 a and the second encapsulant 23 a.
  • the interface 24 is on an edge of the die 20 b.
  • the interface 24 is connected to the second sidewall 40 b of the die 20 b.
  • the interface 24 and the second sidewall 40 b may be not coplanar.
  • the interface 24 is not connected to the second sidewall 40 b of the die 20 b (shown as the dotted line A′).
  • the profile of the interface 24 is inclined, curved, or arced, for example.
  • Interfaces also exist between the protection layer 18 a and the first encapsulant 22 a, and between the protection layer 18 a and the second encapsulant 23 a.
  • the interface between the protection layer 18 a and the first encapsulant 22 a and the interface between the protection layer 18 a and the second encapsulant 23 a may respectively be straight or inclined.
  • a redistribution layer (RDL) structure 26 is formed over and electrically connected to the dies 120 a and 20 b.
  • the die 120 a and the die 20 b are electrically connected to each other through the RDL structure 26 .
  • the RDL structure 26 is referred as a “front-side redistribution layer structure”, wherein the “front-side” refers to a side close to the connectors 17 a and 17 b of the dies 120 a and 20 b.
  • the RDL structure 26 includes a plurality of polymer layers PM 1 , PM 2 , PM 3 and PM 4 and a plurality of redistribution layers RDL 1 , RDL 2 , RDL 3 and RDL 4 stacked alternately.
  • the number of the polymer layers or the redistribution layers is not limited by the disclosure.
  • the redistribution layer RDL 1 penetrates through the polymer layer PM 1 and is electrically connected to the connectors 17 a and 17 b of the dies 120 a and 20 b.
  • the redistribution layer RDL 2 penetrates through the polymer layer PM 2 and is electrically connected to the redistribution layer RDL 1 .
  • the redistribution layer RDL 3 penetrates through the polymer layer PM 3 and is electrically connected to the redistribution layer RDL 2 .
  • the redistribution layer RDL 4 penetrates through the polymer layer PM 4 and is electrically connected to the redistribution layer RDL 3 .
  • the material of the polymer layer PM 1 , PM 2 , PM 3 , PM 4 may be the same as or different from the material of the protection layer 18 a of the die 120 a, the material of the first encapsulant 22 a or the material of the second encapsulant 23 a.
  • each of the polymer layers PM 1 , PM 2 , PM 3 and PM 4 includes a photo-sensitive material such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof or the like.
  • the protection layer 18 a is referred as a polymer layer PM 0 .
  • each of the redistribution layers RDL 1 , RDL 2 , RDL 3 and RDL 4 includes conductive materials.
  • the conductive materials includes metal such as copper, nickel, titanium, a combination thereof or the like, and is formed by an electroplating process.
  • the redistribution layers RDL 1 , RDL 2 , RDL 3 and RDL 4 respectively includes a seed layer (not shown) and a metal layer formed thereon (not shown).
  • the seed layer may be a metal seed layer such as a copper seed layer.
  • the seed layer includes a first metal layer such as a titanium layer and a second metal layer such as a copper layer over the first metal layer.
  • the metal layer may be copper or other suitable metals.
  • the redistribution layers RDL 1 , RDL 2 , RDL 3 and RDL 4 respectively includes a plurality of vias V and a plurality of traces T connected to each other.
  • the vias V vertically penetrate through the polymer layers PM 1 , PM 2 , PM 3 and PM 4 to connect the traces T of the redistribution layers RDL 1 , RDL 2 , RDL 3 and RDL 4 , and the traces T are respectively located on the polymer layers PM 1 , PM 2 , PM 3 and PM 4 , and are respectively horizontally extending on the top surface of the polymer layers PM 1 , PM 2 , PM 3 and PM 4 .
  • the traces T of the redistribution layers RDL 1 are routing over the first encapsulant 22 a and the protection layer 18 a, and not over the second encapsulant 23 a.
  • the traces T or T 1 on the first encapsulant 22 a may achieve a fine quality, and the trace broken (open) or bridge (short) issues may occur due to the roughness of the encapsulant is avoided.
  • the redistribution layer RDL 4 is the topmost redistribution layer of the RDL structure 26 , and is referred as an under-ball metallurgy (UBM) layer for ball mounting.
  • UBM under-ball metallurgy
  • a plurality of connectors 27 are formed over and electrically connected to the redistribution layer RDL 4 of the RDL structure 26 .
  • the connectors 27 are referred as conductive terminals.
  • the connectors 27 may be ball grid array (BGA) connectors, solder balls, controlled collapse chip connection (C 4 ) bumps, or a combination thereof.
  • the material of the connector 27 includes copper, aluminum, lead-free alloys (e.g., gold, tin, silver, aluminum, or copper alloys) or lead alloys (e.g., lead-tin alloys).
  • the connector 27 may be formed by a suitable process such as evaporation, plating, ball dropping, screen printing and reflow process, a ball mounting process or a C 4 process.
  • metal posts or metal pillars may further be formed between the redistribution layer RDL 4 and the connectors 27 (not shown).
  • the connectors 27 are electrically connected to the two dies 120 a and 20 b through the RDL structure 26 .
  • the de-bonding layer 11 is decomposed under the heat of light, and the carrier 10 is then released.
  • the adhesive layer 12 is then removed by, for example, a cleaning process.
  • the bottom surfaces (or referred as back surfaces) of the dies 120 a and 20 b, that is, the bottom surfaces of the substrates 13 a and 13 b are exposed.
  • the package structure 50 a is thus completed.
  • the package structure 50 a is also referred as a fan-out package structure.
  • the package structure 50 a includes the two dies 120 a and 20 b, the first encapsulant 22 a, the second encapsulant 23 a, the RDL structure 26 and the connectors 27 .
  • the die 120 a and the die 20 b are connected through the RDL structure 26 .
  • the first encapsulant 22 a is located between the die 120 a and the die 20 b, and on the die 20 b.
  • the first encapsulant 22 a at least encapsulates the first sidewall 40 a of the die 120 a, the first sidewall 40 a of the die 20 b, the sidewalls of the connectors 27 of the die 20 b , and a portion of the top surface of the passivation layer 15 b of the die 20 b.
  • the cross-section shape of the portion of the first encapsulant 22 a under the trace T 1 is reversed L-shaped, for example.
  • the sidewalls of the portion of the first encapsulant 22 a between the two dies 120 a and 13 b are straight or inclined.
  • the sidewall of the first encapsulant 22 a on the edge of the die 20 b is inclined, curved, or arced.
  • the second encapsulant 23 a is aside and encapsulates the sidewall of the first encapsulant 22 a, aside and encapsulates the second sidewalls 40 b of the dies 120 a and 20 b.
  • the connectors 17 a of the die 120 a are laterally covered by and in contact with the protection layer 18 a, and are separated from the first encapsulant 22 a.
  • the protection layer 18 a of the die 120 a is in contact with the first encapsulant 22 a at the first sidewall 40 a of the die 120 a, and in contact with the second encapsulant 23 a at the second sidewall 40 b of the die 120 a.
  • the connectors 17 b of the die 20 b are laterally covered by and in contact with the first encapsulant 22 a , and separated from the second encapsulant 23 a.
  • the corner ⁇ 1 of the die 20 b is covered by and in contact with the first encapsulant 22 a .
  • the corner ⁇ 2 of the die 20 b is covered by and in contact with the first encapsulant 22 a or/and the second encapsulant 23 a.
  • the corner ⁇ 1 of the die 120 a is covered by and in contact with the protection layer 18 a and the first encapsulant 22 a.
  • the corner ⁇ 2 of the die 120 a is covered by and in contact with the protection layer 18 a and the second encapsulant 23 a.
  • the corners ⁇ 1 and ⁇ 2 are referred to the corners of the passivation layer 15 b of the die 20 b, the corners ⁇ 1 and ⁇ 2 are referred to the corners of the passivation layer 15 b of the die 20 b.
  • the interface 24 includes two end points 24 a and 24 b.
  • the end point 24 a is in contact with the polymer layer PM 1 of the RDL structure 26 , and at the same plane as the top surfaces of the connectors 17 a / 17 b.
  • the end point 24 b is on the edge of the die 20 b and is in contact with the protection layer 15 b.
  • the end point 24 b is on the top surface of the protection layer 15 b, and away from the second sidewall 40 b of the die 20 b.
  • the end point 24 b is at the intersection point of the top surface of the passivation layer 15 b and the second sidewall 40 b of the die 20 b.
  • an included angle a between the interface 24 and the top surface of the passivation layer 15 b is less than 90°. In other words, the interface 24 is inclined towards the connector 17 a of the die 20 b. A portion of the second encapsulant 23 a is located over the die 20 b.
  • the top surface of the passivation layer 15 b of the die 20 b is covered by the first encapsulant 22 a, and is not in contact with the second encapsulant 23 a.
  • the disclosure is not limited thereto.
  • a portion of the top surface of the passivation layer 15 b adjacent to the corner ⁇ 2 is not covered by the first encapsulant 22 a, but is covered by the second encapsulant 23 a.
  • the package structure 50 a may further be electrically coupled to other package components such as a printed circuit board (PCB), a flex PCB, or the like through the connectors 27 .
  • PCB printed circuit board
  • flex PCB flex PCB
  • a package structure 50 b is formed.
  • the package structure 50 b is similar to the package structure 50 a, but differs from the package structure 50 a in that the first encapsulant 22 a further extends to cover the second sidewall 40 b of the die 20 b, and the other structural characteristics of package structure 50 b are substantially the same as those of the package structure 50 a.
  • the first encapsulant 22 a encapsulates the first sidewall 40 a of the die 120 a, the first sidewall 40 a and the second sidewall 40 b of the die 20 b, the sidewalls of the connectors 17 b of the die 20 b, and the top surface of the passivation layer 15 a of the die 20 b.
  • the interface 24 ′ between the first encapsulant 22 a and the second encapsulant 23 a is over the edge of the die 20 b, and aside the second sidewall 40 b of the die 20 b.
  • the interface 24 ′ is not connected to the second sidewall 40 b of the die 20 b.
  • the interface 24 ′ is not in contact with the passivation layer 15 b of the die 20 b.
  • the interface 24 ′ includes two end points 24 a ′ and 24 b ′.
  • the interface 24 ′ differs from the interface 24 in that the end point 24 b ′ is aside the second sidewall 40 b of the die 20 b, and at a same plane as the bottom surfaces of the dies 120 a and 20 b.
  • the first sidewall 40 a, the second sidewall 40 b and the corners 01 and ⁇ 2 of the die 20 b are covered and in contact with the first encapsulant 22 a, and are not in contact with the second encapsulant 23 a.
  • the second sidewall 40 b and the corner ⁇ 2 of the die 20 b are separated from the second encapsulant 23 a by the first encapsulant 22 a therebetween.
  • the structural relationship between the die 120 a and the encapsulants 22 a and 23 a are substantially the same as those of the package structure 50 a ( FIG. 1F ), which is not described again.
  • FIG. 2A to FIG. 2F are schematic cross-sectional views illustrating a forming method of a package structure according to a second embodiment of the disclosure.
  • the second embodiment is similar to the first embodiment, but differs from the first embodiment in that, the sidewalls of the connectors 17 a of the die 20 a are not surrounded by a protection layer, but encapsulated by a first encapsulant 122 a.
  • a de-bonding layer 11 is formed on a carrier 10 , a first die 20 a and a second die 20 b are attached to the de-bonding layer 11 over the carrier 10 through an adhesive layer 12 .
  • a gap 21 is existed between the die 20 a and the die 20 b.
  • both the connectors 17 a of the die 20 a and the connectors 17 b of the die 20 b are not surrounded by a protection layer, that is to say, the sidewalls of the connectors 17 a and 17 b and the top surface of the passivation layer 15 a and 15 b are exposed.
  • the other features of the die 20 a and the die 20 b are substantially the same as those of the die 120 a and the die 20 b in the first embodiment.
  • a first encapsulant material layer 122 is formed on the dies 20 a and 20 b, and fills in the gap 21 between the dies 20 a and 20 b.
  • the first encapsulant material layer 122 at least encapsulates the first sidewalls 40 a of the dies 20 a and 20 b, portions of the top surfaces of the passivation layer 15 a and 15 b, the sidewalls and the top surfaces of the connectors 17 a and 17 b.
  • the material and the forming method of the first encapsulant material layer 122 are substantially the same as those of the first encapsulant material layer 22 in the first embodiment.
  • the surface of first encapsulant material layer 122 is unflat, and may have an inclined, a curved or an arced profile, for example.
  • the top surfaces of the passivation layer 15 a and 15 b are completely covered by the first encapsulant material layer 122 , but the disclosure is not limited thereto. In some other embodiments, portions of the top surfaces of the passivation layer 15 a and 15 b on the edge (the edge adjacent to the second sidewalls 40 b ) of the dies 20 a and 20 b may be not covered by the first encapsulant material layer 122 , but exposed (shown as the dotted line C).
  • the second sidewalls 40 b of the dies 20 a and 20 b are not covered by the first encapsulant material layer 22 , and are exposed.
  • the disclosure is not limited thereto.
  • the first encapsulant material layer 122 may further extend to encapsulate the second sidewalls 40 b of the dies 20 a and 20 b (shown as the dotted line D).
  • a second encapsulant material layer 123 is formed on the carrier 10 and on the first encapsulant material layer 122 .
  • the second encapsulant material layer 123 encapsulates the second sidewalls 40 b of the dies 20 a and 20 b and the top surface of the first encapsulant material layer 122 .
  • the material and the forming method of the second encapsulant material layer 123 are substantially the same as those of the second encapsulant material layer 23 in the first embodiment.
  • a planarization process is performed, and a portion of the second encapsulant material layer 123 and a portion of the first encapsulant material layer 122 are removed, such that the connectors 17 a of the die 20 a and the connectors 17 b of the die 20 b are exposed, and a first encapsulant 122 a and a second encapsulant 123 a are formed.
  • the top surfaces of the connectors 17 a and 17 b, the top surface of the first encapsulant 122 , and the top surface of the second encapsulant 123 are substantially coplanar with each other.
  • a RDL structure 26 is formed on the dies 20 a and 20 b, on the first encapsulant 122 a and the second encapsulant 123 a.
  • the RDL structure 26 includes polymer layers PM 1 , PM 2 , PM 3 , PM 4 and redistribution layers RDL 1 , RDL 2 , RDL 3 , RDL 4 .
  • a plurality of connectors 27 are formed on the redistribution layer RDL 4 of the RDL structure 26 . The connectors 27 are electrically connected to the dies 20 a and 20 b through the RDL structure 26 .
  • the de-bonding layer 11 is decomposed under the heat of light, and the carrier 10 is then released.
  • the adhesive layer 12 is removed by, for example, a cleaning process.
  • the bottom surfaces (or referred as back surfaces) of the dies 20 a and 20 b are exposed.
  • the package structure 150 a includes the two dies 20 a and 20 b, the first encapsulant 122 a, the second encapsulant 123 a, the RDL structure 26 and the connectors 27 .
  • the die 20 a and the die 20 b are electrically connected to each other through the RDL structure 26 .
  • the first encapsulant 122 a is located between the die 20 a and the die 20 b, and on the dies 20 a and 20 b.
  • the first encapsulant 122 a at least encapsulates and contacts with the first sidewalls 40 a of the dies 20 a and 20 b, the sidewalls of the connectors 17 a and 17 b, and portions of the top surfaces of the passivation layer 15 a and 15 b.
  • the top surface of the first encapsulant 122 a is in contact with the bottom surface of the polymer layer PM 1 .
  • the cross-section shape of the portion of the first encapsulant 122 a under the trace T 1 of the RDL 1 is T-shaped.
  • the sidewalls of the first encapsulant 122 a are inclined, curved, or arced.
  • the second encapsulant 123 a is located aside and encapsulates the second sidewalls 40 b of the dies 20 a and 20 b and the sidewalls of the first encapsulant 122 a.
  • An interface 124 is existed between the first encapsulant 122 a and the second encapsulant 123 a.
  • the interface 124 includes a first interface 124 a and a second interface 124 b .
  • the interface 124 a is on an edge (the edge adjacent to the corner ⁇ 2 ) of the die 120 a.
  • the first interface 124 a is connected to the second sidewall 40 b of the die 20 a.
  • the first interface 124 a is not connected to the second sidewall 40 b of the die 20 a (shown as the dotted line C′).
  • the interface 124 b is on an edge (the edge adjacent to the corner ⁇ 2 ) of the die 20 b.
  • the second interface 124 b is connected to the second sidewall 40 b of the die 20 b. In some other embodiments, the interface 124 b is not connected to the second sidewall 40 b of the die 20 b (shown as the dotted line). In some embodiments, the first interface 124 a and the second interface 124 b are symmetrical to each other, but the disclosure is not limited thereto. The structural characteristics of the first interface 124 a and the second interface 124 b are respectively similar to those of the interface 24 shown in FIG. 1F , and is not described again.
  • the connectors 17 a of the die 20 a and the connectors 17 b of the die 20 b are laterally covered by and in contact with the first encapsulant 122 a, and are separated from the second encapsulant 123 a.
  • the corner ⁇ 1 of the die 20 a and the corner ⁇ 1 of the die 20 b are covered by and in contact with the first encapsulant 122 a.
  • the corner ⁇ 2 of the die 20 a and the corner ⁇ 2 of the die 20 b are covered by and in contact with the first encapsulant 122 a or/and the second encapsulant 123 a.
  • the corner ⁇ 2 of the die 20 a and the corner ⁇ 2 of the die 20 b are covered by the second encapsulant 123 a.
  • the top surfaces of passivation layer 15 a and the passivation layer 15 b are covered by the first encapsulant 122 a, and are not in contact with the second encapsulant 123 a, but the disclosure is not limited thereto.
  • a portion of the top surface of the passivation layer 15 a adjacent to the corner ⁇ 2 of the die 20 a, and a portion of the top surface of the passivation layer 15 b adjacent to the corner ⁇ 2 of the die 20 b are not covered by the first encapsulant 122 a, but covered by the second encapsulant 123 a (shown as the dotted line C′).
  • the package structure 150 a may further be electrically coupled to other package components such as a printed circuit board (PCB), a flex PCB, or the like through the connectors 27 .
  • PCB printed circuit board
  • flex PCB flex PCB
  • a package structure 150 b is formed.
  • the package structure 150 b is similar to the package structure 150 a, but differs from the package structure 150 a in that the first encapsulant 122 a further extends to cover the second sidewalls 40 b of the dies 20 a and 20 b, and the other structural characteristics of the package structure 150 b are substantially the same as those of the package structure 150 a.
  • the first encapsulant 122 a laterally encapsulates and contacts with the first sidewalls 40 a and the second sidewalls 40 b of the dies 20 a and 20 b, and is on the dies 20 a and 20 b, encapsulating and contacting with the sidewalls of the connectors 17 a and 17 b, and the top surfaces of the passivation layers 15 a and 15 b of the die 20 a.
  • the second encapsulant 123 a is located aside the first encapsulant 122 a, encapsulating the sidewalls of the first encapsulant 122 a.
  • the second encapsulant 123 a is not in contact with the second sidewalls 40 b of the dies 20 a / 20 b, but separated from the dies 20 a / 20 b by the first encapsulant 122 a therebetween.
  • the interface 124 ′ between the first encapsulant 122 a and the encapsulant 123 a is not in contact with the edge of the dies 20 a and 20 b, or connected to the second sidewalls 40 b of the dies 20 a and 20 b. Instead, portions of the interface 124 ′ are located aside the second sidewalls 40 b of the dies 20 a and 20 b.
  • the interface 124 ′ includes a first interface 124 a ′ aside the second sidewall 40 b of the die 20 a, and a second interface 124 b ′ aside the second sidewall 40 b of the die 20 b.
  • first interface 124 a ′ and the second interface 124 b ′ are symmetrical to each other, but the disclosure is not limited thereto.
  • the structural characteristics of the first interface 124 a ′ and the second interface 124 b ′ are respectively similar to those of the interface 24 ′ shown in FIG. 4 , and is not described again.
  • FIG. 3A to FIG. 3F are schematic cross-sectional views illustrating a forming method of a package structure according to a third embodiment of the disclosure.
  • the third embodiment is similar to the foregoing embodiments, but differs from the foregoing embodiments in that, the sidewalls of the connectors 17 a are surrounded by and in contact with a protection layer 18 a of a die 120 a, and the sidewalls of the connectors 17 b are surrounded by and in contact with a protection layer 18 b of a die 120 b.
  • a de-bonding layer 11 is formed on a carrier 10 , a die 120 a and a die 120 b are attached to the de-bonding 11 through an adhesive layer 12 .
  • the structural characteristics of the die 120 a are substantially the same as those of the die 120 a in the first embodiment.
  • the die 120 b differs from the die 20 b in that, the die 120 further includes a protection layer 18 b.
  • the protection layer 18 b is formed on the passivation layer 15 b, and aside the connectors 17 b, surrounding and covering the sidewalls of the connectors 17 b.
  • the top surface of the protection layer 18 b and the top surfaces of the connectors 17 b are substantially coplanar with each other.
  • a gap 21 is existed between the die 120 a and the die 120 b.
  • a first encapsulant material layer 222 is formed to fill the gap 21 between the die 120 a and the die 120 b.
  • the first encapsulant material layer 222 at least encapsulates the first sidewalls 40 a of the dies 120 a and 120 b.
  • the first encapsulant material layer 222 may protrudes from the top surfaces of the dies 120 a and 120 b.
  • the first encapsulant material layer 222 may further cover a portion of the top surface of the die 120 a or/and a portion of the top surface of the die 120 b.
  • a second encapsulant material layer 223 is formed on the carrier 10 , the dies 120 a and 120 b, and the first encapsulant material layer 222 .
  • the materials and the forming methods of the first encapsulant material layer 222 and the second encapsulant material layer 223 are substantially the same as those of the first encapsulant material layer 22 and the second encapsulant material layer 23 described in the first embodiment, respectively.
  • a planarization process is performed, and a portion of the first encapsulant material layer 222 and a portion of the second encapsulant material layer 223 are removed, such that the top surfaces of the connectors 17 a and the connectors 17 b are exposed, a first encapsulant 222 a and a second encapsulant 223 a are formed.
  • a RDL structure 26 and a plurality of connectors 27 are formed on the dies 120 a and 120 b, the first encapsulant 222 a and the second encapsulant 223 a.
  • the die 120 a and the die 120 b are electrically connected to each other through the RDL structure 26 .
  • the connectors 27 are electrically connected to the dies 120 a and 120 b through the RDL structure 26 .
  • the de-bonding layer 11 is decomposed under the heat of light, and the carrier 10 is then released. In some embodiments, the adhesive layer 12 is removed. The bottom surfaces (or referred as back surfaces) of the dies 120 a and 120 b are exposed.
  • the package structure 250 includes the two dies 120 a and 120 b, the first encapsulant 222 a, the second encapsulant 223 a, the RDL structure 26 and the connectors 27 .
  • the first encapsulant 222 a is located between the die 120 a and the die 120 b, that is, aside the first sidewalls 40 a of the dies 120 a and 120 b, encapsulating and contacting with the first sidewalls 40 a of the dies 120 a and 120 b.
  • the cross-section shape of the first encapsulant 222 a includes I-shape, rectangle, square, or a combination thereof.
  • the second encapsulant 223 a is located aside, encapsulates and contacts with the second sidewalls 40 b of the dies 120 a and 120 b. In this embodiment, the first encapsulant 222 a and the second encapsulant 223 a are not in contact with each other.
  • the connectors 17 a and 17 b are not in contact with the first encapsulant 222 a or the second encapsulant 223 a, but are respectively surrounded by and in contact with the protection layers 18 a and 18 b. Interfaces are existed between the protection layer 18 a / 18 b and the first encapsulant 222 a or between the protection layer 18 a / 18 b and the second encapsulant 223 a, and the interfaces may be straight or inclined.
  • the package structure 250 may further be electrically coupled to other package components such as a printed circuit board (PCB), a flex PCB, or the like through the connectors 27 .
  • PCB printed circuit board
  • flex PCB flex PCB
  • FIG. 6 is a flow chart illustrating a method of forming a package structure according to some embodiments of the disclosure.
  • a first encapsulant is formed at least between a first die and a second die.
  • a second encapsulant is formed aside a sidewall of the first die and a sidewall of the second die.
  • a redistribution layer (RDL) structure is formed on the first die, the second die, the first encapsulant, and the second encapsulant.
  • RDL redistribution layer
  • a plurality of conductive terminals are electrically connected to the first die and the second die through the RDL structure.
  • package structure including two dies and method of manufacturing the same are illustrated.
  • the disclosure is not limited thereto, the disclosure may also applied to single die package structure including one die or multiple die package structure including more than two dies.
  • the encapsulant including a first encapsulant and a second encapsulant aside the dies are formed of two different materials by two step processes.
  • the first encapsulant is formed at least aside the first sidewalls of the two dies
  • the second encapsulant is formed aside the second sidewalls of the two dies.
  • the first encapsulant is formed of a material comprising fine fillers or no filler. Therefore, the problem of roughness surface or even pits may be caused by large filler are avoided.
  • the first encapsulant is formed at least between the two dies, especially under the traces connecting the two dies.
  • the traces of the bottommost redistribution layer are routing over the first encapsulant or/and the protection layer of the die in which no filler or fine filler is included. Therefore, the traces may achieve a fine quality, and the trace broken (open) and bridge (short) issues may occur due to the roughness of the encapsulant is avoided.
  • a package structure includes a first die and a second die, a first encapsulant, a second encapsulant and a RDL structure.
  • the first die includes a first connector and a first protection layer covering sidewalls of the first connector, and the second die includes a second connector.
  • the first encapsulant is at least disposed laterally between the first die and the second die to encapsulate first sidewalls of the first die and the second die that faces each other.
  • the second encapsulant encapsulates second sidewalls of the first die and the second die.
  • the RDL structure is disposed on and electrically connected to the first die and the second die. The top surfaces of the first protection layer, the first encapsulant, and the second encapsulant are in contact with a bottom surface of the RDL structure.
  • a package structure includes a first die and a second die, a first encapsulant, a second encapsulant and a conductive terminal.
  • the first die includes a first connector
  • the second includes a second connector.
  • the first encapsulant is laterally between the first die and the second die and on the second die.
  • the first connector is separated from the first encapsulant by a protection layer of the first die, and the second connector of the second die is in contact with the first encapsulant.
  • the second encapsulant laterally encapsulates the first die, the second die and the first encapsulant.
  • the conductive terminal is electrically connected to the first die and the second die through a RDL structure.
  • a method of forming a package structure includes: providing a first die and a second die, wherein the first die comprises a first connector and a first protection layer covering sidewalls of the first connector, and the second die comprises a second connector; forming a first encapsulant at least between the first die and the second die; forming a second encapsulant to laterally encapsulate the first die and the second die, wherein the first encapsulant and the second encapsulant are formed by different processes; and forming a redistribution layer (RDL) structure on and electrically connected to the first die and the second die, wherein top surfaces of the first protection layer, the first encapsulant and the second encapsulant are in contact with a bottom surface of the RDL structure.
  • RDL redistribution layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A package structure and a method of forming the same are provided. The package structure includes a first die and a second die, a first encapsulant, a second encapsulant and a RDL structure. The first die includes a first connector and a first protection layer covering sidewalls of the first connector, and the second die includes a second connector. The first encapsulant is at least disposed laterally between the first die and the second die to encapsulate first sidewalls of the first die and the second die that faces each other. The second encapsulant encapsulates second sidewalls of the first die and the second die. The RDL structure is disposed on and electrically connected to the first die and the second die. The top surfaces of the first protection layer, the first encapsulant, and the second encapsulant are in contact with a bottom surface of the RDL structure.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application is a continuation application of and claims the priority benefit of a prior application Ser. No. 15/835,466, filed on Dec. 08, 2017, now allowed. The prior application Ser. No. 15/835,466 claims the priority benefit of U.S. provisional application Ser. No. 62/584,914, filed on Nov. 13, 2017. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.
  • BACKGROUND
  • The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from continuous reductions in minimum feature size, which allows more of the smaller components to be integrated into a given area. These smaller electronic components also require smaller packages that utilize less area than previous packages. Some smaller types of packages for semiconductor components include quad flat packages (QFPs), pin grid array (PGA) packages, ball grid array (BGA) packages, and so on.
  • Currently, integrated fan-out packages are becoming increasingly popular for their compactness.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1A to FIG. 1F are schematic cross-sectional views illustrating a method of forming a package structure according to a first embodiment of the disclosure.
  • FIG. 2A to FIG. 2F are schematic cross-sectional views illustrating a method of forming a package structure according to a second embodiment of the disclosure.
  • FIG. 3A to FIG. 3F are schematic cross-sectional views illustrating a method of forming a package structure according to a third embodiment of the disclosure.
  • FIG. 4 is a schematic cross-sectional view illustrating a package structure according to some embodiments of the disclosure.
  • FIG. 5 is a schematic cross-sectional view illustrating a package structure according to some embodiments of the disclosure.
  • FIG. 6 is a flow chart illustrating a method of forming a package structure according to some embodiments of the disclosure.
  • DETAILED DESCRIPTION
  • The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a second feature over or on a first feature in the description that follows may include embodiments in which the second and first features are formed in direct contact, and may also include embodiments in which additional features may be formed between the second and first features, such that the second and first features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
  • Further, spatially relative terms, such as “beneath”, “below”, “lower”, “on”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the FIG.s. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the FIG.s. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
  • Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs.
  • FIG. 1A to FIG. 1F are schematic cross-sectional views illustrating a forming method of a package structure according to a first embodiment of the disclosure.
  • Referring to FIG. 1A, a carrier 10 is provided. The carrier 10 may be a glass carrier, a ceramic carrier, or the like. In some embodiments, the carrier 10 has a de-bonding layer 11 formed thereon. The de-bonding layer 11 is formed by, for example, a spin coating method. In some embodiments, the de-bonding layer 11 may be formed of an adhesive such as an Ultra-Violet (UV) glue, a Light-to-Heat Conversion (LTHC) glue, or the like, or other types of adhesives. The de-bonding layer 11 is decomposable under the heat of light to thereby release the carrier 10 from the overlying structures that will be formed in subsequent steps.
  • In some embodiments, a die 120 a and a die 20 b are attached side by side to the de-bonding layer 11 over the carrier 10 through an adhesive layer 12 such as a die attach film (DAF), silver paste, or the like. The die 120 a and the die 20 b may respectively be an application-specific integrated circuit (ASIC) chip, an analog chip, a sensor chip, a wireless and radio frequency chip, a voltage regulator chip, a memory chip or the like. The die 120 a and the die 20 b may be the same types of dies or the different types of dies. In some embodiments, the two dies 120 a and 20 b are two small die partitions with different function of a larger single die. The size (refers to the height and/or the width) of the two dies 120 a and 20 b may be the same or different. In some embodiments, a gap 21 is existed between the two dies 120 a and 20 b. The number of the dies attached to the carrier 10 is not limited to that is shown in FIG. 1A. In some other embodiments, one die or more than two dies are attached to the carrier 10.
  • In some embodiments, the two dies 120 a and 20 b have similar structures. For the sake of brevity, the die 120 a is taken for example. The die 120 a includes a substrate 13 a, a pad 14 a, a passivation layer 15 a, conductive posts 19 a and a protection layer 18 a.
  • In some embodiments, the substrate 13 is made of silicon or other semiconductor materials. Alternatively or additionally, the substrate 13 includes other elementary semiconductor materials such as germanium, gallium arsenic, or other suitable semiconductor materials. In some embodiments, the substrate 13 may further include other features such as various doped regions, a buried layer, and/or an epitaxy layer. Moreover, in some embodiments, the substrate 13 is made of an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. Furthermore, the substrate 13 may be a semiconductor on insulator such as silicon on insulator (SOI) or silicon on sapphire.
  • The pads 14 a may be a part of an interconnection structure (not shown) and electrically connected to the devices (not shown) formed on the substrate 13 a. In some embodiments, the devices may be active devices, passive devices, or a combination thereof. In some embodiments, the devices are integrated circuit devices. The passivation layer 15 a is formed over the substrate 13 a and covers a portion of the pads 14 a. A portion of the pads 14 a is exposed by the passivation layer 15 a and serves as an external connection of the die 120 a. In some embodiments, the passivation layer 15 a includes a first passivation layer 8 a and a second passivation layer 9 a on the first passivation layer 8 a. The material of the first passivation layer 8 a and the material of the second passivation layer 9 a may be the same or different. The second passivation layer 9 a is also referred as a post-passivation layer, and is optionally formed.
  • The conductive posts 19 a are formed on and electrically connected to the pads 14 a exposed by the passivation layer 15 a. In some embodiments, the conductive post 19 includes a first portion 16 a and a second portion 17 a. The first portion 16 a is embedded in and laterally covered by the passivation layer 15 a. The second portion 17 a is on the first portion 16 a and the passivation layer 15 a. In some embodiments, the second portion 17 a covers a portion of the top surface of the passivation layer 15 a. In some other embodiments, the second portion 17 a is on the first portion 16 a and does not cover the top surface of the passivation layer 15 a. The second portion 17 a is also referred as a connector. The conductive posts 19 a include solder bumps, gold bumps, copper bumps, copper posts, copper pillars, or the like. The protection layer 18 a is formed over the passivation layer 15 a and aside the connectors 17 a to cover the sidewalls of the connectors 17 a. The passivation layer 15 a and the protection layer 18 a respectively include an insulating material such as silicon oxide, silicon nitride, polymer, or a combination thereof. The polymer includes polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof or the like, for example. In some embodiments, the passivation layer 15 a and the protection layer 18 a are free of fillers. The materials of the passivation layer 15 a and the protection layer 18 a may be the same or different. In some embodiments, the top surface of the protection layer 18 a is substantially level with the top surface of the connectors 17 a.
  • Similar to the die 120 a, the die 20 b includes a substrate 13 b, a pad 14 b, a passivation layer 15 b, and a conductive post 19 b. In some embodiments, the passivation layer 15 b includes a first passivation layer 8 b and a second passivation layer 9 b. The second passivation layer 9 b is also referred as a post-passivation layer and is optionally formed. The conductive post 19 b includes a first portion 16 b and a second portion 17 b. The second portion 17 b is also refereed as a connector. The material and the structural characteristics of the substrate 13 b, the pad 14 b, the passivation layer 15 b, and the conductive post 19 b of the die 20 b are substantially the same as or different from those of the substrate 13 a, the pad 14 a, the passivation layer 15 a, the conductive post 19 a of the die 120 a. The die 20 b differs from the die 120 a in that, no protection layer is formed aside the connectors 17 b. That is to say, the sidewalls of the connectors 17 b are not covered by a protection layer, but exposed. In some embodiments, the top surfaces of the connectors 17 a and the top surfaces of the connectors 17 b are substantially coplanar with each other, but the disclosure is not limited thereto. In some other embodiments, the top surfaces of the connectors 17 a and the top surfaces of the connectors 17 b may be not coplanar with each other.
  • In some embodiments, the dies 120 a and 20 b respectively has a first sidewall 40 a and a second sidewall 40 b opposite to each other. The first sidewall 40 a of the die 120 a or 20 b is the sidewall adjacent to another die 20 b or 120 a, and the second sidewall 40 b of the die 120 a or 20 b is the sidewall far away from another die 20 b or 120 a. The first sidewalls 40 a and the second sidewalls 40 b may be straight or inclined.
  • Referring to FIG. 1B, a first encapsulant material layer 22 is formed over the carrier 10 and on the die 20 b. The first encapsulant material layer 22 fills in the gap 21 between the die 120 a and the die 20 b, at least encapsulates the first sidewalls 40 a of the dies 120 a and 20 b, the top surfaces and sidewalls of the connectors 17 b of the die 20 b, and a portion of top surface of the passivation layer 15 b of the die 20 b. In some embodiments, the top surface of the passivation layer 15 b is completely covered by the first encapsulant material layer 22, but the disclosure is not limited thereto. In some other embodiments, a portion of the top surface of the passivation layer 15 b at an edge (the edge adjacent to the second sidewall 40 b) of the die 20 b may be not covered by the first encapsulant material layer 22 (shown as the dotted line A). In some embodiments, the top surface of the die 120 a, and the second sidewall 40 b of the die 20 b are not covered by the first encapsulant material layer 22, but the disclosure is not limited thereto. In some other embodiments, the first encapsulant material layer 22 may further extend to cover the top surface of the die 120 a or/and the sidewall 40 b of the die 20 b (shown as dotted line B).
  • In some embodiments, the first encapsulant material layer 22 is formed of an underfill material, a molding underfill material, polymer, or a combination thereof. The polymer includes polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof or the like. Referring to the enlarged view of the first encapsulant material layer 22, in some embodiments in which the first encapsulant material layer 22 is formed of underfill material or molding underfill material, the first encapsulant material layer 22 includes polymer and a plurality of fillers 22′. The filler 22′ may be a powdered inorganic material, the filler 22′ may be a single element, a compound such as nitride, or a combination thereof, e.g., silica, alumina, carbon, or aluminum nitride, or mixtures thereof. In some embodiments, the filler 22′ is fine filler whose particle size is very small. The average particle size of the filler 22′ ranges from 0.1 μm to 10 μm, or even smaller than 0.1 μm, for example. In some other embodiments, the first encapsulant material layer 22 may be free of filler. The first encapsulant material layer 22 may be formed by a dispensing process, for example. In some embodiments, after the first encapsulant material layer 22 is dispensed in the gap 21 and on the die 20 b, a curing process is further performed.
  • Still referring to FIG. 1B, in some embodiments, the surface of the first encapsulant material layer 22 is unflat. The first encapsulant material layer 22 may be tapered towards the die 20 b. The surface of the first encapsulant material layer 22 may have a curved profile, an inclined profile, an arced profile, or a combination thereof. In some embodiments, the surface of the first encapsulant material layer 22 is higher than the top surface of the protection layer 18 a of the die 120 a.
  • Referring to FIG. 1C, a second encapsulant material layer 23 is formed over the carrier 10 and the dies 120 a and 20 b, so as to encapsulate the second sidewalls 40 b of the dies 120 a and 20 b, the top surface of the die 120 a and the top surface of the first encapsulant material layer 22. The material of the second encapsulant material layer 23 may be the same as or different from the material of the first encapsulant material layer 22. In some embodiments, the first encapsulant material layer 22 and the second encapsulant material layer 23 comprise the same material with different physical characteristics (e.g. particle size). The second encapsulant material layer 23 includes a molding compound, for example. In some embodiments, the second encapsulant material layer 23 is formed by a process different from that of the first encapsulant material layer 22, such as a molding process.
  • Referring to the enlarged view of the first encapsulant material layer 22 and the second encapsulant material layer 23, in some embodiments, the second encapsulant material layer 23 is a composite material including a polymer and a plurality of fillers 23′. The filler 23′ may be a single element, a compound such as nitride, oxide, or a combination thereof. The fillers 23′ may comprise silicon oxide, aluminum oxide, boron nitride, alumina, silica, and the like, for example. The cross-section shape of the filler 22′ or 23′ may be circle, square, rectangle, or any other shape, and the disclosure is not limited thereto. In some embodiments, the particle size of the filler 23′ is larger than the particle size of the filler 22′, herein, the particle size of the filler 22′ or 23′ refers to the diameter, length, width or height of the filler 22′ or 23′. The average particle size of the filler 23′ ranges from 3 μm to 30 μm, or even larger than 30 μm, for example. In some embodiments, the particle size is referred to the average particle size D50, and the average particle size D50 of the filler 23′ is larger than the average particle size D50 of the filler 22′.
  • Referring to FIG. 1C and FIG. 1D, a planarization process is performed, and a portion of the second encapsulant material layer 23 and a portion of the first encapsulant material layer 22 are removed, such that the connectors 17 a of the die 120 a and the connectors 17 b of the die 20 b are exposed, and a first encapsulant 22 a and a second encapsulant 23 a are formed. In some embodiments in which the top surfaces of the connectors 17 a and the top surfaces of the connectors 17 b are not coplanar with each other, ones of the connectors 17 a and the connectors 17 b at a higher level are removed during the planarization process, that is, portions of the connectors 17 a and a portion of the protection layer 18 a, or portions of the connectors 17 b are also removed during the planarization process. In some embodiments, after the planarization process, the top surfaces of the connectors 17 a and the protection layer 18 a of the die 120 a, the top surfaces of the connectors 17 b of the die 20 b, the top surface of the first encapsulant 22 a, and the top surface of the second encapsulant 23 a are substantially coplanar with each other. The planarization process includes a grinding process or a polishing process, such as a chemical mechanical polishing (CMP) process. After the planarization process, as the first encapsulant 22 a is formed of materials free of filler or including fine fillers, the first encapsulant 22 a may have a substantially flat surface, and the problem of rounghness surface or pits may be caused by large fillers is avoided. In some embodiments in which the second encapsulant 23 a includes fillers having larger particle size than the first encapsulant 22 a, the top surface of the first encapsulant 22 a is more flat than the top surface of the second encapsulant 23 a.
  • Referring to FIG. 1D, in some embodiments, the first encapsulant 22 a is disposed in the gap 21 between the dies 120 a and 20 b, and on the passivation layer 15 b of the die 20 b, encapsulating the first sidewalls 40 a of the dies 120 a and 20 b, and sidewalls of the connectors 17 b. That is to say, the connectors 17 b of the die 20 b are laterally covered by and in contact with the first encapsulant 22 a. The second encapsulant 23 a is aside and laterally encapsulants the sidewall of the first encapsulant 22 a, and the second sidewalls of the dies 120 a and 20 b.
  • Still referring to FIG. 1D, an interface 24 is existed between the first encapsulant 22 a and the second encapsulant 23 a. The interface 24 is on an edge of the die 20 b. In some embodiments, the interface 24 is connected to the second sidewall 40 b of the die 20 b. The interface 24 and the second sidewall 40 b may be not coplanar. In some other embodiments, the interface 24 is not connected to the second sidewall 40 b of the die 20 b (shown as the dotted line A′). The profile of the interface 24 is inclined, curved, or arced, for example.
  • Interfaces also exist between the protection layer 18 a and the first encapsulant 22 a, and between the protection layer 18 a and the second encapsulant 23 a. In some embodiments, the interface between the protection layer 18 a and the first encapsulant 22 a and the interface between the protection layer 18 a and the second encapsulant 23 a may respectively be straight or inclined.
  • Referring to FIG. 1E, a redistribution layer (RDL) structure 26 is formed over and electrically connected to the dies 120 a and 20 b. In some embodiments, the die 120 a and the die 20 b are electrically connected to each other through the RDL structure 26. In some embodiments, the RDL structure 26 is referred as a “front-side redistribution layer structure”, wherein the “front-side” refers to a side close to the connectors 17 a and 17 b of the dies 120 a and 20 b. In some embodiments, the RDL structure 26 includes a plurality of polymer layers PM1, PM2, PM3 and PM4 and a plurality of redistribution layers RDL1, RDL2, RDL3 and RDL4 stacked alternately. The number of the polymer layers or the redistribution layers is not limited by the disclosure.
  • The redistribution layer RDL1 penetrates through the polymer layer PM1 and is electrically connected to the connectors 17 a and 17 b of the dies 120 a and 20 b. The redistribution layer RDL2 penetrates through the polymer layer PM2 and is electrically connected to the redistribution layer RDL1. The redistribution layer RDL3 penetrates through the polymer layer PM3 and is electrically connected to the redistribution layer RDL2. The redistribution layer RDL4 penetrates through the polymer layer PM4 and is electrically connected to the redistribution layer RDL3.
  • The material of the polymer layer PM1, PM2, PM3, PM4 may be the same as or different from the material of the protection layer 18 a of the die 120 a, the material of the first encapsulant 22 a or the material of the second encapsulant 23 a. In some embodiments, each of the polymer layers PM1, PM2, PM3 and PM4 includes a photo-sensitive material such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof or the like. In some embodiments, the protection layer 18 a is referred as a polymer layer PM0.
  • In some embodiments, each of the redistribution layers RDL1, RDL2, RDL3 and RDL4 includes conductive materials. The conductive materials includes metal such as copper, nickel, titanium, a combination thereof or the like, and is formed by an electroplating process. In some embodiments, the redistribution layers RDL1, RDL2, RDL3 and RDL4 respectively includes a seed layer (not shown) and a metal layer formed thereon (not shown). The seed layer may be a metal seed layer such as a copper seed layer. In some embodiments, the seed layer includes a first metal layer such as a titanium layer and a second metal layer such as a copper layer over the first metal layer. The metal layer may be copper or other suitable metals.
  • In some embodiments, the redistribution layers RDL1, RDL2, RDL3 and RDL4 respectively includes a plurality of vias V and a plurality of traces T connected to each other. The vias V vertically penetrate through the polymer layers PM1, PM2, PM3 and PM4 to connect the traces T of the redistribution layers RDL1, RDL2, RDL3 and RDL 4, and the traces T are respectively located on the polymer layers PM1, PM2, PM3 and PM 4, and are respectively horizontally extending on the top surface of the polymer layers PM1, PM2, PM3 and PM4.
  • In some embodiments, the traces T of the redistribution layers RDL1, especially the traces T1 connecting the die 120 a and the die 20 b, are routing over the first encapsulant 22 a and the protection layer 18 a, and not over the second encapsulant 23 a. As the top surface of the first encapsulant 22 a is relatively more flat than the top surface of the second encapsulant 23 a, therefore, the traces T or T1 on the first encapsulant 22 a may achieve a fine quality, and the trace broken (open) or bridge (short) issues may occur due to the roughness of the encapsulant is avoided.
  • In some embodiments, the redistribution layer RDL4 is the topmost redistribution layer of the RDL structure 26, and is referred as an under-ball metallurgy (UBM) layer for ball mounting.
  • Still referring to FIG. 1E, thereafter, a plurality of connectors 27 are formed over and electrically connected to the redistribution layer RDL4 of the RDL structure 26. In some embodiments, the connectors 27 are referred as conductive terminals. In some embodiments, the connectors 27 may be ball grid array (BGA) connectors, solder balls, controlled collapse chip connection (C4) bumps, or a combination thereof. In some embodiments, the material of the connector 27 includes copper, aluminum, lead-free alloys (e.g., gold, tin, silver, aluminum, or copper alloys) or lead alloys (e.g., lead-tin alloys). The connector 27 may be formed by a suitable process such as evaporation, plating, ball dropping, screen printing and reflow process, a ball mounting process or a C4 process. In some embodiments, metal posts or metal pillars may further be formed between the redistribution layer RDL4 and the connectors 27 (not shown). The connectors 27 are electrically connected to the two dies 120 a and 20 b through the RDL structure 26.
  • Referring to FIG. 1E and FIG. 1F, the de-bonding layer 11 is decomposed under the heat of light, and the carrier 10 is then released. In some embodiments, the adhesive layer 12 is then removed by, for example, a cleaning process. The bottom surfaces (or referred as back surfaces) of the dies 120 a and 20 b, that is, the bottom surfaces of the substrates 13 a and 13 b are exposed.
  • Referring to FIG. 1F, a package structure 50 a is thus completed. The package structure 50 a is also referred as a fan-out package structure. The package structure 50 a includes the two dies 120 a and 20 b, the first encapsulant 22 a, the second encapsulant 23 a, the RDL structure 26 and the connectors 27. The die 120 a and the die 20 b are connected through the RDL structure 26.
  • In some embodiments, the first encapsulant 22 a is located between the die 120 a and the die 20 b, and on the die 20 b. The first encapsulant 22 a at least encapsulates the first sidewall 40 a of the die 120 a, the first sidewall 40 a of the die 20 b, the sidewalls of the connectors 27 of the die 20 b, and a portion of the top surface of the passivation layer 15 b of the die 20 b. In some embodiments, the cross-section shape of the portion of the first encapsulant 22 a under the trace T1 is reversed L-shaped, for example. In some embodiments, the sidewalls of the portion of the first encapsulant 22 a between the two dies 120 a and 13 b are straight or inclined. The sidewall of the first encapsulant 22 a on the edge of the die 20 b is inclined, curved, or arced.
  • In some embodiments, the second encapsulant 23 a is aside and encapsulates the sidewall of the first encapsulant 22 a, aside and encapsulates the second sidewalls 40 b of the dies 120 a and 20 b.
  • The connectors 17 a of the die 120 a are laterally covered by and in contact with the protection layer 18 a, and are separated from the first encapsulant 22 a. The protection layer 18 a of the die 120 a is in contact with the first encapsulant 22 a at the first sidewall 40 a of the die 120 a, and in contact with the second encapsulant 23 a at the second sidewall 40 b of the die 120 a. The connectors 17 b of the die 20 b are laterally covered by and in contact with the first encapsulant 22 a, and separated from the second encapsulant 23 a.
  • The corner θ1 of the die 20 b is covered by and in contact with the first encapsulant 22 a. The corner θ2 of the die 20 b is covered by and in contact with the first encapsulant 22 a or/and the second encapsulant 23 a. The corner β1 of the die 120 a is covered by and in contact with the protection layer 18 a and the first encapsulant 22 a. The corner β2 of the die 120 a is covered by and in contact with the protection layer 18 a and the second encapsulant 23 a. Herein, the corners θ1 and θ2 are referred to the corners of the passivation layer 15 b of the die 20 b, the corners β1 and β2 are referred to the corners of the passivation layer 15 b of the die 20 b.
  • In some embodiments, the interface 24 includes two end points 24 a and 24 b. The end point 24 a is in contact with the polymer layer PM1 of the RDL structure 26, and at the same plane as the top surfaces of the connectors 17 a/17 b. The end point 24 b is on the edge of the die 20 b and is in contact with the protection layer 15 b. In some embodiments, the end point 24 b is on the top surface of the protection layer 15 b, and away from the second sidewall 40 b of the die 20 b. In some embodiments, the end point 24 b is at the intersection point of the top surface of the passivation layer 15 b and the second sidewall 40 b of the die 20 b. In some embodiments, an included angle a between the interface 24 and the top surface of the passivation layer 15 b is less than 90°. In other words, the interface 24 is inclined towards the connector 17 a of the die 20 b. A portion of the second encapsulant 23 a is located over the die 20 b.
  • In some embodiments in which the interface 24 is connected to the second sidewall 40 b of the die 20 b, the top surface of the passivation layer 15 b of the die 20 b is covered by the first encapsulant 22 a, and is not in contact with the second encapsulant 23 a. However, the disclosure is not limited thereto. In some other embodiments in which the interface 24 is not connected to the second sidewall 40 b of the die 20 b (shown as the dotted line A′), a portion of the top surface of the passivation layer 15 b adjacent to the corner θ2 is not covered by the first encapsulant 22 a, but is covered by the second encapsulant 23 a.
  • In some embodiments, the package structure 50 a may further be electrically coupled to other package components such as a printed circuit board (PCB), a flex PCB, or the like through the connectors 27.
  • Referring to FIG. 4, in some embodiments in which the first encapsulant material layer 22 further extends to cover the second sidewall 40 b of the die 20 b, a package structure 50 b is formed. The package structure 50 b is similar to the package structure 50 a, but differs from the package structure 50 a in that the first encapsulant 22 a further extends to cover the second sidewall 40 b of the die 20 b, and the other structural characteristics of package structure 50 b are substantially the same as those of the package structure 50 a.
  • Still referring to FIG. 4, in the package structure 50 b, the first encapsulant 22 a encapsulates the first sidewall 40 a of the die 120 a, the first sidewall 40 a and the second sidewall 40 b of the die 20 b, the sidewalls of the connectors 17 b of the die 20 b, and the top surface of the passivation layer 15 a of the die 20 b. The interface 24′ between the first encapsulant 22 a and the second encapsulant 23 a is over the edge of the die 20 b, and aside the second sidewall 40 b of the die 20 b. The interface 24′ is not connected to the second sidewall 40 b of the die 20 b. In some embodiments, the interface 24′ is not in contact with the passivation layer 15 b of the die 20 b. The interface 24′ includes two end points 24 a′ and 24 b′. The interface 24′ differs from the interface 24 in that the end point 24 b′ is aside the second sidewall 40 b of the die 20 b, and at a same plane as the bottom surfaces of the dies 120 a and 20 b.
  • In some embodiments, the first sidewall 40 a, the second sidewall 40 b and the corners 01 and θ2 of the die 20 b are covered and in contact with the first encapsulant 22 a, and are not in contact with the second encapsulant 23 a. The second sidewall 40 b and the corner θ2 of the die 20 b are separated from the second encapsulant 23 a by the first encapsulant 22 a therebetween. The structural relationship between the die 120 a and the encapsulants 22 a and 23 a are substantially the same as those of the package structure 50 a (FIG. 1F), which is not described again.
  • FIG. 2A to FIG. 2F are schematic cross-sectional views illustrating a forming method of a package structure according to a second embodiment of the disclosure. The second embodiment is similar to the first embodiment, but differs from the first embodiment in that, the sidewalls of the connectors 17 a of the die 20 a are not surrounded by a protection layer, but encapsulated by a first encapsulant 122 a.
  • Referring to FIG. 2A, processes similar to those of the first embodiment are performed, a de-bonding layer 11 is formed on a carrier 10, a first die 20 a and a second die 20 b are attached to the de-bonding layer 11 over the carrier 10 through an adhesive layer 12. A gap 21 is existed between the die 20 a and the die 20 b. In this embodiment, both the connectors 17 a of the die 20 a and the connectors 17 b of the die 20 b are not surrounded by a protection layer, that is to say, the sidewalls of the connectors 17 a and 17 b and the top surface of the passivation layer 15 a and 15 b are exposed. The other features of the die 20 a and the die 20 b are substantially the same as those of the die 120 a and the die 20 b in the first embodiment.
  • Referring to FIG. 2B, a first encapsulant material layer 122 is formed on the dies 20 a and 20 b, and fills in the gap 21 between the dies 20 a and 20 b. In some embodiments, the first encapsulant material layer 122 at least encapsulates the first sidewalls 40 a of the dies 20 a and 20b, portions of the top surfaces of the passivation layer 15 a and 15 b, the sidewalls and the top surfaces of the connectors 17 a and 17 b. The material and the forming method of the first encapsulant material layer 122 are substantially the same as those of the first encapsulant material layer 22 in the first embodiment. In some embodiment, the surface of first encapsulant material layer 122 is unflat, and may have an inclined, a curved or an arced profile, for example.
  • In some embodiments, the top surfaces of the passivation layer 15 a and 15 b are completely covered by the first encapsulant material layer 122, but the disclosure is not limited thereto. In some other embodiments, portions of the top surfaces of the passivation layer 15 a and 15 b on the edge (the edge adjacent to the second sidewalls 40 b) of the dies 20 a and 20 b may be not covered by the first encapsulant material layer 122, but exposed (shown as the dotted line C).
  • In some embodiments, the second sidewalls 40 b of the dies 20 a and 20 b are not covered by the first encapsulant material layer 22, and are exposed. However, the disclosure is not limited thereto. In some other embodiments, the first encapsulant material layer 122 may further extend to encapsulate the second sidewalls 40 b of the dies 20 a and 20 b (shown as the dotted line D).
  • Referring to FIG. 2C, a second encapsulant material layer 123 is formed on the carrier 10 and on the first encapsulant material layer 122. In some embodiments, the second encapsulant material layer 123 encapsulates the second sidewalls 40 b of the dies 20 a and 20 b and the top surface of the first encapsulant material layer 122. The material and the forming method of the second encapsulant material layer 123 are substantially the same as those of the second encapsulant material layer 23 in the first embodiment.
  • Referring to FIG. 2C and FIG. 2D, a planarization process is performed, and a portion of the second encapsulant material layer 123 and a portion of the first encapsulant material layer 122 are removed, such that the connectors 17 a of the die 20 a and the connectors 17 b of the die 20 b are exposed, and a first encapsulant 122 a and a second encapsulant 123 a are formed. In some embodiments, the top surfaces of the connectors 17 a and 17 b, the top surface of the first encapsulant 122, and the top surface of the second encapsulant 123 are substantially coplanar with each other.
  • Referring to FIG. 2E and FIG. 2F, processes similar to those described in FIG. lE and FIG. 1F are performed, a RDL structure 26 is formed on the dies 20 a and 20 b, on the first encapsulant 122 a and the second encapsulant 123 a. The RDL structure 26 includes polymer layers PM1, PM2, PM3, PM4 and redistribution layers RDL1, RDL2, RDL3, RDL4. A plurality of connectors 27 are formed on the redistribution layer RDL4 of the RDL structure 26. The connectors 27 are electrically connected to the dies 20 a and 20 b through the RDL structure 26.
  • Thereafter, the de-bonding layer 11 is decomposed under the heat of light, and the carrier 10 is then released. In some embodiments, the adhesive layer 12 is removed by, for example, a cleaning process. The bottom surfaces (or referred as back surfaces) of the dies 20 a and 20 b are exposed.
  • Referring to FIG. 2F, a package structure 150 a is thus completed. The package structure 150 a includes the two dies 20 a and 20 b, the first encapsulant 122 a, the second encapsulant 123 a, the RDL structure 26 and the connectors 27. In some embodiments, the die 20 a and the die 20 b are electrically connected to each other through the RDL structure 26.
  • The first encapsulant 122 a is located between the die 20 a and the die 20 b, and on the dies 20 a and 20 b. The first encapsulant 122 a at least encapsulates and contacts with the first sidewalls 40 a of the dies 20 a and 20 b, the sidewalls of the connectors 17 a and 17 b, and portions of the top surfaces of the passivation layer 15 a and 15 b. The top surface of the first encapsulant 122 a is in contact with the bottom surface of the polymer layer PM1. In some embodiments, the cross-section shape of the portion of the first encapsulant 122 a under the trace T1 of the RDL1 is T-shaped. In some embodiments, the sidewalls of the first encapsulant 122 a are inclined, curved, or arced.
  • The second encapsulant 123 a is located aside and encapsulates the second sidewalls 40 b of the dies 20 a and 20 b and the sidewalls of the first encapsulant 122 a.
  • An interface 124 is existed between the first encapsulant 122 a and the second encapsulant 123 a. The interface 124 includes a first interface 124 a and a second interface 124 b. The interface 124 a is on an edge (the edge adjacent to the corner β2) of the die 120 a. In some embodiments, the first interface 124 a is connected to the second sidewall 40 b of the die 20 a. In some other embodiments, the first interface 124 a is not connected to the second sidewall 40 b of the die 20 a (shown as the dotted line C′). The interface 124 b is on an edge (the edge adjacent to the corner θ2) of the die 20 b. In some embodiments, the second interface 124 b is connected to the second sidewall 40 b of the die 20 b. In some other embodiments, the interface 124 b is not connected to the second sidewall 40 b of the die 20 b (shown as the dotted line). In some embodiments, the first interface 124 a and the second interface 124 b are symmetrical to each other, but the disclosure is not limited thereto. The structural characteristics of the first interface 124 a and the second interface 124 b are respectively similar to those of the interface 24 shown in FIG. 1F, and is not described again.
  • The connectors 17 a of the die 20 a and the connectors 17 b of the die 20 b are laterally covered by and in contact with the first encapsulant 122 a, and are separated from the second encapsulant 123 a. The corner β1 of the die 20 a and the corner θ1 of the die 20 b are covered by and in contact with the first encapsulant 122 a. The corner β2 of the die 20 a and the corner θ2 of the die 20 b are covered by and in contact with the first encapsulant 122 a or/and the second encapsulant 123 a. In some embodiments in which the interface 124 is on the edges of the dies 20 a and 20 b, and not connected to the second sidewalls 40 b of the dies 20 a and 20 b (shown as the dotted line C′), the corner β2 of the die 20 a and the corner θ2 of the die 20 b are covered by the second encapsulant 123 a.
  • In some embodiments, the top surfaces of passivation layer 15 a and the passivation layer 15 b are covered by the first encapsulant 122 a, and are not in contact with the second encapsulant 123 a, but the disclosure is not limited thereto. In some other embodiments, a portion of the top surface of the passivation layer 15 a adjacent to the corner β2 of the die 20 a, and a portion of the top surface of the passivation layer 15 b adjacent to the corner θ2 of the die 20 b are not covered by the first encapsulant 122 a, but covered by the second encapsulant 123 a (shown as the dotted line C′).
  • Thereafter, the package structure 150 a may further be electrically coupled to other package components such as a printed circuit board (PCB), a flex PCB, or the like through the connectors 27.
  • Referring to FIG. 5, in some embodiments in which the first encapsulant material layer 122 further extend to encapsulate the second sidewalls 40 b of the dies 20 a and 20 b, a package structure 150 b is formed. The package structure 150 b is similar to the package structure 150 a, but differs from the package structure 150 a in that the first encapsulant 122 a further extends to cover the second sidewalls 40 b of the dies 20 a and 20 b, and the other structural characteristics of the package structure 150 b are substantially the same as those of the package structure 150 a.
  • Still referring to FIG. 5, in the package structure 150 b, the first encapsulant 122 a laterally encapsulates and contacts with the first sidewalls 40 a and the second sidewalls 40 b of the dies 20 a and 20 b, and is on the dies 20 a and 20 b, encapsulating and contacting with the sidewalls of the connectors 17 a and 17 b, and the top surfaces of the passivation layers 15 a and 15 b of the die 20 a.
  • The second encapsulant 123 a is located aside the first encapsulant 122 a, encapsulating the sidewalls of the first encapsulant 122 a. The second encapsulant 123 a is not in contact with the second sidewalls 40 b of the dies 20 a/20 b, but separated from the dies 20 a/20 b by the first encapsulant 122 a therebetween.
  • The interface 124′ between the first encapsulant 122 a and the encapsulant 123 a is not in contact with the edge of the dies 20 a and 20 b, or connected to the second sidewalls 40 b of the dies 20 a and 20 b. Instead, portions of the interface 124′ are located aside the second sidewalls 40 b of the dies 20 a and 20 b. The interface 124′ includes a first interface 124 a′ aside the second sidewall 40 b of the die 20 a, and a second interface 124 b′ aside the second sidewall 40 b of the die 20 b. In some embodiments, the first interface 124 a′ and the second interface 124 b′ are symmetrical to each other, but the disclosure is not limited thereto. The structural characteristics of the first interface 124 a′ and the second interface 124 b′ are respectively similar to those of the interface 24′ shown in FIG. 4, and is not described again.
  • FIG. 3A to FIG. 3F are schematic cross-sectional views illustrating a forming method of a package structure according to a third embodiment of the disclosure. The third embodiment is similar to the foregoing embodiments, but differs from the foregoing embodiments in that, the sidewalls of the connectors 17 a are surrounded by and in contact with a protection layer 18 a of a die 120 a, and the sidewalls of the connectors 17 b are surrounded by and in contact with a protection layer 18 b of a die 120 b.
  • Referring to FIG. 3A, processes similar to those described in FIG. 1A are performed, a de-bonding layer 11 is formed on a carrier 10, a die 120 a and a die 120 b are attached to the de-bonding 11 through an adhesive layer 12. The structural characteristics of the die 120 a are substantially the same as those of the die 120 a in the first embodiment. The die 120 b differs from the die 20 b in that, the die 120 further includes a protection layer 18 b. The protection layer 18 b is formed on the passivation layer 15 b, and aside the connectors 17 b, surrounding and covering the sidewalls of the connectors 17 b. In some embodiments, the top surface of the protection layer 18 b and the top surfaces of the connectors 17 b are substantially coplanar with each other. A gap 21 is existed between the die 120 a and the die 120 b.
  • Referring to FIG. 3B and FIG. 3C, a first encapsulant material layer 222 is formed to fill the gap 21 between the die 120 a and the die 120 b. The first encapsulant material layer 222 at least encapsulates the first sidewalls 40 a of the dies 120 a and 120 b. In some embodiments, the first encapsulant material layer 222 may protrudes from the top surfaces of the dies 120 a and 120 b. In some embodiments, the first encapsulant material layer 222 may further cover a portion of the top surface of the die 120 a or/and a portion of the top surface of the die 120 b.
  • A second encapsulant material layer 223 is formed on the carrier 10, the dies 120 a and 120 b, and the first encapsulant material layer 222. The materials and the forming methods of the first encapsulant material layer 222 and the second encapsulant material layer 223 are substantially the same as those of the first encapsulant material layer 22 and the second encapsulant material layer 23 described in the first embodiment, respectively.
  • Referring to FIG. 3C and FIG. 3D, a planarization process is performed, and a portion of the first encapsulant material layer 222 and a portion of the second encapsulant material layer 223 are removed, such that the top surfaces of the connectors 17 a and the connectors 17 b are exposed, a first encapsulant 222 a and a second encapsulant 223 a are formed.
  • Referring to FIG. 3E and FIG. 3F, thereafter, a RDL structure 26 and a plurality of connectors 27 are formed on the dies 120 a and 120 b, the first encapsulant 222 a and the second encapsulant 223 a. The die 120 a and the die 120 b are electrically connected to each other through the RDL structure 26. The connectors 27 are electrically connected to the dies 120 a and 120 b through the RDL structure 26.
  • The de-bonding layer 11 is decomposed under the heat of light, and the carrier 10 is then released. In some embodiments, the adhesive layer 12 is removed. The bottom surfaces (or referred as back surfaces) of the dies 120 a and 120 b are exposed.
  • Referring to FIG. 3F, a package structure 250 is thus completed. The package structure 250 includes the two dies 120 a and 120 b, the first encapsulant 222 a, the second encapsulant 223a, the RDL structure 26 and the connectors 27.
  • The first encapsulant 222 a is located between the die 120 a and the die 120 b, that is, aside the first sidewalls 40 a of the dies 120 a and 120 b, encapsulating and contacting with the first sidewalls 40 a of the dies 120 a and 120 b. In some embodiments, the cross-section shape of the first encapsulant 222 a includes I-shape, rectangle, square, or a combination thereof. The second encapsulant 223 a is located aside, encapsulates and contacts with the second sidewalls 40 b of the dies 120 a and 120 b. In this embodiment, the first encapsulant 222 a and the second encapsulant 223 a are not in contact with each other. The connectors 17 a and 17 b are not in contact with the first encapsulant 222 a or the second encapsulant 223 a, but are respectively surrounded by and in contact with the protection layers 18 a and 18 b. Interfaces are existed between the protection layer 18 a/18 b and the first encapsulant 222 a or between the protection layer 18 a/18 b and the second encapsulant 223 a, and the interfaces may be straight or inclined.
  • Thereafter, the package structure 250 may further be electrically coupled to other package components such as a printed circuit board (PCB), a flex PCB, or the like through the connectors 27.
  • FIG. 6 is a flow chart illustrating a method of forming a package structure according to some embodiments of the disclosure. Referring to FIG. 6, in step S10, a first encapsulant is formed at least between a first die and a second die. In step S12, a second encapsulant is formed aside a sidewall of the first die and a sidewall of the second die. In step S14, a redistribution layer (RDL) structure is formed on the first die, the second die, the first encapsulant, and the second encapsulant. In step S16, a plurality of conductive terminals are electrically connected to the first die and the second die through the RDL structure.
  • In the foregoing embodiments, package structure including two dies and method of manufacturing the same are illustrated. However, the disclosure is not limited thereto, the disclosure may also applied to single die package structure including one die or multiple die package structure including more than two dies.
  • In the embodiments of the disclosure, the encapsulant including a first encapsulant and a second encapsulant aside the dies are formed of two different materials by two step processes. The first encapsulant is formed at least aside the first sidewalls of the two dies, the second encapsulant is formed aside the second sidewalls of the two dies. The first encapsulant is formed of a material comprising fine fillers or no filler. Therefore, the problem of roughness surface or even pits may be caused by large filler are avoided. On the other hand, the first encapsulant is formed at least between the two dies, especially under the traces connecting the two dies. In other words, the traces of the bottommost redistribution layer are routing over the first encapsulant or/and the protection layer of the die in which no filler or fine filler is included. Therefore, the traces may achieve a fine quality, and the trace broken (open) and bridge (short) issues may occur due to the roughness of the encapsulant is avoided.
  • In accordance with some embodiments of the disclosure, a package structure includes a first die and a second die, a first encapsulant, a second encapsulant and a RDL structure. The first die includes a first connector and a first protection layer covering sidewalls of the first connector, and the second die includes a second connector. The first encapsulant is at least disposed laterally between the first die and the second die to encapsulate first sidewalls of the first die and the second die that faces each other. The second encapsulant encapsulates second sidewalls of the first die and the second die. The RDL structure is disposed on and electrically connected to the first die and the second die. The top surfaces of the first protection layer, the first encapsulant, and the second encapsulant are in contact with a bottom surface of the RDL structure.
  • In accordance with alternative embodiments of the disclosure, a package structure includes a first die and a second die, a first encapsulant, a second encapsulant and a conductive terminal. The first die includes a first connector, and the second includes a second connector. The first encapsulant is laterally between the first die and the second die and on the second die. The first connector is separated from the first encapsulant by a protection layer of the first die, and the second connector of the second die is in contact with the first encapsulant. The second encapsulant laterally encapsulates the first die, the second die and the first encapsulant. The conductive terminal is electrically connected to the first die and the second die through a RDL structure.
  • In accordance with some embodiments of the disclosure, a method of forming a package structure includes: providing a first die and a second die, wherein the first die comprises a first connector and a first protection layer covering sidewalls of the first connector, and the second die comprises a second connector; forming a first encapsulant at least between the first die and the second die; forming a second encapsulant to laterally encapsulate the first die and the second die, wherein the first encapsulant and the second encapsulant are formed by different processes; and forming a redistribution layer (RDL) structure on and electrically connected to the first die and the second die, wherein top surfaces of the first protection layer, the first encapsulant and the second encapsulant are in contact with a bottom surface of the RDL structure.
  • The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the disclosure.

Claims (20)

What is claimed is:
1. A package structure, comprising:
a first die and a second die, wherein the first die comprises a first connector and a first protection layer covering sidewalls of the first connector, the second die comprises a second connector;
a first encapsulant, at least disposed laterally between the first die and the second die to encapsulate first sidewalls of the first die and the second die that faces each other; and
a second encapsulant, encapsulating second sidewalls of the first die and the second die; and
a redistribution layer (RDL) structure, disposed on and electrically connected to the first die and the second die, wherein top surfaces of the first protection layer, the first encapsulant and the second encapsulant are in contact with a bottom surface of the RDL structure.
2. The package structure of claim 1, wherein sidewalls of the first protection layer are covered by and in physical contact with the first encapsulant and the second encapsulant.
3. The package structure of claim 1, where the first encapsulant is further disposed to encapsulate sidewalls of the second connector of the second die.
4. The package structure of claim 1, wherein the second die further comprises a second protection layer disposed to cover sidewalls of the second connector, and sidewalls of the second protection layer are covered by the first encapsulant and the second encapsulant.
5. The package structure of claim 1, wherein the first connector of the first die is separated from the first encapsulant and the second encapsulant by the first protection layer.
6. The package structure of claim 1, wherein interfaces are existed between the first protection layer and the first encapsulant, and between the first protection layer and the second encapsulant.
7. The package structure of claim 1, wherein the first encapsulant and the second encapsulant comprise fillers, while the protection layer is free of fillers.
8. The package structure of claim 1, wherein the first encapsulant and the second encapsulant comprise different materials.
9. The package structure of claim 1, wherein the first encapsulant comprises a first filler, the second encapsulant comprises a second filler, and a particle size of the first filler is less than a particle size of the second filler.
10. A package structure, comprising:
a first die and a second die, wherein the first die comprises a first connector, and the second die comprises a second connector;
a first encapsulant, laterally between the first die and the second die, and on the second die, wherein the first connector is separated from the first encapsulant by a protection layer of the first die, and the second connector of the second die is in contact with the first encapsulant;
a second encapsulant, laterally encapsulating the first die, the second die and the first encapsulant; and
a conductive terminal, electrically connected to the first die and the second die through a redistribution layer (RDL) structure.
11. The package structure of claim 10, wherein a top surface of the protection layer of the first die is substantially coplanar with a top surface of the first encapsulant.
12. The package structure of claim 10, wherein the RDL structure comprises a redistribution layer electrically connected to the first die and the second die, the redistribution layer comprises:
a first via, landing on the first connector of the first die;
a second via, landing on the second connector of the second die; and
a trace, extending from the first via to the second via, wherein the trace is overlapped with the protection layer and the first encapsulant in a direction perpendicular to a top surface of the first die.
13. The package structure of claim 10, wherein a portion of the second encapsulant is vertically sandwiched between the first encapsulant and the RDL structure.
14. The package structure of claim 10, wherein a portion of first encapsulant further extends to be sandwiched between a sidewall of the second die and the second encapsulant.
15. The package structure of claim 10, wherein an interface is existed between the first encapsulant and the second encapsulant.
16. A method of forming a package structure, comprising:
providing a first die and a second die, wherein the first die comprises a first connector and a first protection layer covering sidewalls of the first connector, and the second die comprises a second connector;
forming a first encapsulant at least between the first die and the second die;
forming a second encapsulant to laterally encapsulate the first die and the second die, wherein the first encapsulant and the second encapsulant are formed by different processes; and
forming a redistribution layer (RDL) structure on and electrically connected to the first die and the second die, wherein top surfaces of the first protection layer, the first encapsulant and the second encapsulant are in contact with a bottom surface of the RDL structure.
17. The method of claim 16, wherein forming the first encapsulant and the second encapsulant comprises:
forming a first encapsulant material layer to fill a gap between the first die and the second die;
forming a second encapsulant material layer to encapsulate the first die, the second die and the first encapsulant material layer; and
performing a planarization process to remove excess portions of the first encapsulant material layer and the second encapsulant material layer, so as to expose the first connector and the first protection layer of the first die and the second connector of the second die.
18. The method of claim 17, wherein the first encapsulant material layer is formed by a dispensing process, while the second encapsulant material layer is formed by a molding process.
19. The method of claim 16, wherein the first encapsulant is further formed to encapsulate sidewalls of the second connector of the second die.
20. The method of claim 16, wherein the second die further comprises a second protection layer covering sidewalls of the second connector, and the first encapsulant is formed to be laterally sandwiched between the first protection layer and the second protection layer.
US17/207,748 2017-11-13 2021-03-22 Package structure and method of manufacturing the same Abandoned US20210210464A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US17/207,748 US20210210464A1 (en) 2017-11-13 2021-03-22 Package structure and method of manufacturing the same
US18/786,606 US20240387457A1 (en) 2017-11-13 2024-07-29 Package structure and method of manufacturing the same

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201762584914P 2017-11-13 2017-11-13
US15/835,466 US10957672B2 (en) 2017-11-13 2017-12-08 Package structure and method of manufacturing the same
US17/207,748 US20210210464A1 (en) 2017-11-13 2021-03-22 Package structure and method of manufacturing the same

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US15/835,466 Continuation US10957672B2 (en) 2017-11-13 2017-12-08 Package structure and method of manufacturing the same

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US18/786,606 Division US20240387457A1 (en) 2017-11-13 2024-07-29 Package structure and method of manufacturing the same

Publications (1)

Publication Number Publication Date
US20210210464A1 true US20210210464A1 (en) 2021-07-08

Family

ID=66432704

Family Applications (3)

Application Number Title Priority Date Filing Date
US15/835,466 Active US10957672B2 (en) 2017-11-13 2017-12-08 Package structure and method of manufacturing the same
US17/207,748 Abandoned US20210210464A1 (en) 2017-11-13 2021-03-22 Package structure and method of manufacturing the same
US18/786,606 Pending US20240387457A1 (en) 2017-11-13 2024-07-29 Package structure and method of manufacturing the same

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US15/835,466 Active US10957672B2 (en) 2017-11-13 2017-12-08 Package structure and method of manufacturing the same

Family Applications After (1)

Application Number Title Priority Date Filing Date
US18/786,606 Pending US20240387457A1 (en) 2017-11-13 2024-07-29 Package structure and method of manufacturing the same

Country Status (1)

Country Link
US (3) US10957672B2 (en)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10957672B2 (en) * 2017-11-13 2021-03-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
KR102497570B1 (en) * 2018-01-18 2023-02-10 삼성전자주식회사 Semiconductor device
KR20210057828A (en) * 2018-10-09 2021-05-21 마이크론 테크놀로지, 인크 Method of forming a device, and associated devices and electronic systems
US11410875B2 (en) * 2018-12-19 2022-08-09 Texas Instruments Incorporated Fan-out electronic device
US11367657B2 (en) * 2019-08-01 2022-06-21 Semiconductor Components Industries, Llc Process of forming an electronic device including a polymer support layer
EP3772094A3 (en) * 2019-08-01 2023-01-04 MediaTek Inc. Chip scale package structure and method of forming the same
US11139268B2 (en) * 2019-08-06 2021-10-05 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method of manufacturing the same
US11075131B2 (en) * 2019-08-22 2021-07-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of forming the same
CN112582283B (en) * 2019-09-29 2023-11-21 矽磐微电子(重庆)有限公司 Semiconductor packaging method and semiconductor packaging structure
US11508655B2 (en) * 2020-01-08 2022-11-22 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
US11894341B2 (en) * 2020-01-30 2024-02-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package with through vias and stacked redistribution layers and manufacturing method thereof
TWI734401B (en) * 2020-03-06 2021-07-21 矽品精密工業股份有限公司 Electronic package
US11302683B2 (en) * 2020-04-01 2022-04-12 Taiwan Semiconductor Manufacturing Co., Ltd. Optical signal processing package structure
US11450615B2 (en) * 2020-06-12 2022-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of fabricating the same
US11538761B2 (en) * 2021-01-07 2022-12-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package having molded die and semiconductor die and manufacturing method thereof
US20220367366A1 (en) * 2021-05-13 2022-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and method of manufacturing the same
US12374645B2 (en) * 2022-03-25 2025-07-29 Advanced Micro Devices, Inc. Electronic device including dies and an interconnect coupled to the dies and processes of forming the same

Citations (153)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6049124A (en) * 1997-12-10 2000-04-11 Intel Corporation Semiconductor package
US20020004257A1 (en) * 2000-03-24 2002-01-10 Yuji Takaoka Semiconductor device and process for fabricating the same
US6356453B1 (en) * 2000-06-29 2002-03-12 Amkor Technology, Inc. Electronic package having flip chip integrated circuit and passive chip component
US20020031868A1 (en) * 1998-07-21 2002-03-14 Capote Miguel Albert Semiconductor flip-chip package and method for the fabrication thereof
US6424033B1 (en) * 1999-08-31 2002-07-23 Micron Technology, Inc. Chip package with grease heat sink and method of making
US20030008510A1 (en) * 2000-12-06 2003-01-09 Grigg Ford B. Thin flip-chip method
US6700209B1 (en) * 1999-12-29 2004-03-02 Intel Corporation Partial underfill for flip-chip electronic packages
US20040266163A1 (en) * 2003-06-30 2004-12-30 Advanced Semiconductor Engineering, Inc. Bumping process
US20050155706A1 (en) * 1999-01-29 2005-07-21 Kazuto Nishida Electronic component mounting method and apparatus
US20060001152A1 (en) * 2004-07-02 2006-01-05 Phoenix Precision Technology Corporation Direct connection multi-chip semiconductor element structure
US20060063312A1 (en) * 2004-06-30 2006-03-23 Nec Electronics Corporation Semiconductor device and method for manufacturing the same
US20060138671A1 (en) * 2004-12-24 2006-06-29 Kiyonori Watanabe Semiconductor device and fabrication method thereof
US20060163749A1 (en) * 2005-01-25 2006-07-27 Taiwan Semiconductor Manufacturing Co., Ltd. IC chip package structure and underfill process
US20060226542A1 (en) * 2005-04-11 2006-10-12 Siliconware Precision Industries Co., Ltd. Semiconductor device and fabrication method thereof
US20070096306A1 (en) * 2005-10-05 2007-05-03 Sony Corporation Semiconductor device and fabrication method thereof
US20070126127A1 (en) * 2002-08-09 2007-06-07 Casio Computer Co., Ltd. Semiconductor device and method of manufacturing the same
US20070164279A1 (en) * 2005-12-05 2007-07-19 Megica Corporation Semiconductor chip
US20070205520A1 (en) * 2006-03-02 2007-09-06 Megica Corporation Chip package and method for fabricating the same
US20070275503A1 (en) * 2006-05-18 2007-11-29 Megica Corporation Method for fabricating chip package
US7323360B2 (en) * 2001-10-26 2008-01-29 Intel Corporation Electronic assemblies with filled no-flow underfill
US20080308934A1 (en) * 2007-04-23 2008-12-18 Flipchip International, Llc Solder bump interconnect for improved mechanical and thermo-mechanical performance
US20090032974A1 (en) * 2007-07-31 2009-02-05 International Business Machines Corporation Method and structure to reduce cracking in flip chip underfill
US20090203170A1 (en) * 2005-05-17 2009-08-13 Matsushita Electric Industrial Co., Ltd Flip chip mounting method, flip chip mounting apparatus and flip chip mounting body
US20090283877A1 (en) * 2008-05-16 2009-11-19 Xintec Inc. Semiconductor device and manufacturing method thereof
US20090296364A1 (en) * 2008-05-28 2009-12-03 Shinko Electric Industries Co., Ltd. Wiring substrate and semiconductor package
US20100123239A1 (en) * 2008-11-17 2010-05-20 Shinko Electric Industries Co., Ltd. Semiconductor package and method of manufacturing the same
US7843074B2 (en) * 2006-09-12 2010-11-30 Lumination Llc Underfill for light emitting device
US7846770B2 (en) * 2007-07-23 2010-12-07 Commissariat A L'energie Atomique Method for coating two elements hybridized by means of a soldering material
US20110095413A1 (en) * 2009-10-22 2011-04-28 Hans-Joachim Barth Method and Apparatus for Semiconductor Device Fabrication Using a Reconstituted Wafer
US20110193235A1 (en) * 2010-02-05 2011-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC Architecture with Die Inside Interposer
US20110215470A1 (en) * 2010-03-04 2011-09-08 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy Wafers in 3DIC Package Assemblies
US20110278736A1 (en) * 2008-12-12 2011-11-17 Stats Chippac, Ltd. Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP
US20120007230A1 (en) * 2010-07-08 2012-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive bump for semiconductor substrate and method of manufacture
US20120028411A1 (en) * 2010-07-30 2012-02-02 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded Wafer-Level Bonding Approaches
US20120104578A1 (en) * 2010-10-14 2012-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Approach for Bonding Dies onto Interposers
US20120161279A1 (en) * 2010-12-22 2012-06-28 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Integrated Passive Device Over Semiconductor Die with Conductive Bridge and Fan-Out Redistribution Layer
US20120193779A1 (en) * 2011-01-28 2012-08-02 Chung-Sun Lee Semiconductor device and method of fabricating the same
US8294283B2 (en) * 2009-12-07 2012-10-23 Fujitsu Semiconductor Limited Semiconductor device and manufacturing method thereof
US20130062760A1 (en) * 2010-10-14 2013-03-14 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging Methods and Structures Using a Die Attach Film
US8399295B2 (en) * 2010-02-04 2013-03-19 Fujitsu Limited Semiconductor device and its manufacture method
US20130119552A1 (en) * 2011-11-16 2013-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method for Forming Chip-on-Wafer Assembly
US20130134559A1 (en) * 2011-11-30 2013-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-Wafer Structures and Methods for Forming the Same
US20130161784A1 (en) * 2011-12-23 2013-06-27 Samsung Electronics Co., Ltd. Semiconductor package
US20130187258A1 (en) * 2012-01-23 2013-07-25 Taiwan Semiconductor Manufacturing Company, Ltd. Sawing Underfill in Packaging Processes
US20130187270A1 (en) * 2012-01-23 2013-07-25 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-Chip Fan Out Package and Methods of Forming the Same
US20130200529A1 (en) * 2011-09-02 2013-08-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device Packaging Methods and Structures Thereof
US20130244378A1 (en) * 2012-03-13 2013-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Underfill curing method using carrier
US20130264684A1 (en) * 2012-04-09 2013-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and Apparatus of Wafer Level Package for Heterogeneous Integration Technology
US20130307143A1 (en) * 2012-05-18 2013-11-21 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level packaging mechanisms
US8680647B2 (en) * 2011-12-29 2014-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with passive devices and methods of forming the same
US20140091473A1 (en) * 2012-09-28 2014-04-03 Taiwan Semiconductor Manufacturing Company, Ltd. Novel three dimensional integrated circuits stacking approach
US20140120663A1 (en) * 2009-04-24 2014-05-01 Panasonic Corporation Mounting method and mounting structure for semiconductor package component
US20140131856A1 (en) * 2012-11-09 2014-05-15 Won Chul Do Semiconductor device and manufacturing method thereof
US20140183761A1 (en) * 2013-01-03 2014-07-03 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Embedded Wafer Level Chip Scale Packages
US8785299B2 (en) * 2012-11-30 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package with a fan-out structure and method of forming the same
US20140225222A1 (en) * 2013-02-11 2014-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US8809996B2 (en) * 2012-06-29 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package with passive devices and method of forming the same
US20140252579A1 (en) * 2013-03-08 2014-09-11 Taiwan Semiconductor Manufacturing Company, Ltd 3D-Packages and Methods for Forming the Same
US20140264791A1 (en) * 2013-03-14 2014-09-18 Mathew J. Manusharow Direct external interconnect for embedded interconnect bridge package
US20140264930A1 (en) * 2013-03-15 2014-09-18 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-Out Interconnect Structure and Method for Forming Same
US20140360759A1 (en) * 2013-06-05 2014-12-11 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
US20150041980A1 (en) * 2013-08-06 2015-02-12 Amkor Technology, Inc. Semiconductor Package with Reduced Thickness
US20150076713A1 (en) * 2013-09-13 2015-03-19 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated Fan-Out Package Structures with Recesses in Molding Compound
US20150084190A1 (en) * 2013-08-01 2015-03-26 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-Chip Package Structure and Method of Forming Same
US20150084191A1 (en) * 2013-08-01 2015-03-26 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-Chip Package and Method of Formation
US20150102468A1 (en) * 2013-10-16 2015-04-16 Un-Byoung Kang Chip-stacked semiconductor package and method of manufacturing the same
US20150108634A1 (en) * 2013-10-18 2015-04-23 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US20150116965A1 (en) * 2013-10-30 2015-04-30 Qualcomm Incorporated Embedded bridge structure in a substrate
US20150125994A1 (en) * 2011-08-30 2015-05-07 Taiwan Semiconductor Manufacturing Company, Ltd. Die-to-Die Gap Control for Semiconductor Structure and Method
US20150162289A1 (en) * 2013-12-09 2015-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. Protective Layer for Contact Pads in Fan-out Interconnect Structure and Method of Forming Same
US20150162316A1 (en) * 2013-12-10 2015-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged Semiconductor Devices and Methods of Packaging Semiconductor Devices
US20150200188A1 (en) * 2014-01-10 2015-07-16 Taiwan Semiconductor Manufacturing Company Limited Semiconductor package, semiconductor device and method of forming the same
US20150228624A1 (en) * 2014-02-12 2015-08-13 Shinko Electric Industries Co., Ltd. Semiconductor device and method of manufacturing the same
US20150255312A1 (en) * 2014-03-05 2015-09-10 International Business Machines Corporation Low-stress dual underfill packaging
US20150255426A1 (en) * 2014-03-04 2015-09-10 Amkor Technology, Inc. Semiconductor device with reduced warpage
US20150279776A1 (en) * 2014-03-31 2015-10-01 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated Structure in Wafer Level Package
US20150287697A1 (en) * 2014-04-02 2015-10-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device and Method
US20150294939A1 (en) * 2014-04-14 2015-10-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packages and Packaging Methods for Semiconductor Devices, and Packaged Semiconductor Devices
US20160056126A1 (en) * 2014-08-20 2016-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures for wafer level package and methods of forming same
US20160071820A1 (en) * 2014-09-05 2016-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming
US20160071829A1 (en) * 2014-09-05 2016-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. Packages and Methods of Forming Packages
US20160118272A1 (en) * 2011-06-28 2016-04-28 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect Structure for Wafer Level Package
US20160133538A1 (en) * 2014-02-13 2016-05-12 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged Semiconductor Devices and Methods of Packaging Semiconductor Devices
US20160163683A1 (en) * 2012-11-08 2016-06-09 Taiwan Semiconductor Manufacturing Company, Ltd. POP Structures with Dams Encircling Air Gaps and Methods for Forming the Same
US9373588B2 (en) * 2013-09-24 2016-06-21 Intel Corporation Stacked microelectronic dice embedded in a microelectronic substrate
US20160240508A1 (en) * 2015-02-13 2016-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Package Structures and Methods of Forming the Same
US20160276248A1 (en) * 2015-03-16 2016-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Non-vertical through-via in package
US9484307B2 (en) * 2015-01-26 2016-11-01 Advanced Semiconductor Engineering, Inc. Fan-out wafer level packaging structure
US20160329284A1 (en) * 2015-05-04 2016-11-10 Qualcomm Incorporated Semiconductor package with high density die to die connection and method of making the same
US20160343592A1 (en) * 2015-03-25 2016-11-24 Qorvo Us, Inc. Flip chip module with enhanced properties
US20160358865A1 (en) * 2015-06-03 2016-12-08 Inotera Memories, Inc. Wafer level package and fabrication method thereof
US20170005071A1 (en) * 2015-07-02 2017-01-05 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method for chip package
US20170062370A1 (en) * 2015-08-31 2017-03-02 Shinko Electric Industries Co., Ltd. Electronic component device
US9589903B2 (en) * 2015-03-16 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Eliminate sawing-induced peeling through forming trenches
US20170133311A1 (en) * 2013-05-09 2017-05-11 Advanced Semiconductor Engineering, Inc. Semiconductor package and manufacturing method thereof
US20170141053A1 (en) * 2015-11-16 2017-05-18 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated Fan-Out Structure and Method of Forming
US20170186679A1 (en) * 2012-11-15 2017-06-29 Amkor Technology, Inc. Semiconductor Device Package and Manufacturing Method Thereof
US20170194292A1 (en) * 2016-01-06 2017-07-06 Taiwan Semiconductor Manufacturing Company, Ltd. Devices Employing Thermal and Mechanical Enhanced Layers and Methods of Forming Same
US20170221819A1 (en) * 2016-01-29 2017-08-03 Taiwan Semiconductor Manufacturing Company, Ltd. Wireless Charging Package with Chip Integrated in Coil Center
US20170243800A1 (en) * 2014-08-20 2017-08-24 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect Structures for Wafer Level Package and Methods of Forming Same
US20170287871A1 (en) * 2016-03-29 2017-10-05 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
US9812381B1 (en) * 2016-05-31 2017-11-07 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US20170352613A1 (en) * 2016-06-03 2017-12-07 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US9847269B2 (en) * 2015-07-31 2017-12-19 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out packages and methods of forming same
US20170365581A1 (en) * 2016-06-15 2017-12-21 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US20180047713A1 (en) * 2015-03-24 2018-02-15 Intel Corporation Method of fabricating an optical module that includes an electronic package
US20180061811A1 (en) * 2016-08-30 2018-03-01 Chipmos Technologies Inc. Semiconductor package and manufacturing method thereof
US20180068980A1 (en) * 2016-09-08 2018-03-08 Freescale Semiconductor, Inc. Multiple interconnections between die
US20180102343A1 (en) * 2016-10-07 2018-04-12 Mediatek Inc. Semiconductor package with improved bandwidth
US20180138101A1 (en) * 2016-11-14 2018-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming the same
US20180138151A1 (en) * 2016-11-14 2018-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming the same
US20180166420A1 (en) * 2016-12-13 2018-06-14 Samsung Electronics Co., Ltd. Semiconductor package and fabrication method thereof
US20180190560A1 (en) * 2016-12-30 2018-07-05 Intel Corporation Electronic package assembly with compact die placement
US10032704B2 (en) * 2015-02-13 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing cracking by adjusting opening size in pop packages
US20180211929A1 (en) * 2017-01-23 2018-07-26 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US10074604B1 (en) * 2017-04-28 2018-09-11 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US20180287005A1 (en) * 2017-03-31 2018-10-04 Asahi Kasei Microdevices Corporation Optical device and method for manufacturing the same
US20180294241A1 (en) * 2017-04-07 2018-10-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with Si-substrate-free Interposer and Method Forming Same
US20180366436A1 (en) * 2017-06-15 2018-12-20 Invensas Corporation Multi-Chip Modules Formed Using Wafer-Level Processing of a Reconstitute Wafer
US20190006307A1 (en) * 2016-01-22 2019-01-03 Sj Semiconductor (Jiangyin) Corporation Package method and package structure of fan-out chip
US20190013273A1 (en) * 2017-07-06 2019-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package with dual sides of metal routing
US20190043848A1 (en) * 2017-08-04 2019-02-07 Mediatek Inc. Semiconductor package assembly and method for forming the same
US20190067104A1 (en) * 2017-08-31 2019-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive vias in semiconductor packages and methods of forming same
US20190067037A1 (en) * 2017-08-29 2019-02-28 Ciena Corporation Flip-chip high speed components with underfill
US10269744B2 (en) * 2014-03-04 2019-04-23 Amkor Technology, Inc. Semiconductor device with thin redistribution layers
US20190148340A1 (en) * 2017-11-13 2019-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of manufacturing the same
US20190189563A1 (en) * 2016-09-29 2019-06-20 Intel Corporation Panel level packaging for multi-die products interconnected with very high density (vhd) interconnect layers
US20190237423A1 (en) * 2018-01-30 2019-08-01 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of manufacturing the same
US20190279938A1 (en) * 2016-12-29 2019-09-12 Intel Corporation Semiconductor package having wafer-level active die and external die mount
US20200006251A1 (en) * 2018-06-29 2020-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. Supporting InFO Packages to Reduce Warpage
US20200020628A1 (en) * 2018-07-16 2020-01-16 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out packages and methods of forming the same
US20200105684A1 (en) * 2017-03-14 2020-04-02 Mediatek Inc. Semiconductor package structure
US20200168548A1 (en) * 2018-11-23 2020-05-28 Mediatek Inc. Semiconductor package structure and method for forming the same
US20200227394A1 (en) * 2019-01-15 2020-07-16 Omnivision Technologies, Inc. Semiconductor device package and method of manufacturing the same
US20200365571A1 (en) * 2019-05-16 2020-11-19 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of manufacturing the same
US10879170B2 (en) * 2019-04-21 2020-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
US20210020574A1 (en) * 2019-07-17 2021-01-21 Taiwan Semiconductor Manufacturing Company, Ltd. Package with Bridge Die For Interconnection and Method Forming Same
US20210118812A1 (en) * 2019-10-17 2021-04-22 Advanced Semiconductor Engineering, Inc. Package structure, assembly structure and method for manufacturing the same
US20210125885A1 (en) * 2019-10-29 2021-04-29 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of forming the same
US20210134770A1 (en) * 2019-11-05 2021-05-06 Samsung Electronics Co., Ltd. Method of transferring micro-light emitting diode for led display
US20210134711A1 (en) * 2019-11-06 2021-05-06 Advanced Semiconductor Engineering, Inc. Package structure, assembly structure and method for manufacturing the same
US20210159188A1 (en) * 2019-11-22 2021-05-27 Advanced Semiconductor Engineering, Inc. Package structure and method for manufacturing the same
US20210157052A1 (en) * 2019-11-27 2021-05-27 Taiwan Semiconductor Manufacturing Co., Ltd. Package and method of forming same
US20210193542A1 (en) * 2019-12-19 2021-06-24 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of manufacturing the same
US20210202336A1 (en) * 2019-12-30 2021-07-01 Advanced Semiconductor Engineering, Inc. Package structure and method for manufacturing the same
US20210375978A1 (en) * 2020-05-28 2021-12-02 Hitachi, Ltd. Semiconductor detector and method of manufacturing the same
US11244909B2 (en) * 2020-03-12 2022-02-08 Advanced Semiconductor Engineering, Inc. Package structure and method for manufacturing the same
US20220068839A1 (en) * 2020-08-26 2022-03-03 Advanced Semiconductor Engineering, Inc. Package structure and method for manufacturing the same
US20220181267A1 (en) * 2020-12-03 2022-06-09 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
US20220310577A1 (en) * 2021-03-26 2022-09-29 Samsung Electronics Co., Ltd. Semiconductor package
US11600590B2 (en) * 2019-03-22 2023-03-07 Advanced Semiconductor Engineering, Inc. Semiconductor device and semiconductor package
US20230084360A1 (en) * 2021-09-10 2023-03-16 Innolux Corporation Electronic device and manufacturing method thereof
US20230307372A1 (en) * 2022-03-25 2023-09-28 International Business Machines Corporation Multichip interconnect package fine jet underfill

Family Cites Families (108)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3454888B2 (en) * 1993-11-24 2003-10-06 富士通株式会社 Electronic component unit and method of manufacturing the same
US5866953A (en) * 1996-05-24 1999-02-02 Micron Technology, Inc. Packaged die on PCB with heat sink encapsulant
US6338980B1 (en) * 1999-08-13 2002-01-15 Citizen Watch Co., Ltd. Method for manufacturing chip-scale package and manufacturing IC chip
JP2001094005A (en) * 1999-09-22 2001-04-06 Oki Electric Ind Co Ltd Semiconductor device and method of manufacturing semiconductor device
JP3973340B2 (en) * 1999-10-05 2007-09-12 Necエレクトロニクス株式会社 Semiconductor device, wiring board, and manufacturing method thereof
US6856007B2 (en) * 2001-08-28 2005-02-15 Tessera, Inc. High-frequency chip packages
US6972964B2 (en) * 2002-06-27 2005-12-06 Via Technologies Inc. Module board having embedded chips and components and method of forming the same
US6919508B2 (en) * 2002-11-08 2005-07-19 Flipchip International, Llc Build-up structures with multi-angle vias for chip to chip interconnects and optical bussing
US20060272150A1 (en) * 2003-07-03 2006-12-07 Syuuji Eguchi Module and method for fabricating the same
US7382620B2 (en) * 2005-10-13 2008-06-03 International Business Machines Corporation Method and apparatus for optimizing heat transfer with electronic components
JP2008091638A (en) * 2006-10-02 2008-04-17 Nec Electronics Corp Electronic device and manufacturing method thereof
US7830004B2 (en) * 2006-10-27 2010-11-09 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging with base layers comprising alloy 42
US20080160751A1 (en) * 2006-12-28 2008-07-03 Mengzhi Pang Microelectronic die including solder caps on bumping sites thereof and method of making same
JPWO2008105535A1 (en) * 2007-03-01 2010-06-03 日本電気株式会社 Semiconductor device and manufacturing method thereof
JP4975514B2 (en) * 2007-04-26 2012-07-11 信越化学工業株式会社 DIE BONDING AGENT AND SEMICONDUCTOR DEVICE USING THE SAME
US7838424B2 (en) * 2007-07-03 2010-11-23 Taiwan Semiconductor Manufacturing Company, Ltd. Enhanced reliability of wafer-level chip-scale packaging (WLCSP) die separation using dry etching
US10074553B2 (en) * 2007-12-03 2018-09-11 STATS ChipPAC Pte. Ltd. Wafer level package integration and method
US7759212B2 (en) * 2007-12-26 2010-07-20 Stats Chippac, Ltd. System-in-package having integrated passive devices and method therefor
US8033012B2 (en) * 2008-03-07 2011-10-11 Taiwan Semiconductor Manufacturing Co., Ltd. Method for fabricating a semiconductor test probe card space transformer
US8354742B2 (en) * 2008-03-31 2013-01-15 Stats Chippac, Ltd. Method and apparatus for a package having multiple stacked die
US20100109169A1 (en) * 2008-04-29 2010-05-06 United Test And Assembly Center Ltd Semiconductor package and method of making the same
US20090309238A1 (en) * 2008-06-13 2009-12-17 Mun Leong Loke Molded flip chip package with enhanced mold-die adhesion
US9117828B2 (en) * 2009-03-27 2015-08-25 Taiwan Semiconductor Manufacturing Company, Ltd. Method of handling a thin wafer
US9136144B2 (en) * 2009-11-13 2015-09-15 Stats Chippac, Ltd. Method of forming protective material between semiconductor die stacked on semiconductor wafer to reduce defects during singulation
TWI392069B (en) * 2009-11-24 2013-04-01 日月光半導體製造股份有限公司 Package structure and packaging process
JP5570799B2 (en) * 2009-12-17 2014-08-13 ピーエスフォー ルクスコ エスエイアールエル Semiconductor device and manufacturing method thereof
US9576919B2 (en) * 2011-12-30 2017-02-21 Deca Technologies Inc. Semiconductor device and method comprising redistribution layers
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US8598695B2 (en) * 2010-07-23 2013-12-03 Tessera, Inc. Active chip on carrier or laminated chip having microelectronic element embedded therein
KR20120060665A (en) * 2010-12-02 2012-06-12 삼성전자주식회사 Semiconductor package
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
JP2012191062A (en) * 2011-03-11 2012-10-04 Toshiba Corp Semiconductor device
KR101739939B1 (en) * 2011-03-16 2017-05-26 삼성전자주식회사 Method of forming semiconductor device
KR20120123919A (en) * 2011-05-02 2012-11-12 삼성전자주식회사 Method for manufacturing a chip stacked semiconductor package and the chip stacked semiconductor package thereof
US8557684B2 (en) * 2011-08-23 2013-10-15 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional integrated circuit (3DIC) formation process
US9013037B2 (en) * 2011-09-14 2015-04-21 Stmicroelectronics Pte Ltd. Semiconductor package with improved pillar bump process and structure
KR101906408B1 (en) * 2011-10-04 2018-10-11 삼성전자주식회사 Semiconductor package and method of manufacturing the same
US8664040B2 (en) * 2011-12-20 2014-03-04 Taiwan Semiconductor Manufacturing Company, Ltd. Exposing connectors in packages through selective treatment
US9000584B2 (en) * 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
KR101896665B1 (en) * 2012-01-11 2018-09-07 삼성전자주식회사 Semiconductor package
JP2013149660A (en) * 2012-01-17 2013-08-01 Elpida Memory Inc Method for manufacturing semiconductor device
US8686570B2 (en) * 2012-01-20 2014-04-01 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-dimensional integrated circuit structures and methods of forming the same
US20130307153A1 (en) 2012-05-18 2013-11-21 International Business Machines Corporation Interconnect with titanium-oxide diffusion barrier
KR20150060758A (en) * 2012-10-02 2015-06-03 피에스4 뤽스코 에스.에이.알.엘. Semiconductor device and method for manufacturing same
US9799592B2 (en) * 2013-11-19 2017-10-24 Amkor Technology, Inc. Semicondutor device with through-silicon via-less deep wells
US8803306B1 (en) * 2013-01-18 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package structure and methods for forming the same
KR102029646B1 (en) * 2013-01-31 2019-11-08 삼성전자 주식회사 Method for fabricating semiconductor device
US20140246227A1 (en) * 2013-03-01 2014-09-04 Bridge Semiconductor Corporation Method of making cavity substrate with built-in stiffener and cavity substrate manufactured thereby
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
KR20140124631A (en) * 2013-04-17 2014-10-27 삼성전자주식회사 Flip chip Semiconductor package
US20160329304A1 (en) * 2013-05-07 2016-11-10 Ps4 Luxco S.A.R.L. Semiconductor device and method of manufacturing semiconductor device
US9633869B2 (en) * 2013-08-16 2017-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with interposers and methods for forming the same
US9209046B2 (en) * 2013-10-02 2015-12-08 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
KR102107961B1 (en) * 2013-11-14 2020-05-28 삼성전자 주식회사 Semiconductor device and method for fabricating the same
US9805997B2 (en) * 2014-01-27 2017-10-31 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods for semiconductor devices with encapsulant ring
US9406650B2 (en) * 2014-01-31 2016-08-02 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of packaging semiconductor devices and packaged semiconductor devices
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9230936B2 (en) * 2014-03-04 2016-01-05 Qualcomm Incorporated Integrated device comprising high density interconnects and redistribution layers
US9355997B2 (en) * 2014-03-12 2016-05-31 Invensas Corporation Integrated circuit assemblies with reinforcement frames, and methods of manufacture
US9418877B2 (en) * 2014-05-05 2016-08-16 Qualcomm Incorporated Integrated device comprising high density interconnects in inorganic layers and redistribution layers in organic layers
US9455236B2 (en) * 2014-06-13 2016-09-27 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit packages and methods of forming same
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
KR101995141B1 (en) * 2014-06-26 2019-07-02 도판 인사츠 가부시키가이샤 Wiring board, semiconductor device and method for manufacturing semiconductor device
JP6358431B2 (en) * 2014-08-25 2018-07-18 新光電気工業株式会社 Electronic component device and manufacturing method thereof
US9548273B2 (en) * 2014-12-04 2017-01-17 Invensas Corporation Integrated circuit assemblies with rigid layers used for protection against mechanical thinning and for other purposes, and methods of fabricating such assemblies
JP6318084B2 (en) * 2014-12-17 2018-04-25 新光電気工業株式会社 Semiconductor device and manufacturing method thereof
US10032969B2 (en) * 2014-12-26 2018-07-24 Nichia Corporation Light emitting device
WO2016111512A1 (en) * 2015-01-09 2016-07-14 Samsung Electronics Co., Ltd. Semiconductor package and method of manufacturing the same
US9583462B2 (en) * 2015-01-22 2017-02-28 Qualcomm Incorporated Damascene re-distribution layer (RDL) in fan out split die application
US10074630B2 (en) * 2015-04-14 2018-09-11 Amkor Technology, Inc. Semiconductor package with high routing density patch
US9601471B2 (en) * 2015-04-23 2017-03-21 Apple Inc. Three layer stack structure
KR102327142B1 (en) * 2015-06-11 2021-11-16 삼성전자주식회사 Wafer Level Package
US9478504B1 (en) * 2015-06-19 2016-10-25 Invensas Corporation Microelectronic assemblies with cavities, and methods of fabrication
JP6444269B2 (en) * 2015-06-19 2018-12-26 新光電気工業株式会社 Electronic component device and manufacturing method thereof
US9786976B2 (en) * 2015-06-24 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Transmission line design and method, where high-k dielectric surrounds the transmission line for increased isolation
US9806058B2 (en) * 2015-07-02 2017-10-31 Taiwan Semiconductor Manufacturing Company, Ltd. Chip package having die structures of different heights and method of forming same
US9735079B2 (en) * 2015-10-08 2017-08-15 Dyi-chung Hu Molding compound wrapped package substrate
US9640498B1 (en) * 2015-10-20 2017-05-02 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out (InFO) package structures and methods of forming same
FR3047604B1 (en) * 2016-02-04 2018-02-02 Commissariat A L'energie Atomique Et Aux Energies Alternatives HUMIDITY PROTECTED HYBRID ELECTRONIC DEVICE AND HUMIDITY PROTECTION METHOD OF HYBRID ELECTRONIC DEVICE
KR102579876B1 (en) * 2016-02-22 2023-09-18 삼성전자주식회사 Semiconductor package
US10037974B2 (en) * 2016-03-08 2018-07-31 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US10002857B2 (en) * 2016-04-12 2018-06-19 Qualcomm Incorporated Package on package (PoP) device comprising thermal interface material (TIM) in cavity of an encapsulation layer
US9922895B2 (en) * 2016-05-05 2018-03-20 Taiwan Semiconductor Manufacturing Company, Ltd. Package with tilted interface between device die and encapsulating material
US20180005916A1 (en) * 2016-06-30 2018-01-04 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US9793230B1 (en) * 2016-07-08 2017-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method of forming
US10672741B2 (en) * 2016-08-18 2020-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages with thermal-electrical-mechanical chips and methods of forming the same
KR102508526B1 (en) * 2016-08-24 2023-03-09 삼성전자주식회사 Method for manufacturing semiconductor package
US10475775B2 (en) * 2016-08-31 2019-11-12 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
US10014260B2 (en) * 2016-11-10 2018-07-03 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
US10424539B2 (en) * 2016-12-21 2019-09-24 Advanced Semiconductor Engineering, Inc. Wiring structure, semiconductor package structure and semiconductor process
US10381301B2 (en) * 2017-02-08 2019-08-13 Micro Technology, Inc. Semiconductor package and method for fabricating the same
US10784211B2 (en) * 2017-03-14 2020-09-22 Mediatek Inc. Semiconductor package structure
US20180286704A1 (en) * 2017-04-01 2018-10-04 Intel Corporation Processes and methods for applying underfill to singulated die
KR20180112394A (en) * 2017-04-03 2018-10-12 에스케이하이닉스 주식회사 Method of fabricating semiconductor package and semiconductor package by the same
US10014218B1 (en) * 2017-04-20 2018-07-03 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming semiconductor device structure with bumps
US10276536B2 (en) * 2017-04-28 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of chip package with fan-out structure
US10727198B2 (en) * 2017-06-30 2020-07-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method manufacturing the same
US10283428B2 (en) * 2017-06-30 2019-05-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method manufacturing the same
US10685934B2 (en) * 2017-07-10 2020-06-16 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
US10461014B2 (en) * 2017-08-31 2019-10-29 Taiwan Semiconductor Manufacturing Company, Ltd. Heat spreading device and method
US10276508B2 (en) * 2017-09-28 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor packages and methods of forming the same
US10797022B2 (en) * 2017-10-06 2020-10-06 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US10163825B1 (en) * 2017-10-26 2018-12-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US10636715B2 (en) * 2017-11-06 2020-04-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method of fabricating the same
US10522440B2 (en) * 2017-11-07 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of manufacturing the same
US10867954B2 (en) * 2017-11-15 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect chips
TWI631676B (en) * 2017-12-08 2018-08-01 矽品精密工業股份有限公司 Electronic package and its manufacturing method
KR102397902B1 (en) * 2018-01-29 2022-05-13 삼성전자주식회사 Semiconductor package

Patent Citations (177)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6049124A (en) * 1997-12-10 2000-04-11 Intel Corporation Semiconductor package
US20020031868A1 (en) * 1998-07-21 2002-03-14 Capote Miguel Albert Semiconductor flip-chip package and method for the fabrication thereof
US20050155706A1 (en) * 1999-01-29 2005-07-21 Kazuto Nishida Electronic component mounting method and apparatus
US6424033B1 (en) * 1999-08-31 2002-07-23 Micron Technology, Inc. Chip package with grease heat sink and method of making
US6700209B1 (en) * 1999-12-29 2004-03-02 Intel Corporation Partial underfill for flip-chip electronic packages
US20040113245A1 (en) * 2000-03-24 2004-06-17 Yuji Takaoka Semiconductor device and process for fabricating the same
US20020004257A1 (en) * 2000-03-24 2002-01-10 Yuji Takaoka Semiconductor device and process for fabricating the same
US6356453B1 (en) * 2000-06-29 2002-03-12 Amkor Technology, Inc. Electronic package having flip chip integrated circuit and passive chip component
US20030008510A1 (en) * 2000-12-06 2003-01-09 Grigg Ford B. Thin flip-chip method
US7323360B2 (en) * 2001-10-26 2008-01-29 Intel Corporation Electronic assemblies with filled no-flow underfill
US20070126127A1 (en) * 2002-08-09 2007-06-07 Casio Computer Co., Ltd. Semiconductor device and method of manufacturing the same
US20040266163A1 (en) * 2003-06-30 2004-12-30 Advanced Semiconductor Engineering, Inc. Bumping process
US20060063312A1 (en) * 2004-06-30 2006-03-23 Nec Electronics Corporation Semiconductor device and method for manufacturing the same
US20060001152A1 (en) * 2004-07-02 2006-01-05 Phoenix Precision Technology Corporation Direct connection multi-chip semiconductor element structure
US20060138671A1 (en) * 2004-12-24 2006-06-29 Kiyonori Watanabe Semiconductor device and fabrication method thereof
US20060163749A1 (en) * 2005-01-25 2006-07-27 Taiwan Semiconductor Manufacturing Co., Ltd. IC chip package structure and underfill process
US20060226542A1 (en) * 2005-04-11 2006-10-12 Siliconware Precision Industries Co., Ltd. Semiconductor device and fabrication method thereof
US20090203170A1 (en) * 2005-05-17 2009-08-13 Matsushita Electric Industrial Co., Ltd Flip chip mounting method, flip chip mounting apparatus and flip chip mounting body
US20070096306A1 (en) * 2005-10-05 2007-05-03 Sony Corporation Semiconductor device and fabrication method thereof
US20070164279A1 (en) * 2005-12-05 2007-07-19 Megica Corporation Semiconductor chip
US20070205520A1 (en) * 2006-03-02 2007-09-06 Megica Corporation Chip package and method for fabricating the same
US20070275503A1 (en) * 2006-05-18 2007-11-29 Megica Corporation Method for fabricating chip package
US7843074B2 (en) * 2006-09-12 2010-11-30 Lumination Llc Underfill for light emitting device
US20080308934A1 (en) * 2007-04-23 2008-12-18 Flipchip International, Llc Solder bump interconnect for improved mechanical and thermo-mechanical performance
US7846770B2 (en) * 2007-07-23 2010-12-07 Commissariat A L'energie Atomique Method for coating two elements hybridized by means of a soldering material
US20090032974A1 (en) * 2007-07-31 2009-02-05 International Business Machines Corporation Method and structure to reduce cracking in flip chip underfill
US20090283877A1 (en) * 2008-05-16 2009-11-19 Xintec Inc. Semiconductor device and manufacturing method thereof
US20090296364A1 (en) * 2008-05-28 2009-12-03 Shinko Electric Industries Co., Ltd. Wiring substrate and semiconductor package
US20100123239A1 (en) * 2008-11-17 2010-05-20 Shinko Electric Industries Co., Ltd. Semiconductor package and method of manufacturing the same
US20110278736A1 (en) * 2008-12-12 2011-11-17 Stats Chippac, Ltd. Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP
US20140120663A1 (en) * 2009-04-24 2014-05-01 Panasonic Corporation Mounting method and mounting structure for semiconductor package component
US9331047B2 (en) * 2009-04-24 2016-05-03 Panasonic Intellectual Property Management Co., Ltd. Mounting method and mounting structure for semiconductor package component
US20110095413A1 (en) * 2009-10-22 2011-04-28 Hans-Joachim Barth Method and Apparatus for Semiconductor Device Fabrication Using a Reconstituted Wafer
US20140335654A1 (en) * 2009-10-22 2014-11-13 Infineon Technologies Ag Method and Apparatus for Semiconductor Device Fabrication Using a Reconstituted Wafer
US8294283B2 (en) * 2009-12-07 2012-10-23 Fujitsu Semiconductor Limited Semiconductor device and manufacturing method thereof
US8399295B2 (en) * 2010-02-04 2013-03-19 Fujitsu Limited Semiconductor device and its manufacture method
US20110193235A1 (en) * 2010-02-05 2011-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC Architecture with Die Inside Interposer
US20110215470A1 (en) * 2010-03-04 2011-09-08 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy Wafers in 3DIC Package Assemblies
US20120007230A1 (en) * 2010-07-08 2012-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive bump for semiconductor substrate and method of manufacture
US8361842B2 (en) * 2010-07-30 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded wafer-level bonding approaches
US20120028411A1 (en) * 2010-07-30 2012-02-02 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded Wafer-Level Bonding Approaches
US20130062760A1 (en) * 2010-10-14 2013-03-14 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging Methods and Structures Using a Die Attach Film
US20120104578A1 (en) * 2010-10-14 2012-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Approach for Bonding Dies onto Interposers
US20120161279A1 (en) * 2010-12-22 2012-06-28 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Integrated Passive Device Over Semiconductor Die with Conductive Bridge and Fan-Out Redistribution Layer
US20120193779A1 (en) * 2011-01-28 2012-08-02 Chung-Sun Lee Semiconductor device and method of fabricating the same
US20140091460A1 (en) * 2011-01-28 2014-04-03 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
US8604615B2 (en) * 2011-01-28 2013-12-10 Samsung Electronics Co., Ltd. Semiconductor device including a stack of semiconductor chips, underfill material and molding material
US9553000B2 (en) * 2011-06-28 2017-01-24 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for wafer level package
US20160118272A1 (en) * 2011-06-28 2016-04-28 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect Structure for Wafer Level Package
US20150125994A1 (en) * 2011-08-30 2015-05-07 Taiwan Semiconductor Manufacturing Company, Ltd. Die-to-Die Gap Control for Semiconductor Structure and Method
US20130200529A1 (en) * 2011-09-02 2013-08-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device Packaging Methods and Structures Thereof
US20140287553A1 (en) * 2011-11-16 2014-09-25 Taiwan Semiconductor Manufacturing Company, Ltd. Method for Forming Chip-on-Wafer Assembly
US20130119552A1 (en) * 2011-11-16 2013-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method for Forming Chip-on-Wafer Assembly
US20140134802A1 (en) * 2011-11-30 2014-05-15 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-Wafer Structures and Methods for Forming the Same
US20130134559A1 (en) * 2011-11-30 2013-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-Wafer Structures and Methods for Forming the Same
US20130161784A1 (en) * 2011-12-23 2013-06-27 Samsung Electronics Co., Ltd. Semiconductor package
US8680647B2 (en) * 2011-12-29 2014-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with passive devices and methods of forming the same
US20130187270A1 (en) * 2012-01-23 2013-07-25 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-Chip Fan Out Package and Methods of Forming the Same
US20130187258A1 (en) * 2012-01-23 2013-07-25 Taiwan Semiconductor Manufacturing Company, Ltd. Sawing Underfill in Packaging Processes
US20170294409A1 (en) * 2012-01-23 2017-10-12 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-Chip Fan Out Package and Methods of Forming the Same
US20170213809A1 (en) * 2012-01-23 2017-07-27 Taiwan Semiconductor Manufacturing Company, Ltd. Sawing Underfill in Packaging Processes
US20130244378A1 (en) * 2012-03-13 2013-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Underfill curing method using carrier
US20130264684A1 (en) * 2012-04-09 2013-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and Apparatus of Wafer Level Package for Heterogeneous Integration Technology
US20140197535A1 (en) * 2012-05-18 2014-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level packaging mechanisms
US20130307143A1 (en) * 2012-05-18 2013-11-21 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level packaging mechanisms
US8703542B2 (en) * 2012-05-18 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level packaging mechanisms
US8809996B2 (en) * 2012-06-29 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package with passive devices and method of forming the same
US20140091473A1 (en) * 2012-09-28 2014-04-03 Taiwan Semiconductor Manufacturing Company, Ltd. Novel three dimensional integrated circuits stacking approach
US20160163683A1 (en) * 2012-11-08 2016-06-09 Taiwan Semiconductor Manufacturing Company, Ltd. POP Structures with Dams Encircling Air Gaps and Methods for Forming the Same
US20140131856A1 (en) * 2012-11-09 2014-05-15 Won Chul Do Semiconductor device and manufacturing method thereof
US20170186679A1 (en) * 2012-11-15 2017-06-29 Amkor Technology, Inc. Semiconductor Device Package and Manufacturing Method Thereof
US8785299B2 (en) * 2012-11-30 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package with a fan-out structure and method of forming the same
US20140183761A1 (en) * 2013-01-03 2014-07-03 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Embedded Wafer Level Chip Scale Packages
US20140225222A1 (en) * 2013-02-11 2014-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US20140252579A1 (en) * 2013-03-08 2014-09-11 Taiwan Semiconductor Manufacturing Company, Ltd 3D-Packages and Methods for Forming the Same
US20140264791A1 (en) * 2013-03-14 2014-09-18 Mathew J. Manusharow Direct external interconnect for embedded interconnect bridge package
US20140264930A1 (en) * 2013-03-15 2014-09-18 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-Out Interconnect Structure and Method for Forming Same
US20170133311A1 (en) * 2013-05-09 2017-05-11 Advanced Semiconductor Engineering, Inc. Semiconductor package and manufacturing method thereof
US20140360759A1 (en) * 2013-06-05 2014-12-11 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
US20150084190A1 (en) * 2013-08-01 2015-03-26 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-Chip Package Structure and Method of Forming Same
US20150084191A1 (en) * 2013-08-01 2015-03-26 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-Chip Package and Method of Formation
US20190139922A1 (en) * 2013-08-01 2019-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-Chip Package and Method of Formation
US20150041980A1 (en) * 2013-08-06 2015-02-12 Amkor Technology, Inc. Semiconductor Package with Reduced Thickness
US20150076713A1 (en) * 2013-09-13 2015-03-19 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated Fan-Out Package Structures with Recesses in Molding Compound
US9373588B2 (en) * 2013-09-24 2016-06-21 Intel Corporation Stacked microelectronic dice embedded in a microelectronic substrate
US20150102468A1 (en) * 2013-10-16 2015-04-16 Un-Byoung Kang Chip-stacked semiconductor package and method of manufacturing the same
US20150108634A1 (en) * 2013-10-18 2015-04-23 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US20150116965A1 (en) * 2013-10-30 2015-04-30 Qualcomm Incorporated Embedded bridge structure in a substrate
US20150162289A1 (en) * 2013-12-09 2015-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. Protective Layer for Contact Pads in Fan-out Interconnect Structure and Method of Forming Same
US20150162316A1 (en) * 2013-12-10 2015-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged Semiconductor Devices and Methods of Packaging Semiconductor Devices
US20170092634A1 (en) * 2014-01-10 2017-03-30 Taiwan Semiconductor Manufacturing Company Limited Semiconductor Package, Semiconductor Device and Method of Forming the Same
US20150200188A1 (en) * 2014-01-10 2015-07-16 Taiwan Semiconductor Manufacturing Company Limited Semiconductor package, semiconductor device and method of forming the same
US20150228624A1 (en) * 2014-02-12 2015-08-13 Shinko Electric Industries Co., Ltd. Semiconductor device and method of manufacturing the same
US20160133538A1 (en) * 2014-02-13 2016-05-12 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged Semiconductor Devices and Methods of Packaging Semiconductor Devices
US10269744B2 (en) * 2014-03-04 2019-04-23 Amkor Technology, Inc. Semiconductor device with thin redistribution layers
US20150255426A1 (en) * 2014-03-04 2015-09-10 Amkor Technology, Inc. Semiconductor device with reduced warpage
US20160049345A1 (en) * 2014-03-05 2016-02-18 International Business Machines Corporation Low-stress dual underfill packaging
US20150255312A1 (en) * 2014-03-05 2015-09-10 International Business Machines Corporation Low-stress dual underfill packaging
US20150279776A1 (en) * 2014-03-31 2015-10-01 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated Structure in Wafer Level Package
US20150287697A1 (en) * 2014-04-02 2015-10-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device and Method
US20150294939A1 (en) * 2014-04-14 2015-10-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packages and Packaging Methods for Semiconductor Devices, and Packaged Semiconductor Devices
US20160056126A1 (en) * 2014-08-20 2016-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures for wafer level package and methods of forming same
US20170243800A1 (en) * 2014-08-20 2017-08-24 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect Structures for Wafer Level Package and Methods of Forming Same
US20160071829A1 (en) * 2014-09-05 2016-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. Packages and Methods of Forming Packages
US20200294967A1 (en) * 2014-09-05 2020-09-17 Taiwan Semiconductor Manufacturing Co., Ltd. Package Structures and Methods of Forming
US20160071820A1 (en) * 2014-09-05 2016-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming
US9484307B2 (en) * 2015-01-26 2016-11-01 Advanced Semiconductor Engineering, Inc. Fan-out wafer level packaging structure
US9564416B2 (en) * 2015-02-13 2017-02-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming the same
US10032704B2 (en) * 2015-02-13 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing cracking by adjusting opening size in pop packages
US9859267B2 (en) * 2015-02-13 2018-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming the same
US20160240508A1 (en) * 2015-02-13 2016-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Package Structures and Methods of Forming the Same
US9589903B2 (en) * 2015-03-16 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Eliminate sawing-induced peeling through forming trenches
US10115647B2 (en) * 2015-03-16 2018-10-30 Taiwan Semiconductor Manufacturing Company, Ltd. Non-vertical through-via in package
US20160276248A1 (en) * 2015-03-16 2016-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Non-vertical through-via in package
US20180047713A1 (en) * 2015-03-24 2018-02-15 Intel Corporation Method of fabricating an optical module that includes an electronic package
US20160343592A1 (en) * 2015-03-25 2016-11-24 Qorvo Us, Inc. Flip chip module with enhanced properties
US20160329284A1 (en) * 2015-05-04 2016-11-10 Qualcomm Incorporated Semiconductor package with high density die to die connection and method of making the same
US20160358865A1 (en) * 2015-06-03 2016-12-08 Inotera Memories, Inc. Wafer level package and fabrication method thereof
US20170005071A1 (en) * 2015-07-02 2017-01-05 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method for chip package
US9847269B2 (en) * 2015-07-31 2017-12-19 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out packages and methods of forming same
US20170062370A1 (en) * 2015-08-31 2017-03-02 Shinko Electric Industries Co., Ltd. Electronic component device
US20170141053A1 (en) * 2015-11-16 2017-05-18 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated Fan-Out Structure and Method of Forming
US20170194292A1 (en) * 2016-01-06 2017-07-06 Taiwan Semiconductor Manufacturing Company, Ltd. Devices Employing Thermal and Mechanical Enhanced Layers and Methods of Forming Same
US20190006307A1 (en) * 2016-01-22 2019-01-03 Sj Semiconductor (Jiangyin) Corporation Package method and package structure of fan-out chip
US20170221819A1 (en) * 2016-01-29 2017-08-03 Taiwan Semiconductor Manufacturing Company, Ltd. Wireless Charging Package with Chip Integrated in Coil Center
US20170287871A1 (en) * 2016-03-29 2017-10-05 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
US9812381B1 (en) * 2016-05-31 2017-11-07 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US20170352613A1 (en) * 2016-06-03 2017-12-07 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US20170365581A1 (en) * 2016-06-15 2017-12-21 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US20180130772A1 (en) * 2016-06-15 2018-05-10 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US20180061811A1 (en) * 2016-08-30 2018-03-01 Chipmos Technologies Inc. Semiconductor package and manufacturing method thereof
US20180068980A1 (en) * 2016-09-08 2018-03-08 Freescale Semiconductor, Inc. Multiple interconnections between die
US20190189563A1 (en) * 2016-09-29 2019-06-20 Intel Corporation Panel level packaging for multi-die products interconnected with very high density (vhd) interconnect layers
US20180102343A1 (en) * 2016-10-07 2018-04-12 Mediatek Inc. Semiconductor package with improved bandwidth
US20180138101A1 (en) * 2016-11-14 2018-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming the same
US20190115272A1 (en) * 2016-11-14 2019-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Package Structures and Methods of Forming the Same
US20180138151A1 (en) * 2016-11-14 2018-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming the same
US20180166420A1 (en) * 2016-12-13 2018-06-14 Samsung Electronics Co., Ltd. Semiconductor package and fabrication method thereof
US20190279938A1 (en) * 2016-12-29 2019-09-12 Intel Corporation Semiconductor package having wafer-level active die and external die mount
US20180190560A1 (en) * 2016-12-30 2018-07-05 Intel Corporation Electronic package assembly with compact die placement
US20180211929A1 (en) * 2017-01-23 2018-07-26 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US20200105684A1 (en) * 2017-03-14 2020-04-02 Mediatek Inc. Semiconductor package structure
US20180287005A1 (en) * 2017-03-31 2018-10-04 Asahi Kasei Microdevices Corporation Optical device and method for manufacturing the same
US20180294241A1 (en) * 2017-04-07 2018-10-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with Si-substrate-free Interposer and Method Forming Same
US10074604B1 (en) * 2017-04-28 2018-09-11 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US20180366436A1 (en) * 2017-06-15 2018-12-20 Invensas Corporation Multi-Chip Modules Formed Using Wafer-Level Processing of a Reconstitute Wafer
US20190013273A1 (en) * 2017-07-06 2019-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package with dual sides of metal routing
US20190043848A1 (en) * 2017-08-04 2019-02-07 Mediatek Inc. Semiconductor package assembly and method for forming the same
US20190067037A1 (en) * 2017-08-29 2019-02-28 Ciena Corporation Flip-chip high speed components with underfill
US20190067104A1 (en) * 2017-08-31 2019-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive vias in semiconductor packages and methods of forming same
US20190148340A1 (en) * 2017-11-13 2019-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of manufacturing the same
US20190237423A1 (en) * 2018-01-30 2019-08-01 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of manufacturing the same
US20200006251A1 (en) * 2018-06-29 2020-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. Supporting InFO Packages to Reduce Warpage
US20200020628A1 (en) * 2018-07-16 2020-01-16 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out packages and methods of forming the same
US20210351126A1 (en) * 2018-07-16 2021-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out packages and methods of forming the same
US20200168548A1 (en) * 2018-11-23 2020-05-28 Mediatek Inc. Semiconductor package structure and method for forming the same
US20200227394A1 (en) * 2019-01-15 2020-07-16 Omnivision Technologies, Inc. Semiconductor device package and method of manufacturing the same
US11600590B2 (en) * 2019-03-22 2023-03-07 Advanced Semiconductor Engineering, Inc. Semiconductor device and semiconductor package
US10879170B2 (en) * 2019-04-21 2020-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
US20200365571A1 (en) * 2019-05-16 2020-11-19 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of manufacturing the same
US20210020574A1 (en) * 2019-07-17 2021-01-21 Taiwan Semiconductor Manufacturing Company, Ltd. Package with Bridge Die For Interconnection and Method Forming Same
US20210118812A1 (en) * 2019-10-17 2021-04-22 Advanced Semiconductor Engineering, Inc. Package structure, assembly structure and method for manufacturing the same
US20210125885A1 (en) * 2019-10-29 2021-04-29 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of forming the same
US20210134770A1 (en) * 2019-11-05 2021-05-06 Samsung Electronics Co., Ltd. Method of transferring micro-light emitting diode for led display
US20210134711A1 (en) * 2019-11-06 2021-05-06 Advanced Semiconductor Engineering, Inc. Package structure, assembly structure and method for manufacturing the same
US20210159188A1 (en) * 2019-11-22 2021-05-27 Advanced Semiconductor Engineering, Inc. Package structure and method for manufacturing the same
US20210157052A1 (en) * 2019-11-27 2021-05-27 Taiwan Semiconductor Manufacturing Co., Ltd. Package and method of forming same
US20210193542A1 (en) * 2019-12-19 2021-06-24 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of manufacturing the same
US20210202336A1 (en) * 2019-12-30 2021-07-01 Advanced Semiconductor Engineering, Inc. Package structure and method for manufacturing the same
US11244909B2 (en) * 2020-03-12 2022-02-08 Advanced Semiconductor Engineering, Inc. Package structure and method for manufacturing the same
US20210375978A1 (en) * 2020-05-28 2021-12-02 Hitachi, Ltd. Semiconductor detector and method of manufacturing the same
US20220068839A1 (en) * 2020-08-26 2022-03-03 Advanced Semiconductor Engineering, Inc. Package structure and method for manufacturing the same
US20220181267A1 (en) * 2020-12-03 2022-06-09 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
US11756896B2 (en) * 2020-12-03 2023-09-12 Advanced Semiconductor Engineering, Inc. Semiconductor package structure including shielding layer contacting conductive contact
US20220310577A1 (en) * 2021-03-26 2022-09-29 Samsung Electronics Co., Ltd. Semiconductor package
US20230084360A1 (en) * 2021-09-10 2023-03-16 Innolux Corporation Electronic device and manufacturing method thereof
US20230307372A1 (en) * 2022-03-25 2023-09-28 International Business Machines Corporation Multichip interconnect package fine jet underfill

Also Published As

Publication number Publication date
US20240387457A1 (en) 2024-11-21
US10957672B2 (en) 2021-03-23
US20190148340A1 (en) 2019-05-16

Similar Documents

Publication Publication Date Title
US20240387457A1 (en) Package structure and method of manufacturing the same
US11955459B2 (en) Package structure
US11862469B2 (en) Package structure and method of manufacturing the same
US12334434B2 (en) Package structure and method of forming the same
US10879224B2 (en) Package structure, die and method of manufacturing the same
US11948904B2 (en) Die and package structure
US11145562B2 (en) Package structure and method of manufacturing the same
US10276509B2 (en) Integrated fan-out package
US10879147B1 (en) Method of manufacturing package structure
US10290610B2 (en) PoP device and method of forming the same
US20200294921A1 (en) Package structure and method of manufacturing the same
US11037899B2 (en) Package structures and methods of forming the same
US20250132216A1 (en) Semiconductor package and method of forming the same

Legal Events

Date Code Title Description
STPP Information on status: patent application and granting procedure in general

Free format text: APPLICATION DISPATCHED FROM PREEXAM, NOT YET DOCKETED

STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: FINAL REJECTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: FINAL REJECTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE AFTER FINAL ACTION FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: ADVISORY ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: FINAL REJECTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION