[go: up one dir, main page]

US20200168525A1 - Integrated circuit chip packaging - Google Patents

Integrated circuit chip packaging Download PDF

Info

Publication number
US20200168525A1
US20200168525A1 US16/774,573 US202016774573A US2020168525A1 US 20200168525 A1 US20200168525 A1 US 20200168525A1 US 202016774573 A US202016774573 A US 202016774573A US 2020168525 A1 US2020168525 A1 US 2020168525A1
Authority
US
United States
Prior art keywords
circuit board
integrated circuit
chip
circuit chip
embedded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US16/774,573
Inventor
Young Hoon Kwark
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to US16/774,573 priority Critical patent/US20200168525A1/en
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KWARK, YOUNG HOON
Publication of US20200168525A1 publication Critical patent/US20200168525A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
    • H10W40/22—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H01L21/481—Insulating layers on insulating parts, with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H01L21/4882—Assembly of heatsink parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
    • H01L25/165—Containers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
    • H10W40/037—
    • H10W40/226—
    • H10W40/228—
    • H10W44/20—
    • H10W70/635—
    • H10W70/65—
    • H10W70/68—
    • H10W72/851—
    • H10W90/00—
    • H10W99/00—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6627—Waveguides, e.g. microstrip line, strip line, coplanar line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40105—Connecting bonding areas at different heights
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/40237—Connecting the strap to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45014—Ribbon connectors, e.g. rectangular cross-section
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1903—Structure including wave guides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1903—Structure including wave guides
    • H01L2924/19031—Structure including wave guides being a strip line type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09036—Recesses or grooves in insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09145—Edge details
    • H05K2201/0919—Exposing inner circuit layers or metal planes at the side edge of the printed circuit board [PCB] or at the walls of large holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09145—Edge details
    • H05K2201/092—Exposing inner circuit layers or metal planes at the walls of high aspect ratio holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09845—Stepped hole, via, edge, bump or conductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/049—Wire bonding
    • H10W44/216—
    • H10W70/63—
    • H10W70/682—
    • H10W72/07251—
    • H10W72/07554—
    • H10W72/20—
    • H10W72/534—
    • H10W72/536—
    • H10W72/5363—
    • H10W72/547—
    • H10W72/647—
    • H10W72/871—
    • H10W90/724—
    • H10W90/764—

Definitions

  • the present invention generally relates to integrated circuit chip packaging. More particularly, the present invention relates to integrated circuit chip packaging connecting an integrated circuit chip to a conductive layer embedded between layers of a printed circuit board.
  • a surface attachment restricts the launch to a conductive layer that is on the surface of a printed circuit board and if a signal from the integrated circuit chip must be launched into a conductive layer that is between the layers of the printed circuit board (i.e., an embedded conductor), then the signal is subject to problems, which may be caused by vias that are used to transfer the signal from the surface to the embedded conductor.
  • an integrated circuit chip may be placed into a carrier a package) and the carrier may then be mounted onto a surface of the printed circuit board.
  • Exemplary conventional techniques arc shown in FIG. 1 .
  • FIG. 1 shows a conventional surface mount package 102 and a conventional flip chip package mounting 104 .
  • the conventional flip chip package mounting 104 connects to the printed circuit board using two via configurations.
  • a first configuration includes a via 106 that has a long stub 107 that extends past an embedded conductor layer 108 .
  • the flip chip 104 is electrically connected to the embedded conductor layer 108 .
  • the second confizuration includes a buried via 110 that sloes not include a lengthy stub and, therefore, avoids the signal degradation associated with a lengthy stub.
  • a buried via 110 is more expensive to fabricate.
  • the conventional surface mount package 102 also shows connection to another embedded conductor 111 , which connects to the distal end of via 109 . This configuration, referred to as a “through via,” minimizes the length of the stub, but the presence of the via still leads to signal distortion.
  • Integrated circuit chips that operate at high frequencies often rely on flip chip packaging to minimize the parasitics that are associated with conventional chip packages.
  • the highest speed signals use conductive surface layers or buried vias in the printed circuit board in order to reduce a via stub effect that may compromise signal transmission.
  • an exemplary feature of the present invention is to provide an integrated circuit chip package in which a cavity in a printed circuit board receives an integrated circuit chip to connect to a conductor that is embedded between layers of a printed circuit board.
  • a printed circuit board has a cavity extending into a surface to a conductor that is embedded between layers of a printed circuit board, an integrated circuit chip is in the cavity, and an electrical connection connects the integrated circuit chip to the embedded conductor.
  • a method of mounting an integrated circuit chip to a printed circuit board includes providing a cavity extending from a surface of the printed circuit board to a conductor that is embedded between layers of a printed circuit board, placing the integrated circuit chip into the cavity, and electrically connecting the integrated circuit Chip to the conductor.
  • a printed circuit board may include a plurality of insulating layers, a conductor embedded between two of the plurality of insulating layers, and a cavity extending from a surface of the printed circuit board to the embedded conductor.
  • the inventors of the present invention discovered that more direct access to a conductor that is embedded between layers of a printed circuit board is desired, without having to rely upon a surface mount or a via to connect to an embedded conductor.
  • a printed circuit board may include alternating stacks of patterned conductors, such as, for example, copper planes. Usually those planes are copper, in which case they may include ground planes or power planes. Alternatively, the planes are patterned into narrower traces to form conductors, which are sandwiched between layers to provide controlled impedance transmission lines. These conductors are, thus, embedded between layers of the printed circuit board and are particularly well suited to transmit high fidelity signals. Other signals, such as power, control connections, or the like, do not need controlled impedance lines and may have varying widths depending upon their functional needs.
  • patterned conductors such as, for example, copper planes. Usually those planes are copper, in which case they may include ground planes or power planes. Alternatively, the planes are patterned into narrower traces to form conductors, which are sandwiched between layers to provide controlled impedance transmission lines. These conductors are, thus, embedded between layers of the printed circuit board and are particularly well suited to transmit high fidelity signals. Other
  • An embedded conductor is superior to a surface conductor because an embedded conductor has better signal fidelity and an embedded conductor is completely shielded, while a surffice conductor is not completely shielded. Therefore, an exemplary embodiment of the present invention is advantageous because the integrated circuit chips no longer need to connect to surface conductors, rather the integrated circuit chips may attach more directly to embedded conductors.
  • An exemplary embodiment of the present invention connects a chip to a conductor embedded between layers of a printed circuit board without using a via.
  • the printed circuit board may be milled to expose an embedded conductor into which a signal from an integrated circuit chip may be launched.
  • the milling may create a cavity that may be shaped to receive the integrated circuit chip.
  • the cavity may be deep enough such that, when the cavity receives the chip, the top of the chip is substantially co-planar with an embedded conductor. In this manner, very short ribbon bonds may be connected between contacts on the chip to the substantially co-planar embedded conductor.
  • a launch into an embedded conductor is generally capable of carrying a signal that incorporates frequency components that exceed 40 Ghz.
  • an exemplary embodiment of the present invention is capable of handling signals incorporating a 40 Ghz component.
  • the printed circuit board includes a step-shaped (e.g., a terraced) side surface that may reveal launch points into a plurality of embedded conductors and non-controlled impedance traces, such as those used for control and power.
  • a step-shaped (e.g., a terraced) side surface that may reveal launch points into a plurality of embedded conductors and non-controlled impedance traces, such as those used for control and power.
  • the best launch exposed by the step-shaped structure is the one that is substantially co-planar with the top of a chip.
  • the remaining launches may be used to handle slower and/or less critical signals.
  • two integrated circuit chips may be connected by a high speed embedded conductor by placing each of these chips into cavities such that the tops of both chips are substantially co-planar with the same embedded conductor.
  • the present invention obviates the necessity of providing vias to connect the two chips to each other.
  • An exemplary embodiment of the present invention may use a precision engraving machine, rather than just a generic milling machine.
  • an exemplary embodiment of the present invention may be adapted to either wire/ribbon bonding or to a flip chip implemenation.
  • This packaging technique offers even higher performance than the conventional techniques mentioned above while at the same time being low in cost.
  • FIG. 1 is a cross-sectional view of a printed circuit board with two conventionally mounted integrated circuit chip packages
  • FIG. 2 is a cross-sectional view of an exemplary embodiment of the present invention.
  • FIG. 3 is a cross-sectional view of the exemplary embodiment of FIG. 2 in a passivated configuration
  • FIG. 4 is a cross-sectional view of another exemplary embodiment of the present invention.
  • FIG. 5 is a flowchart of an exemplary method in accordance with the present invention.
  • FIGS. 1-5 there are shown exemplary embodiments of the method and structures of the present invention.
  • PCBs printed circuit boards
  • Internal embedded conductors which may include an embedded conductor sandwiched between solid planes of a reference ground plane, offer many advantages over surface conductors. Embedded conductors support less dispersive transverse electric and magnetic modes which may be advantageous for wide band operation. An embedded conductor may also be self-shielding and, since they may undergo fewer processing steps than surface wiring they may be easier and less costly to fabricate.
  • a chip may be connected to an embedded conductor using a wire bond, a ribbon bond, or the like, or may be flip chip connected using solder balls, or the like.
  • layers in a printed circuit board 200 may be milled back to create a cavity with a step-shaped side surface 202 .
  • the side surface may have a plurality of steps.
  • the outer surface of the printed circuit board may be milled to form a cavity that extends down to a desired embedded conductor.
  • a side of such a cavity may have a terraced profile (step-shaped side surface) wherein each step of the terraced profile exposes a surface of an embedded conductor.
  • an exposed surface of the embedded conductor may be treated to facilitate bonding.
  • the surface may be plated with a metal (e.g., a noble metal such as gold, platinum, silver, and the like) to improve wire bonding and/or ribbon bonding.
  • a metal e.g., a noble metal such as gold, platinum, silver, and the like
  • the cavity in the printed circuit board extends deep enough into the printed circuit board such that a top of an integrated circuit chip positioned in the recess would be substantially co-planar with an embedded conductor.
  • the embedded conductor may then be provided the highest speed signal more directly from the integrated circuit chip.
  • the top surface 204 of the chip 206 is substantially co-planar with an embedded conductor 208 .
  • an exemplary embodiment of the present invention offers a launch from the chip 206 into the printed circuit board more directly to a desired embedded conductor 208 .
  • the top of the chip 204 may be connected to the highest performance embedded conductor 208 with a ribbon bond 210 because a ribbon bond may offer a higher performance potential.
  • the step-shaped surface of the cavity may also reveal the surfaces of other embedded conductors, which are not substantially co-planar with a top of the chip, in general, as the distance from the top of the chip 204 to an embedded conductor increases, a longer connection will be required.
  • a longer connection will generally offer poorer performance than a shorter connection and, therefore, the printed circuit board may be designed such that, as the distance between an embedded conductor and the top of the chip increases, the less critical a signal will be carried by that respective embedded conductor. For example, most low speed control lines do not require controlled impedance and, therefore, are insensitive to the longer distances that need to be bridged by a wire bond.
  • the less critical connections may use lower performance connections such as, for example, a wire bond and/or a ball bond as opposed to a ribbon bond.
  • a wire bond and/or a ball bond as opposed to a ribbon bond.
  • any type of connection may be used to establish electrical communication between a chip and an embedded conductor and still practice the invention.
  • the embedded conductor 212 which is the next closest to the top of the chip 204 , and a ground plane 214 are also connected to the chip using ribbon bonds 210 .
  • next closest embedded conductors 218 to the top of the chip 204 are connected by ball bonds 218 to the chip 206 .
  • FIG. 2 also illustrates a flip chip package 220 , which may be connected to the printed circuit board 200 in a conventional manner.
  • a printed circuit board may be constructed by laminating many different layers together using, for example, an epoxy resin. That lamination may be done under a high temperature and a pressure to cure the resin. The resin essentially flows between the layers in a pattern sensitive manner depending upon what copper features happen to be nearby. Thus, the surfaces between the layers of a printed circuit board may not necessarily be planar. Rather, the surfaces of the layers may incorporate a bit of waviness depending upon the copper patterns.
  • a conventional milling machine may cut entirely through the embedded conductor, thereby, destroying the embedded conductor in some places, while simultaneously not even reaching the same embedded conductor in another place.
  • a precision milling machine may sense an electrical contact between a cutting edge of the milling machine and a stripline. In this manner, the milling machine may incorporate a closed-loop feedback system that regulates the depth of the milling into the printed circuit board.
  • a closed-loop feedback might not electrically sense the patterned layer of the desired embedded conductor in order to control the depth of the milling process. Rather, a calibration structure that may closely track the local internal waviness may be provided which provides a desired feedback control signal. This may be accomplished either electrically, with optical recognition, or by analyzing the chips as they are received from the milling operation. When copper chips are detected, then the desired target layer has been reached.
  • an embedded conductor Before connecting the leads, but after milling, an embedded conductor may have a bare surface.
  • the bare surfaces of the embedded conductor may be plated with a material which facilitates bonding.
  • a material for plating may include, for example, gold and the like, which may be electro-lessly plated onto a surface of an embedded conductor.
  • a sacrificial plating web may be patterned in the copper and subsequently milled away.
  • ground planes in a printed circuit board may be electrically connected to each other using a via in close proximity to the milled cavity in order to maintain tight coupling between the planes for embedded conductor integrity.
  • FIG. 3 illustrates an exemplary embodiment of a printed circuit board 300 in accordance with the present invention.
  • the step-shaped surface 302 and the chip 304 are incorporated into the printed circuit board 300 in a final passivated configuration.
  • the printed circuit board 300 includes an underfill material 306 which fills the recess 308 in the printed circuit board 300 to protect the chip 304 and the connections 310 from the chip 304 to the embedded conductors 312 within the printed circuit board 300 .
  • the printed circuit board 300 also includes a thermal slug 314 mounted to a top surface 316 of the chip 304 and a heat sink 318 mounted to an outer surface 320 of the thermal slug 314 to conduct thermal energy away from the printed circuit board 300 .
  • the chip may be accessed from the backside for thermal management.
  • an exemplary embodiment 400 of the invention may permit a chip 402 to connect with an embedded conductor 404 using a flip chip connection 406 .
  • the other vias 408 supporting the non-embedded conductor signals from the chip 402 are not buried vias, but are typical through vias that have pads 410 at the level of the embedded conductor 404 .
  • these pads 410 may be revealed in the course of milling a cavity into the printed circuit board. This exemplary method maintains the low cost of through via construction by avoiding the use of buried vias.
  • FIG. 5 illustrates a flowchart 5 for an exemplary method in accordance with the present invention.
  • the flowchart 500 starts at step 502 and continues to step 504 where a cavity is milled into a circuit board to expose an embedded conductor.
  • the flowchart 500 continues to step 506 where an integrated circuit chip is positioned inside the cavity.
  • the integrated circuit chip is electrically connected to the embedded conductor that was exposed in step 504 .
  • the flowchart ends at step 510 .

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Materials Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

A method of mounting an integrated circuit chip to a circuit board includes placing the integrated circuit chip into a cavity extending from a surface of the circuit hoard to an embedded conductor, electrically connecting the integrated circuit chip to the embedded conductor, and disposing a heat sink over a surface of the integrated circuit chip.

Description

  • The present application is a Continuation Application of U.S. patent application Ser. No. 15/589,131, filed on May 8, 2017, which is a Divisional Application of U.S. patent application Ser. No. 11/411,920, filed on Apr. 27, 2006, now U.S. Pat. No. 9,713,258 B2, issued on Jul. 18, 2017, the entire contents of which are incorporated herein by reference.
    • FIELD OF THE INVENTION
  • The present invention generally relates to integrated circuit chip packaging. More particularly, the present invention relates to integrated circuit chip packaging connecting an integrated circuit chip to a conductive layer embedded between layers of a printed circuit board.
    • DESCRIPTION OF THE RELATED ART
  • Conventional methods and systems for connecting an integrated circuit chip to a printed circuit board have relied upon a surface attachment. A surface attachment restricts the launch to a conductive layer that is on the surface of a printed circuit board and if a signal from the integrated circuit chip must be launched into a conductive layer that is between the layers of the printed circuit board (i.e., an embedded conductor), then the signal is subject to problems, which may be caused by vias that are used to transfer the signal from the surface to the embedded conductor.
  • Conventionally, an integrated circuit chip may be placed into a carrier a package) and the carrier may then be mounted onto a surface of the printed circuit board. Exemplary conventional techniques arc shown in FIG. 1.
  • FIG. 1 shows a conventional surface mount package 102 and a conventional flip chip package mounting 104. The conventional flip chip package mounting 104 connects to the printed circuit board using two via configurations. A first configuration includes a via 106 that has a long stub 107 that extends past an embedded conductor layer 108. The flip chip 104 is electrically connected to the embedded conductor layer 108.
  • The second confizuration includes a buried via 110 that sloes not include a lengthy stub and, therefore, avoids the signal degradation associated with a lengthy stub. However, a buried via 110 is more expensive to fabricate. The conventional surface mount package 102 also shows connection to another embedded conductor 111, which connects to the distal end of via 109. This configuration, referred to as a “through via,” minimizes the length of the stub, but the presence of the via still leads to signal distortion.
  • In addition, if many signals try to connect to embedded conductors at the same level of a layer, then wiring congestion may result.
  • Integrated circuit chips that operate at high frequencies often rely on flip chip packaging to minimize the parasitics that are associated with conventional chip packages. For best performance, conventionally, the highest speed signals use conductive surface layers or buried vias in the printed circuit board in order to reduce a via stub effect that may compromise signal transmission.
    • SUMMARY OF THE INVENTION
  • In view of the foregoing and other exemplary problems, drawbacks, and disadvantages of the conventional methods and structures, an exemplary feature of the present invention is to provide an integrated circuit chip package in which a cavity in a printed circuit board receives an integrated circuit chip to connect to a conductor that is embedded between layers of a printed circuit board.
  • In a first exemplary aspect of the present invention, a printed circuit board has a cavity extending into a surface to a conductor that is embedded between layers of a printed circuit board, an integrated circuit chip is in the cavity, and an electrical connection connects the integrated circuit chip to the embedded conductor.
  • In a second exemplary aspect of the present invention, a method of mounting an integrated circuit chip to a printed circuit board includes providing a cavity extending from a surface of the printed circuit board to a conductor that is embedded between layers of a printed circuit board, placing the integrated circuit chip into the cavity, and electrically connecting the integrated circuit Chip to the conductor.
  • In a third exemplary aspect of the present invention, a printed circuit board may include a plurality of insulating layers, a conductor embedded between two of the plurality of insulating layers, and a cavity extending from a surface of the printed circuit board to the embedded conductor.
  • The inventors of the present invention discovered that more direct access to a conductor that is embedded between layers of a printed circuit board is desired, without having to rely upon a surface mount or a via to connect to an embedded conductor.
  • A printed circuit board may include alternating stacks of patterned conductors, such as, for example, copper planes. Usually those planes are copper, in which case they may include ground planes or power planes. Alternatively, the planes are patterned into narrower traces to form conductors, which are sandwiched between layers to provide controlled impedance transmission lines. These conductors are, thus, embedded between layers of the printed circuit board and are particularly well suited to transmit high fidelity signals. Other signals, such as power, control connections, or the like, do not need controlled impedance lines and may have varying widths depending upon their functional needs.
  • An embedded conductor is superior to a surface conductor because an embedded conductor has better signal fidelity and an embedded conductor is completely shielded, while a surffice conductor is not completely shielded. Therefore, an exemplary embodiment of the present invention is advantageous because the integrated circuit chips no longer need to connect to surface conductors, rather the integrated circuit chips may attach more directly to embedded conductors.
  • An exemplary embodiment of the present invention connects a chip to a conductor embedded between layers of a printed circuit board without using a via.
  • In an exemplary embodiment of the present invention, the printed circuit board may be milled to expose an embedded conductor into which a signal from an integrated circuit chip may be launched.
  • In an exemplary embodiment of the present invention, the milling may create a cavity that may be shaped to receive the integrated circuit chip.
  • In an exemplary embodiment of the present invention the cavity may be deep enough such that, when the cavity receives the chip, the top of the chip is substantially co-planar with an embedded conductor. In this manner, very short ribbon bonds may be connected between contacts on the chip to the substantially co-planar embedded conductor.
  • It is advantageous to minimize the length of a wire bond and/or a ribbon bond, because a bond represents a discontinuity. Therefore, milling the cavity such that the top of the chip is substantially co-planar with the launch, minimizes the length of a wire/ribbon bond and, as a result, reduces the adverse affects of the discontinuity.
  • A launch into an embedded conductor is generally capable of carrying a signal that incorporates frequency components that exceed 40 Ghz. Thus, an exemplary embodiment of the present invention is capable of handling signals incorporating a 40 Ghz component.
  • In an exemplary embodiment of the present invention, the printed circuit board includes a step-shaped (e.g., a terraced) side surface that may reveal launch points into a plurality of embedded conductors and non-controlled impedance traces, such as those used for control and power.
  • In general, the best launch exposed by the step-shaped structure is the one that is substantially co-planar with the top of a chip. The remaining launches may be used to handle slower and/or less critical signals.
  • In an exemplary embodiment of the present invention two integrated circuit chips may be connected by a high speed embedded conductor by placing each of these chips into cavities such that the tops of both chips are substantially co-planar with the same embedded conductor. In this manner, the present invention obviates the necessity of providing vias to connect the two chips to each other.
  • An exemplary embodiment of the present invention may use a precision engraving machine, rather than just a generic milling machine.
  • Further, an exemplary embodiment of the present invention may be adapted to either wire/ribbon bonding or to a flip chip implemenation. This packaging technique offers even higher performance than the conventional techniques mentioned above while at the same time being low in cost.
  • These and many other advantages may be achieved with the present invention.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The foregoing and other exemplary purposes, aspects and advantages will be better understood from the following detailed description of an exemplary embodiment of the invention with reference to the drawings, in which:
  • FIG. 1 is a cross-sectional view of a printed circuit board with two conventionally mounted integrated circuit chip packages;
  • FIG. 2 is a cross-sectional view of an exemplary embodiment of the present invention;
  • FIG. 3 is a cross-sectional view of the exemplary embodiment of FIG. 2 in a passivated configuration;
  • FIG. 4 is a cross-sectional view of another exemplary embodiment of the present invention;
  • FIG. 5 is a flowchart of an exemplary method in accordance with the present invention
    •  DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS OF THE INVENTION
  • Referring now to the drawings, and more particularly to FIGS. 1-5, there are shown exemplary embodiments of the method and structures of the present invention.
  • As explained above, there are many topologies conventionally available for implementing transmission lines in circuit boards (e.g., printed circuit boards (PCBs)). Internal embedded conductors, which may include an embedded conductor sandwiched between solid planes of a reference ground plane, offer many advantages over surface conductors. Embedded conductors support less dispersive transverse electric and magnetic modes which may be advantageous for wide band operation. An embedded conductor may also be self-shielding and, since they may undergo fewer processing steps than surface wiring they may be easier and less costly to fabricate.
  • Connecting an integrated circuit chip to embedded conductors conventionally requires the use of vias to connect from the surface of a printed circuit board where components are traditionally attached. However, if the overlying layers are removed from the printed circuit board in accordance with an exemplary embodiment of the present invention (e.g. by milling) these embedded conductors may permit a more direct attachment of these embedded conductors to high speed nets on a chip. A chip may be connected to an embedded conductor using a wire bond, a ribbon bond, or the like, or may be flip chip connected using solder balls, or the like.
  • As illustrated by FIG. 2, in accordance with an exemplary embodiment of the present invention, layers in a printed circuit board 200 may be milled back to create a cavity with a step-shaped side surface 202. As shown, the side surface may have a plurality of steps.
  • In other words, the outer surface of the printed circuit board may be milled to form a cavity that extends down to a desired embedded conductor. Further, a side of such a cavity may have a terraced profile (step-shaped side surface) wherein each step of the terraced profile exposes a surface of an embedded conductor.
  • In another exemplary embodiment of the present invention, after a cavity is formed in the printed circuit board, an exposed surface of the embedded conductor may be treated to facilitate bonding. For example, the surface may be plated with a metal (e.g., a noble metal such as gold, platinum, silver, and the like) to improve wire bonding and/or ribbon bonding.
  • In an exemplary embodiment of the present invention, the cavity in the printed circuit board extends deep enough into the printed circuit board such that a top of an integrated circuit chip positioned in the recess would be substantially co-planar with an embedded conductor. The embedded conductor may then be provided the highest speed signal more directly from the integrated circuit chip.
  • For example, in FIG. 2 the top surface 204 of the chip 206 is substantially co-planar with an embedded conductor 208. In this manner, an exemplary embodiment of the present invention offers a launch from the chip 206 into the printed circuit board more directly to a desired embedded conductor 208. The top of the chip 204 may be connected to the highest performance embedded conductor 208 with a ribbon bond 210 because a ribbon bond may offer a higher performance potential.
  • The step-shaped surface of the cavity may also reveal the surfaces of other embedded conductors, which are not substantially co-planar with a top of the chip, in general, as the distance from the top of the chip 204 to an embedded conductor increases, a longer connection will be required. A longer connection will generally offer poorer performance than a shorter connection and, therefore, the printed circuit board may be designed such that, as the distance between an embedded conductor and the top of the chip increases, the less critical a signal will be carried by that respective embedded conductor. For example, most low speed control lines do not require controlled impedance and, therefore, are insensitive to the longer distances that need to be bridged by a wire bond.
  • Further, the less critical connections may use lower performance connections such as, for example, a wire bond and/or a ball bond as opposed to a ribbon bond. However, one of ordinary skill in the art understands that any type of connection may be used to establish electrical communication between a chip and an embedded conductor and still practice the invention.
  • In the exemplary embodiment illustrated by FIG. 2, the embedded conductor 212, which is the next closest to the top of the chip 204, and a ground plane 214 are also connected to the chip using ribbon bonds 210.
  • Further, the next closest embedded conductors 218 to the top of the chip 204 are connected by ball bonds 218 to the chip 206.
  • FIG. 2 also illustrates a flip chip package 220, which may be connected to the printed circuit board 200 in a conventional manner.
  • A printed circuit board may be constructed by laminating many different layers together using, for example, an epoxy resin. That lamination may be done under a high temperature and a pressure to cure the resin. The resin essentially flows between the layers in a pattern sensitive manner depending upon what copper features happen to be nearby. Thus, the surfaces between the layers of a printed circuit board may not necessarily be planar. Rather, the surfaces of the layers may incorporate a bit of waviness depending upon the copper patterns.
  • Thus, when using a conventional milling machine and open-loop programming on the milling machine to mill down to a certain level into a printed circuit board, there is a likelihood that the milling might not reach a level that corresponds to the level of a desired embedded conductor. The thickness of a patterned copper layer of an embedded conductor is typically about 1 mil and the waviness of a reasonably thick layer of a printed circuit board is typically more than 1 mil. Therefore, a conventional milling machine may cut entirely through the embedded conductor, thereby, destroying the embedded conductor in some places, while simultaneously not even reaching the same embedded conductor in another place.
  • In an exemplary embodiment of the present invention, a precision milling machine may sense an electrical contact between a cutting edge of the milling machine and a stripline. In this manner, the milling machine may incorporate a closed-loop feedback system that regulates the depth of the milling into the printed circuit board.
  • In another exemplary embodiment of the present invention, a closed-loop feedback might not electrically sense the patterned layer of the desired embedded conductor in order to control the depth of the milling process. Rather, a calibration structure that may closely track the local internal waviness may be provided which provides a desired feedback control signal. This may be accomplished either electrically, with optical recognition, or by analyzing the chips as they are received from the milling operation. When copper chips are detected, then the desired target layer has been reached.
  • Before connecting the leads, but after milling, an embedded conductor may have a bare surface. In an exemplary embodiment of the present invention, the bare surfaces of the embedded conductor may be plated with a material which facilitates bonding. A material for plating may include, for example, gold and the like, which may be electro-lessly plated onto a surface of an embedded conductor.
  • Alternatively, if a thicker gold layer is required, then a sacrificial plating web may be patterned in the copper and subsequently milled away.
  • Although not shown in the Figures, ground planes in a printed circuit board may be electrically connected to each other using a via in close proximity to the milled cavity in order to maintain tight coupling between the planes for embedded conductor integrity.
  • FIG. 3 illustrates an exemplary embodiment of a printed circuit board 300 in accordance with the present invention. The step-shaped surface 302 and the chip 304 are incorporated into the printed circuit board 300 in a final passivated configuration. The printed circuit board 300 includes an underfill material 306 which fills the recess 308 in the printed circuit board 300 to protect the chip 304 and the connections 310 from the chip 304 to the embedded conductors 312 within the printed circuit board 300.
  • The printed circuit board 300 also includes a thermal slug 314 mounted to a top surface 316 of the chip 304 and a heat sink 318 mounted to an outer surface 320 of the thermal slug 314 to conduct thermal energy away from the printed circuit board 300.
  • In another exemplary embodiment in accordance with the present invention (not shown), the chip may be accessed from the backside for thermal management.
  • As illustrated by FIG. 4, an exemplary embodiment 400 of the invention may permit a chip 402 to connect with an embedded conductor 404 using a flip chip connection 406.
  • The other vias 408 supporting the non-embedded conductor signals from the chip 402 are not buried vias, but are typical through vias that have pads 410 at the level of the embedded conductor 404.
  • In accordance with an exemplary embodiment of the present invention, these pads 410 may be revealed in the course of milling a cavity into the printed circuit board. This exemplary method maintains the low cost of through via construction by avoiding the use of buried vias.
  • FIG. 5 illustrates a flowchart 5 for an exemplary method in accordance with the present invention. The flowchart 500 starts at step 502 and continues to step 504 where a cavity is milled into a circuit board to expose an embedded conductor. The flowchart 500 continues to step 506 where an integrated circuit chip is positioned inside the cavity. Next, in step 508, the integrated circuit chip is electrically connected to the embedded conductor that was exposed in step 504. The flowchart ends at step 510.
  • While the invention has been described in terms of several exemplary embodiments, those skilled in the art will recognize that the invention can be practiced with modification.
  • Further, it is noted that, Applicant's intent is to encompass equivalents of all claim elements, even if amended later during prosecution.

Claims (20)

What is claimed is:
1. A method of mounting an integrated circuit chip to a circuit board, the method comprising:
placing said integrated circuit chip into a cavity extending from a surface of said circuit board to an embedded conductor:
electrically connecting said integrated circuit chip to said embedded conductor; and
disposing a heat sink over a surface of said integrated circuit chip.
2. The method of claim 1, further comprising providing said cavity in said circuit board.
3. The method of claim 2, wherein said providing said cavity comprises milling said surface of said circuit board to said embedded conductor.
4. The method of claim 3, wherein said providing of said cavity comprises providing said cavity with a side surface that includes a step.
5. The method of claim 4, wherein a top surface of said step is aligned with another embedded conductor.
6. The method of claim 4, wherein a top surface of said step exposes said embedded conductor.
7. The method of claim 4, wherein said electrically connecting comprises electrically connecting said integrated circuit chip to a plurality of embedded conductors in addition to said embedded conductor,
8. The method of claim 7, wherein said electrically connecting said integrated circuit chip to the plurality of embedded conductors comprises providing one of a ribbon bond, a wire bond, and a ball bond.
9. The method of claim 1, wherein said electrically connecting said integrated circuit chip to said embedded conductor comprises flip chip mounting said integrated circuit chip within said cavity.
10. The method of claim 1, wherein a top surface of said integrated circuit chip is located above a side surface of the integrated circuit chip.
11. The method of claim 10, further comprising:
disposing the heat sink on an outer surface of a thermal slug for transferring a thermal energy away from said circuit board.
12. The method of claim 11, wherein said circuit board is disposed on an upper surface and a lower surface of said embedded conductor.
13. The method of claim 1, wherein said circuit board is disposed on an upper surface and a lower surface of said embedded conductor.
14. The method of claim 1, wherein said integrated circuit chip abuts a bottom surface of a thermal slug.
15. The method of claim 14, wherein, with respect to a bottom surface of said integrated circuit chip, a top surface of the thermal slug is located higher than a top surface of said circuit board.
16. The method of claim 1, further comprising:
disposing a heat sink on a top surface of a thermal slug for transferring a thermal energy away from said circuit board, the heat sink extending above a top surface of said circuit board,
17. The method of claim 16, further comprising:
disposing a flip chip package between the top surface of said circuit board and a bottom surface of the heat sink.
18. The method of claim 16, wherein the bottom surface of the heat sink abuts a top surface of the flip chip package.
19. A method of mounting an integrated circuit chip to a circuit board, the method comprising:
providing a cavity in the circuit board;
placing the integrated circuit chip into the cavity, the cavity extending from the surface of the circuit board to a conductor embedded in the circuit board;
electrically connecting the integrated circuit chip to the conductor;
disposing a thermal slug on a surface of the integrated circuit chip; and
disposing a heat sink over a surface of said integrated circuit chip.
20. A method of mounting an integrated circuit chip to a circuit board, the method comprising:
milling a surface of a circuit board to provide a cavity in the circuit board;
placing the integrated circuit chip into the cavity, the cavity extending from the surface of the circuit board to a conductor embedded in the circuit board;
electrically connecting the integrated circuit chip to the conductor;
disposing a thermal slug on a surface of the integrated circuit chip; and
disposing a flip chip package on a top surface of the circuit board.
US16/774,573 2006-04-27 2020-01-28 Integrated circuit chip packaging Abandoned US20200168525A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/774,573 US20200168525A1 (en) 2006-04-27 2020-01-28 Integrated circuit chip packaging

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/411,920 US9713258B2 (en) 2006-04-27 2006-04-27 Integrated circuit chip packaging
US15/589,131 US10600715B2 (en) 2006-04-27 2017-05-08 Integrated circuit chip packaging
US16/774,573 US20200168525A1 (en) 2006-04-27 2020-01-28 Integrated circuit chip packaging

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US15/589,131 Continuation US10600715B2 (en) 2006-04-27 2017-05-08 Integrated circuit chip packaging

Publications (1)

Publication Number Publication Date
US20200168525A1 true US20200168525A1 (en) 2020-05-28

Family

ID=38686482

Family Applications (5)

Application Number Title Priority Date Filing Date
US11/411,920 Active 2030-07-05 US9713258B2 (en) 2006-04-27 2006-04-27 Integrated circuit chip packaging
US15/589,108 Expired - Fee Related US10818572B2 (en) 2006-04-27 2017-05-08 Integrated circuit chip packaging including a heat sink topped cavity
US15/589,131 Expired - Fee Related US10600715B2 (en) 2006-04-27 2017-05-08 Integrated circuit chip packaging
US16/774,524 Abandoned US20200168524A1 (en) 2006-04-27 2020-01-28 Integrated circuit chip packaging
US16/774,573 Abandoned US20200168525A1 (en) 2006-04-27 2020-01-28 Integrated circuit chip packaging

Family Applications Before (4)

Application Number Title Priority Date Filing Date
US11/411,920 Active 2030-07-05 US9713258B2 (en) 2006-04-27 2006-04-27 Integrated circuit chip packaging
US15/589,108 Expired - Fee Related US10818572B2 (en) 2006-04-27 2017-05-08 Integrated circuit chip packaging including a heat sink topped cavity
US15/589,131 Expired - Fee Related US10600715B2 (en) 2006-04-27 2017-05-08 Integrated circuit chip packaging
US16/774,524 Abandoned US20200168524A1 (en) 2006-04-27 2020-01-28 Integrated circuit chip packaging

Country Status (1)

Country Link
US (5) US9713258B2 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9713258B2 (en) 2006-04-27 2017-07-18 International Business Machines Corporation Integrated circuit chip packaging
US8296868B2 (en) * 2007-08-17 2012-10-30 Easton Sports, Inc. Adjustable hockey helmet
US8081045B1 (en) * 2008-08-08 2011-12-20 Lockheed Martin Corporation Beamformer power divider/combiner with transmission lines distributed between MMIC and associated PC board
JP2010152542A (en) * 2008-12-24 2010-07-08 Toshiba Corp Memory system
US20150136357A1 (en) * 2013-11-21 2015-05-21 Honeywell Federal Manufacturing & Technologies, Llc Heat dissipation assembly
MY199173A (en) * 2017-05-29 2023-10-18 Intel Corp Integrated circuit packages with conductive element having cavities housing electrically connected embedded components
US10398031B2 (en) 2017-09-29 2019-08-27 International Business Machines Corporation Integrating Josephson amplifiers or Josephson mixers into printed circuit boards
US11056452B2 (en) * 2017-10-26 2021-07-06 Intel Corporation Interface bus for inter-die communication in a multi-chip package over high density interconnects
US11676886B2 (en) * 2021-05-18 2023-06-13 Nanya Technology Corporation Integrated circuit package structure with conductive stair structure and method of manufacturing thereof

Citations (65)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4628411A (en) * 1984-03-12 1986-12-09 International Business Machines Corporation Apparatus for directly powering a multi-chip module from a power distribution bus
US5136471A (en) * 1987-02-26 1992-08-04 Nec Corporation Laminate wiring board
US5365402A (en) * 1990-11-30 1994-11-15 Hitachi, Ltd. Cooling apparatus of electronic device
US5455457A (en) * 1990-11-27 1995-10-03 Nec Corporation Package for semiconductor elements having thermal dissipation means
US5542175A (en) * 1994-12-20 1996-08-06 International Business Machines Corporation Method of laminating and circuitizing substrates having openings therein
US5583378A (en) * 1994-05-16 1996-12-10 Amkor Electronics, Inc. Ball grid array integrated circuit package with thermal conductor
US5610442A (en) * 1995-03-27 1997-03-11 Lsi Logic Corporation Semiconductor device package fabrication method and apparatus
US5625166A (en) * 1994-11-01 1997-04-29 Intel Corporation Structure of a thermally and electrically enhanced plastic pin grid array (PPGA) package for high performance devices with wire bond interconnect
US5646828A (en) * 1995-02-24 1997-07-08 Lucent Technologies Inc. Thin packaging of multi-chip modules with enhanced thermal/power management
US5672548A (en) * 1994-07-11 1997-09-30 International Business Machines Corporation Method for attaching heat sinks directly to chip carrier modules using flexible-epoxy
US5742477A (en) * 1995-07-06 1998-04-21 Nec Corporation Multi-chip module
US5796170A (en) * 1996-02-15 1998-08-18 Northern Telecom Limited Ball grid array (BGA) integrated circuit packages
US5805430A (en) * 1996-07-22 1998-09-08 International Business Machines Corporation Zero force heat sink
US5831810A (en) * 1996-08-21 1998-11-03 International Business Machines Corporation Electronic component package with decoupling capacitors completely within die receiving cavity of substrate
US5910686A (en) * 1998-07-23 1999-06-08 Vlsi Technology, Inc. Cavity down HBGA package structure
US5923540A (en) * 1993-11-30 1999-07-13 Fujitsu Limited Semiconductor unit having semiconductor device and multilayer substrate, in which grounding conductors surround conductors used for signal and power
US6043559A (en) * 1996-09-09 2000-03-28 Intel Corporation Integrated circuit package which contains two in plane voltage busses and a wrap around conductive strip that connects a bond finger to one of the busses
US6081027A (en) * 1998-05-21 2000-06-27 Micron Technology, Inc. Integrated heat sink
US6081028A (en) * 1994-03-29 2000-06-27 Sun Microsystems, Inc. Thermal management enhancements for cavity packages
US6153829A (en) * 1998-09-15 2000-11-28 Intel Corporation Split cavity wall plating for an integrated circuit package
US6184580B1 (en) * 1999-09-10 2001-02-06 Siliconware Precision Industries Co., Ltd. Ball grid array package with conductive leads
US6219238B1 (en) * 1999-05-10 2001-04-17 International Business Machines Corporation Structure for removably attaching a heat sink to surface mount packages
US6265769B1 (en) * 1997-11-13 2001-07-24 Texas Instruments Incorporated Double-sided chip mount package
US6268239B1 (en) * 1999-04-20 2001-07-31 Nec Corporation Semiconductor chip cooling structure and manufacturing method thereof
US6313521B1 (en) * 1998-11-04 2001-11-06 Nec Corporation Semiconductor device and method of manufacturing the same
US20010045644A1 (en) * 2000-01-13 2001-11-29 Chien-Ping Huang Semiconductor package having heat sink at the outer surface
US6359234B1 (en) * 1999-06-25 2002-03-19 Nec Corporation Package substrate for mounting semiconductor chip with low impedance and semiconductor device having the same
US20020050407A1 (en) * 1997-07-14 2002-05-02 Signetics Kp Co., Ltd. Ground via structures in semiconductor packages
US6413353B2 (en) * 1997-08-22 2002-07-02 International Business Machines Corporation Method for direct attachment of a chip to a cooling member
US20020096767A1 (en) * 2001-01-25 2002-07-25 Cote Kevin J. Cavity down ball grid array package with EMI shielding and reduced thermal resistance
US20020109226A1 (en) * 2001-02-15 2002-08-15 Broadcom Corporation Enhanced die-down ball grid array and method for making the same
US20020163064A1 (en) * 2001-05-07 2002-11-07 St Assembly Test Services Pte Ltd Enhanced BGA grounded heatsink
US6487083B1 (en) * 2000-08-10 2002-11-26 Nortel Networks Ltd. Multilayer circuit board
US6509642B1 (en) * 2000-07-28 2003-01-21 Agere Systems Inc. Integrated circuit package
US20030025199A1 (en) * 2001-08-01 2003-02-06 Chi-Chuan Wu Super low profile package with stacked dies
US6535388B1 (en) * 2001-10-04 2003-03-18 Intel Corporation Wirebonded microelectronic packages including heat dissipation devices for heat removal from active surfaces thereof
US20030148554A1 (en) * 2002-02-07 2003-08-07 Gerber Mark A. Packaged semiconductor device and method of formation
US20030150641A1 (en) * 2002-02-14 2003-08-14 Noyan Kinayman Multilayer package for a semiconductor device
US20040084764A1 (en) * 2002-09-16 2004-05-06 Junichi Ishimine Package structure, printed circuit board mounted with the same, electronic apparatus having the printed circuit board
US20040150097A1 (en) * 2003-01-30 2004-08-05 International Business Machines Corporation Optimized conductive lid mounting for integrated circuit chip carriers
US20040173901A1 (en) * 2003-03-05 2004-09-09 Intel Corporation Thermally enhanced electronic flip-chip packaging with external-connector side die and method
US20040212961A1 (en) * 2003-04-28 2004-10-28 Harris Shaun L. Stack up assembly
US6867492B2 (en) * 2002-01-17 2005-03-15 Infineon Technologies Ag Radio-frequency power component, radio-frequency power module, method for producing a radio-frequency power component, and method for producing a radio-frequency power module
US6873529B2 (en) * 2002-02-26 2005-03-29 Kyocera Corporation High frequency module
US20050112796A1 (en) * 2003-11-24 2005-05-26 Ararao Virgil C. Semiconductor package heat spreaders and fabrication methods therefor
US20050285260A1 (en) * 2004-06-25 2005-12-29 Dale Hackitt Bottom heat spreader
US20060043576A1 (en) * 2004-08-25 2006-03-02 Hsin-Hui Lee Structures and methods for heat dissipation of semiconductor integrated circuits
US20060081978A1 (en) * 2004-10-20 2006-04-20 Siliconware Precision Industries Co., Ltd. Heat dissipating package structure and method for fabricating the same
US20060113105A1 (en) * 2003-08-28 2006-06-01 Fujitsu Limited Package unit, printed board having the same, and electronic apparatus having the printed board
US20060120058A1 (en) * 2004-12-03 2006-06-08 Delphi Technologies, Inc. Thermal management of surface-mount circuit devices
US20060137902A1 (en) * 2004-12-27 2006-06-29 Fujitsu Limited Semiconductor device and manufacturing method therefor
US20070013051A1 (en) * 2003-08-07 2007-01-18 Johann Heyan Multichip circuit module and method for the production thereof
US20080017998A1 (en) * 2006-07-19 2008-01-24 Pavio Jeanne S Semiconductor component and method of manufacture
US20080237840A1 (en) * 2007-03-26 2008-10-02 Endicott Interconnect Technologies, Inc. Flexible circuit electronic package with standoffs
US7566591B2 (en) * 2005-08-22 2009-07-28 Broadcom Corporation Method and system for secure heat sink attachment on semiconductor devices with macroscopic uneven surface features
US7608915B2 (en) * 2007-05-11 2009-10-27 Siliconware Precision Industries Co., Ltd. Heat dissipation semiconductor package
US20100001906A1 (en) * 2008-07-07 2010-01-07 Akkermans Johannes A G Radio frequency (rf) integrated circuit (ic) packages having characteristics suitable for mass production
US20100218985A1 (en) * 2009-02-27 2010-09-02 Denso Corporation Integrated circuit mounted board, printed wiring board, and method of manufacturing integrated circuit mounted board
US20100226110A1 (en) * 2009-03-09 2010-09-09 Denso Corporation Printed wiring board, printed IC board having the printed wiring board, and method of manufacturing the same
US7983048B2 (en) * 2007-02-15 2011-07-19 Nec Corporation Structure for mounting semiconductor package
US8049313B2 (en) * 2006-09-20 2011-11-01 Freescale Semiconductor, Inc. Heat spreader for semiconductor package
US20130180762A1 (en) * 2012-01-18 2013-07-18 Tyco Healthcare Group Lp Printed Circuit Boards Including Strip-Line Circuitry and Methods of Manufacturing Same
US9763317B2 (en) * 2013-03-14 2017-09-12 Cisco Technology, Inc. Method and apparatus for providing a ground and a heat transfer interface on a printed circuit board
US20180061725A1 (en) * 2016-08-31 2018-03-01 Qorvo Us, Inc. Air-cavity package with enhanced package integration level and thermal performance
US11160160B1 (en) * 2020-08-06 2021-10-26 Multek Technologies Limited PCB for bare die mount and process therefore

Family Cites Families (91)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4866571A (en) * 1982-06-21 1989-09-12 Olin Corporation Semiconductor package
US5272500A (en) * 1983-05-27 1993-12-21 Minolta Camera Kabushiki Kaisha Flash photographing system
US4715115A (en) 1986-04-03 1987-12-29 Hewlett-Packard Company Package for water-scale semiconductor devices
US4922324A (en) * 1987-01-20 1990-05-01 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device
US4855868A (en) 1987-01-20 1989-08-08 Harding Ade Yemi S K Preformed packaging arrangement for energy dissipating devices
US5008734A (en) * 1989-12-20 1991-04-16 National Semiconductor Corporation Stadium-stepped package for an integrated circuit with air dielectric
US5272590A (en) * 1990-02-12 1993-12-21 Hernandez Jorge M Integrated circuit package having an internal cavity for incorporating decoupling capacitor
JP2978533B2 (en) * 1990-06-15 1999-11-15 株式会社日立製作所 Semiconductor integrated circuit device
US5235211A (en) * 1990-06-22 1993-08-10 Digital Equipment Corporation Semiconductor package having wraparound metallization
US5175613A (en) * 1991-01-18 1992-12-29 Digital Equipment Corporation Package for EMI, ESD, thermal, and mechanical shock protection of circuit chips
JP2606631B2 (en) * 1991-02-01 1997-05-07 日本電気株式会社 Master slice type semiconductor integrated circuit device
JP3009788B2 (en) * 1991-11-15 2000-02-14 日本特殊陶業株式会社 Package for integrated circuit
US5280409A (en) 1992-10-09 1994-01-18 Sun Microsystems, Inc. Heat sink and cover for tab integrated circuits
JPH06296084A (en) * 1993-02-12 1994-10-21 Ngk Spark Plug Co Ltd Thermal conductor of high conductivity, wiring board provided therewith and manufacture thereof
US5490324A (en) * 1993-09-15 1996-02-13 Lsi Logic Corporation Method of making integrated circuit package having multiple bonding tiers
US5641988A (en) * 1993-12-22 1997-06-24 Vlsi Technology, Inc. Multi-layered, integrated circuit package having reduced parasitic noise characteristics
US5468999A (en) * 1994-05-26 1995-11-21 Motorola, Inc. Liquid encapsulated ball grid array semiconductor device with fine pitch wire bonding
US5478420A (en) 1994-07-28 1995-12-26 International Business Machines Corporation Process for forming open-centered multilayer ceramic substrates
US5508556A (en) * 1994-09-02 1996-04-16 Motorola, Inc. Leaded semiconductor device having accessible power supply pad terminals
US5886408A (en) * 1994-09-08 1999-03-23 Fujitsu Limited Multi-chip semiconductor device
US5701233A (en) * 1995-01-23 1997-12-23 Irvine Sensors Corporation Stackable modules and multimodular assemblies
US5597643A (en) * 1995-03-13 1997-01-28 Hestia Technologies, Inc. Multi-tier laminate substrate with internal heat spreader
JP3004578B2 (en) * 1995-05-12 2000-01-31 財団法人工業技術研究院 Integrated Circuit Package Consisting of Multi-Heat Conductors for Enhanced Heat Dissipation and Caps Around the Edge for Improved Package Integrity and Reliability
JP2701802B2 (en) * 1995-07-17 1998-01-21 日本電気株式会社 Printed circuit board for bare chip mounting
JP3292798B2 (en) * 1995-10-04 2002-06-17 三菱電機株式会社 Semiconductor device
US5696666A (en) * 1995-10-11 1997-12-09 Motorola, Inc. Low profile exposed die chip carrier package
US6008988A (en) * 1995-12-20 1999-12-28 Intel Corporation Integrated circuit package with a heat spreader coupled to a pair of electrical devices
US5689091A (en) * 1996-09-19 1997-11-18 Vlsi Technology, Inc. Multi-layer substrate structure
US6090237A (en) * 1996-12-03 2000-07-18 Reynolds; Carl V. Apparatus for restraining adhesive overflow in a multilayer substrate assembly during lamination
US5847935A (en) * 1996-12-16 1998-12-08 Sarnoff Corporation Electronic circuit chip package
US6054758A (en) * 1996-12-18 2000-04-25 Texas Instruments Incorporated Differential pair geometry for integrated circuit chip packages
EP0995235B1 (en) * 1997-07-16 2002-04-03 Fraunhofer-Gesellschaft Zur Förderung Der Angewandten Forschung E.V. Contact for very small liaison contacts and method for producing a contact
JP3051700B2 (en) * 1997-07-28 2000-06-12 京セラ株式会社 Method of manufacturing multilayer wiring board with built-in element
JP3147053B2 (en) * 1997-10-27 2001-03-19 日本電気株式会社 Resin-sealed ball grid array IC package and method of manufacturing the same
US6114986A (en) 1998-03-04 2000-09-05 Northrop Grumman Corporation Dual channel microwave transmit/receive module for an active aperture of a radar system
US5986884A (en) * 1998-07-13 1999-11-16 Ford Motor Company Method for cooling electronic components
US6117797A (en) * 1998-09-03 2000-09-12 Micron Technology, Inc. Attachment method for heat sinks and devices involving removal of misplaced encapsulant
TW399309B (en) * 1998-09-30 2000-07-21 World Wiser Electronics Inc Cavity-down package structure with thermal via
KR100298897B1 (en) * 1998-12-23 2001-09-22 이형도 Method for manufacturing pcb
TW410446B (en) * 1999-01-21 2000-11-01 Siliconware Precision Industries Co Ltd BGA semiconductor package
US6075700A (en) 1999-02-02 2000-06-13 Compaq Computer Corporation Method and system for controlling radio frequency radiation in microelectronic packages using heat dissipation structures
TW411595B (en) 1999-03-20 2000-11-11 Siliconware Precision Industries Co Ltd Heat structure for semiconductor package device
US6890798B2 (en) * 1999-06-08 2005-05-10 Intel Corporation Stacked chip packaging
SE514426C2 (en) * 1999-06-17 2001-02-19 Ericsson Telefon Ab L M Device for chip mounting in cavity in multilayer PCBs
US6294966B1 (en) * 1999-12-31 2001-09-25 Hei, Inc. Interconnection device
US7026710B2 (en) * 2000-01-21 2006-04-11 Texas Instruments Incorporated Molded package for micromechanical devices and method of fabrication
JP3976473B2 (en) * 2000-05-09 2007-09-19 日本電気株式会社 High frequency circuit and module and communication device using the same
US6577504B1 (en) * 2000-08-30 2003-06-10 Intel Corporation Integrated heat sink for different size components with EMI suppression features
US6906414B2 (en) * 2000-12-22 2005-06-14 Broadcom Corporation Ball grid array package with patterned stiffener layer
KR100391093B1 (en) * 2001-01-04 2003-07-12 삼성전자주식회사 Ball Grid Array package mounting heat sink
US6469897B2 (en) * 2001-01-30 2002-10-22 Siliconware Precision Industries Co., Ltd. Cavity-down tape ball grid array package assembly with grounded heat sink and method of fabricating the same
US6475327B2 (en) * 2001-04-05 2002-11-05 Phoenix Precision Technology Corporation Attachment of a stiff heat spreader for fabricating a cavity down plastic chip carrier
US6570271B2 (en) * 2001-05-16 2003-05-27 Hewlett-Packard Development Company, L.P. Apparatus for routing signals
TW560018B (en) * 2001-10-30 2003-11-01 Asia Pacific Microsystems Inc A wafer level packaged structure and method for manufacturing the same
US7030482B2 (en) 2001-12-21 2006-04-18 Intel Corporation Method and apparatus for protecting a die ESD events
US6744640B2 (en) 2002-04-10 2004-06-01 Gore Enterprise Holdings, Inc. Board-level EMI shield with enhanced thermal dissipation
US6979594B1 (en) 2002-07-19 2005-12-27 Asat Ltd. Process for manufacturing ball grid array package
US6710442B1 (en) 2002-08-27 2004-03-23 Micron Technology, Inc. Microelectronic devices with improved heat dissipation and methods for cooling microelectronic devices
DE10245930A1 (en) * 2002-09-30 2004-04-08 Osram Opto Semiconductors Gmbh Optoelectronic component and component module
JP2004214258A (en) * 2002-12-27 2004-07-29 Renesas Technology Corp Semiconductor module
JP4401096B2 (en) * 2003-03-26 2010-01-20 Ｄｏｗａホールディングス株式会社 Circuit board manufacturing method
US7116557B1 (en) * 2003-05-23 2006-10-03 Sti Electronics, Inc. Imbedded component integrated circuit assembly and method of making same
JP2005026263A (en) * 2003-06-30 2005-01-27 Nec Compound Semiconductor Devices Ltd Hybrid integrated circuit
US7031162B2 (en) 2003-09-26 2006-04-18 International Business Machines Corporation Method and structure for cooling a dual chip module with one high power chip
JP4131694B2 (en) * 2003-10-06 2008-08-13 三洋電機株式会社 Multilayer ceramic substrate and manufacturing method thereof
TW200514484A (en) 2003-10-08 2005-04-16 Chung-Cheng Wang Substrate for electrical device and methods of fabricating the same
US6982481B1 (en) 2003-10-08 2006-01-03 Nortel Networks Limited System for dissipating heat and shielding electromagnetic radiation produced by an electronic device
WO2005050708A2 (en) 2003-11-13 2005-06-02 Silicon Pipe, Inc. Stair step printed circuit board structures for high speed signal transmissions
TWM250504U (en) * 2003-11-27 2004-11-11 Optimum Care Int Tech Inc Assembly structure for hiding electronic component
TW200404706A (en) 2003-12-05 2004-04-01 Chung Shan Inst Of Science Composite material structure for rotary-wings and its producing method
US7164587B1 (en) 2004-01-14 2007-01-16 Sun Microsystems, Inc. Integral heatsink grounding arrangement
US6933443B2 (en) * 2004-01-28 2005-08-23 Infineon Technologies North America Corp. Method for bonding ceramic to copper, without creating a bow in the copper
TWI247371B (en) * 2004-02-06 2006-01-11 Advanced Semiconductor Eng Semiconductor package and method for manufacturing the same
JP2006032490A (en) * 2004-07-13 2006-02-02 Hitachi Ltd Engine control circuit device
US20060097370A1 (en) * 2004-10-21 2006-05-11 International Business Machines Corporation Stepped integrated circuit packaging and mounting
US7254034B2 (en) * 2004-12-15 2007-08-07 Lucent Technologies Inc. Thermal management for shielded circuit packs
JPWO2006095852A1 (en) * 2005-03-10 2008-08-21 京セラ株式会社 Electronic component module and manufacturing method thereof
KR20060106891A (en) * 2005-04-04 2006-10-12 마츠시타 덴끼 산교 가부시키가이샤 Method for manufacturing cavity structure for optical device, cavity structure for optical device and optical device
US8335084B2 (en) * 2005-08-01 2012-12-18 Georgia Tech Research Corporation Embedded actives and discrete passives in a cavity within build-up layers
US7550319B2 (en) * 2005-09-01 2009-06-23 E. I. Du Pont De Nemours And Company Low temperature co-fired ceramic (LTCC) tape compositions, light emitting diode (LED) modules, lighting devices and method of forming thereof
US7339278B2 (en) * 2005-09-29 2008-03-04 United Test And Assembly Center Ltd. Cavity chip package
US20070195505A1 (en) 2006-02-21 2007-08-23 Dominique Savignac Memory module device
US7977579B2 (en) * 2006-03-30 2011-07-12 Stats Chippac Ltd. Multiple flip-chip integrated circuit package system
US9713258B2 (en) * 2006-04-27 2017-07-18 International Business Machines Corporation Integrated circuit chip packaging
JP5013973B2 (en) * 2007-05-31 2012-08-29 株式会社メイコー Printed wiring board and method for manufacturing the same, electronic component housing board using the printed wiring board, and method for manufacturing the same
US7529095B2 (en) 2007-09-28 2009-05-05 Visteon Global Technologies, Inc. Integrated electrical shield in a heat sink
US8290008B2 (en) * 2009-08-20 2012-10-16 International Business Machines Corporation Silicon carrier optoelectronic packaging
US8411444B2 (en) * 2010-09-15 2013-04-02 International Business Machines Corporation Thermal interface material application for integrated circuit cooling
US9153863B2 (en) * 2012-01-24 2015-10-06 E I Du Pont De Nemours And Company Low temperature co-fired ceramic (LTCC) system in a package (SiP) configurations for microwave/millimeter wave packaging applications
US9842813B2 (en) * 2015-09-21 2017-12-12 Altera Corporation Tranmission line bridge interconnects
WO2018063414A1 (en) * 2016-10-01 2018-04-05 Intel Corporation Module installation on printed circuit boards with embedded trace technology

Patent Citations (75)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4628411A (en) * 1984-03-12 1986-12-09 International Business Machines Corporation Apparatus for directly powering a multi-chip module from a power distribution bus
US5136471A (en) * 1987-02-26 1992-08-04 Nec Corporation Laminate wiring board
US5455457A (en) * 1990-11-27 1995-10-03 Nec Corporation Package for semiconductor elements having thermal dissipation means
US5365402A (en) * 1990-11-30 1994-11-15 Hitachi, Ltd. Cooling apparatus of electronic device
US5923540A (en) * 1993-11-30 1999-07-13 Fujitsu Limited Semiconductor unit having semiconductor device and multilayer substrate, in which grounding conductors surround conductors used for signal and power
US6081028A (en) * 1994-03-29 2000-06-27 Sun Microsystems, Inc. Thermal management enhancements for cavity packages
US5583378A (en) * 1994-05-16 1996-12-10 Amkor Electronics, Inc. Ball grid array integrated circuit package with thermal conductor
US5672548A (en) * 1994-07-11 1997-09-30 International Business Machines Corporation Method for attaching heat sinks directly to chip carrier modules using flexible-epoxy
US5625166A (en) * 1994-11-01 1997-04-29 Intel Corporation Structure of a thermally and electrically enhanced plastic pin grid array (PPGA) package for high performance devices with wire bond interconnect
US5578796A (en) * 1994-12-20 1996-11-26 International Business Machines Corporation Apparatus for laminating and circuitizing substrates having openings therein
US5542175A (en) * 1994-12-20 1996-08-06 International Business Machines Corporation Method of laminating and circuitizing substrates having openings therein
US5646828A (en) * 1995-02-24 1997-07-08 Lucent Technologies Inc. Thin packaging of multi-chip modules with enhanced thermal/power management
US5610442A (en) * 1995-03-27 1997-03-11 Lsi Logic Corporation Semiconductor device package fabrication method and apparatus
US5742477A (en) * 1995-07-06 1998-04-21 Nec Corporation Multi-chip module
US5796170A (en) * 1996-02-15 1998-08-18 Northern Telecom Limited Ball grid array (BGA) integrated circuit packages
US5805430A (en) * 1996-07-22 1998-09-08 International Business Machines Corporation Zero force heat sink
US5831810A (en) * 1996-08-21 1998-11-03 International Business Machines Corporation Electronic component package with decoupling capacitors completely within die receiving cavity of substrate
US6043559A (en) * 1996-09-09 2000-03-28 Intel Corporation Integrated circuit package which contains two in plane voltage busses and a wrap around conductive strip that connects a bond finger to one of the busses
US6440770B1 (en) * 1996-09-09 2002-08-27 Intel Corporation Integrated circuit package
US20020050407A1 (en) * 1997-07-14 2002-05-02 Signetics Kp Co., Ltd. Ground via structures in semiconductor packages
US6413353B2 (en) * 1997-08-22 2002-07-02 International Business Machines Corporation Method for direct attachment of a chip to a cooling member
US6265769B1 (en) * 1997-11-13 2001-07-24 Texas Instruments Incorporated Double-sided chip mount package
US6081027A (en) * 1998-05-21 2000-06-27 Micron Technology, Inc. Integrated heat sink
US5910686A (en) * 1998-07-23 1999-06-08 Vlsi Technology, Inc. Cavity down HBGA package structure
US6153829A (en) * 1998-09-15 2000-11-28 Intel Corporation Split cavity wall plating for an integrated circuit package
US6313521B1 (en) * 1998-11-04 2001-11-06 Nec Corporation Semiconductor device and method of manufacturing the same
US6268239B1 (en) * 1999-04-20 2001-07-31 Nec Corporation Semiconductor chip cooling structure and manufacturing method thereof
US6219238B1 (en) * 1999-05-10 2001-04-17 International Business Machines Corporation Structure for removably attaching a heat sink to surface mount packages
US6359234B1 (en) * 1999-06-25 2002-03-19 Nec Corporation Package substrate for mounting semiconductor chip with low impedance and semiconductor device having the same
US6184580B1 (en) * 1999-09-10 2001-02-06 Siliconware Precision Industries Co., Ltd. Ball grid array package with conductive leads
US6559525B2 (en) * 2000-01-13 2003-05-06 Siliconware Precision Industries Co., Ltd. Semiconductor package having heat sink at the outer surface
US20010045644A1 (en) * 2000-01-13 2001-11-29 Chien-Ping Huang Semiconductor package having heat sink at the outer surface
US6509642B1 (en) * 2000-07-28 2003-01-21 Agere Systems Inc. Integrated circuit package
US6487083B1 (en) * 2000-08-10 2002-11-26 Nortel Networks Ltd. Multilayer circuit board
US20020096767A1 (en) * 2001-01-25 2002-07-25 Cote Kevin J. Cavity down ball grid array package with EMI shielding and reduced thermal resistance
US20020109226A1 (en) * 2001-02-15 2002-08-15 Broadcom Corporation Enhanced die-down ball grid array and method for making the same
US6853070B2 (en) * 2001-02-15 2005-02-08 Broadcom Corporation Die-down ball grid array package with die-attached heat spreader and method for making the same
US20050012203A1 (en) * 2001-02-15 2005-01-20 Rahman Khan Reza-Ur Enhanced die-down ball grid array and method for making the same
US20020163064A1 (en) * 2001-05-07 2002-11-07 St Assembly Test Services Pte Ltd Enhanced BGA grounded heatsink
US20030025199A1 (en) * 2001-08-01 2003-02-06 Chi-Chuan Wu Super low profile package with stacked dies
US20030067750A1 (en) * 2001-10-04 2003-04-10 Garcia Jason A. Wirebonded microelectronic packages including heat dissipation devices for heat removal from active surfaces thereof
US6535388B1 (en) * 2001-10-04 2003-03-18 Intel Corporation Wirebonded microelectronic packages including heat dissipation devices for heat removal from active surfaces thereof
US6867492B2 (en) * 2002-01-17 2005-03-15 Infineon Technologies Ag Radio-frequency power component, radio-frequency power module, method for producing a radio-frequency power component, and method for producing a radio-frequency power module
US20030148554A1 (en) * 2002-02-07 2003-08-07 Gerber Mark A. Packaged semiconductor device and method of formation
US20030150641A1 (en) * 2002-02-14 2003-08-14 Noyan Kinayman Multilayer package for a semiconductor device
US6873529B2 (en) * 2002-02-26 2005-03-29 Kyocera Corporation High frequency module
US20040084764A1 (en) * 2002-09-16 2004-05-06 Junichi Ishimine Package structure, printed circuit board mounted with the same, electronic apparatus having the printed circuit board
US7428154B2 (en) * 2002-09-18 2008-09-23 Fujitsu Limited Package structure, printed circuit board mounted with the same, electronic apparatus having the printed circuit board
US20040150097A1 (en) * 2003-01-30 2004-08-05 International Business Machines Corporation Optimized conductive lid mounting for integrated circuit chip carriers
US20040173901A1 (en) * 2003-03-05 2004-09-09 Intel Corporation Thermally enhanced electronic flip-chip packaging with external-connector side die and method
US7456047B2 (en) * 2003-03-05 2008-11-25 Intel Corporation Thermally enhanced electronic flip-chip packaging with external-connector-side die and method
US20040212961A1 (en) * 2003-04-28 2004-10-28 Harris Shaun L. Stack up assembly
US20050152117A1 (en) * 2003-04-28 2005-07-14 Belady Christian L. Stack up assembly
US6947286B2 (en) * 2003-04-28 2005-09-20 Hewlett-Packard Development Company, L.P. Stack up assembly
US20070013051A1 (en) * 2003-08-07 2007-01-18 Johann Heyan Multichip circuit module and method for the production thereof
US20060113105A1 (en) * 2003-08-28 2006-06-01 Fujitsu Limited Package unit, printed board having the same, and electronic apparatus having the printed board
US20050112796A1 (en) * 2003-11-24 2005-05-26 Ararao Virgil C. Semiconductor package heat spreaders and fabrication methods therefor
US20050285260A1 (en) * 2004-06-25 2005-12-29 Dale Hackitt Bottom heat spreader
US20060043576A1 (en) * 2004-08-25 2006-03-02 Hsin-Hui Lee Structures and methods for heat dissipation of semiconductor integrated circuits
US20060081978A1 (en) * 2004-10-20 2006-04-20 Siliconware Precision Industries Co., Ltd. Heat dissipating package structure and method for fabricating the same
US20060120058A1 (en) * 2004-12-03 2006-06-08 Delphi Technologies, Inc. Thermal management of surface-mount circuit devices
US20060137902A1 (en) * 2004-12-27 2006-06-29 Fujitsu Limited Semiconductor device and manufacturing method therefor
US7566591B2 (en) * 2005-08-22 2009-07-28 Broadcom Corporation Method and system for secure heat sink attachment on semiconductor devices with macroscopic uneven surface features
US20080017998A1 (en) * 2006-07-19 2008-01-24 Pavio Jeanne S Semiconductor component and method of manufacture
US8049313B2 (en) * 2006-09-20 2011-11-01 Freescale Semiconductor, Inc. Heat spreader for semiconductor package
US7983048B2 (en) * 2007-02-15 2011-07-19 Nec Corporation Structure for mounting semiconductor package
US20080237840A1 (en) * 2007-03-26 2008-10-02 Endicott Interconnect Technologies, Inc. Flexible circuit electronic package with standoffs
US7608915B2 (en) * 2007-05-11 2009-10-27 Siliconware Precision Industries Co., Ltd. Heat dissipation semiconductor package
US20100001906A1 (en) * 2008-07-07 2010-01-07 Akkermans Johannes A G Radio frequency (rf) integrated circuit (ic) packages having characteristics suitable for mass production
US20100218985A1 (en) * 2009-02-27 2010-09-02 Denso Corporation Integrated circuit mounted board, printed wiring board, and method of manufacturing integrated circuit mounted board
US20100226110A1 (en) * 2009-03-09 2010-09-09 Denso Corporation Printed wiring board, printed IC board having the printed wiring board, and method of manufacturing the same
US20130180762A1 (en) * 2012-01-18 2013-07-18 Tyco Healthcare Group Lp Printed Circuit Boards Including Strip-Line Circuitry and Methods of Manufacturing Same
US9763317B2 (en) * 2013-03-14 2017-09-12 Cisco Technology, Inc. Method and apparatus for providing a ground and a heat transfer interface on a printed circuit board
US20180061725A1 (en) * 2016-08-31 2018-03-01 Qorvo Us, Inc. Air-cavity package with enhanced package integration level and thermal performance
US11160160B1 (en) * 2020-08-06 2021-10-26 Multek Technologies Limited PCB for bare die mount and process therefore

Also Published As

Publication number Publication date
US10600715B2 (en) 2020-03-24
US10818572B2 (en) 2020-10-27
US20170243816A1 (en) 2017-08-24
US20170243802A1 (en) 2017-08-24
US20070266281A1 (en) 2007-11-15
US9713258B2 (en) 2017-07-18
US20200168524A1 (en) 2020-05-28

Similar Documents

Publication Publication Date Title
US20200168525A1 (en) Integrated circuit chip packaging
KR100733103B1 (en) Embedded rf vertical interconnect for flexible conformal antenna
EP0600638B1 (en) Method and apparatus for the interconnection of radio frequency (RF) monolithic microwave integrated circuits
CA1240371A (en) Coplanar microstrap waveguide
US9414497B2 (en) Semiconductor package including an embedded circuit component within a support structure of the package
US20190378801A1 (en) RF Functionality and Electromagnetic Radiation Shielding in a Component Carrier
US20030151133A1 (en) RF transition for an area array package
US6911733B2 (en) Semiconductor device and electronic device
EP3547363B1 (en) Electronic assembly and electronic system with impedance matched interconnect structures
CN114639943A (en) Integrated circuit package with integrated waveguide emitter
KR20010099684A (en) Tape ball grid array with interconnected ground plane
KR20050065038A (en) Printed circuit board and package having oblique via
US11690173B2 (en) Circuit board structure
US5852391A (en) Microwave/millimeter-wave functional module package
JP2021141370A (en) Semiconductor package
EP3425667B1 (en) Manufacturing a semiconductor package including an embedded circuit component within a support structure of the package and corresponding device
US6998292B2 (en) Apparatus and method for inter-chip or chip-to-substrate connection with a sub-carrier
EP3570646B1 (en) Structure for circuit interconnects
JP2784523B2 (en) Substrate for mounting electronic components
JP2784525B2 (en) Substrate for mounting electronic components
US12300621B2 (en) Hybrid integrated circuit package
JPH11163217A (en) Semiconductor device
EP4312470A1 (en) Component carrier with signal conductive element and shielding conductive structure
US20120211487A1 (en) Microwave unit and method therefore
JP4349891B2 (en) Wiring board and electronic device

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KWARK, YOUNG HOON;REEL/FRAME:051747/0518

Effective date: 20170413

STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: FINAL REJECTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE AFTER FINAL ACTION FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: ADVISORY ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: FINAL REJECTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE AFTER FINAL ACTION FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: ADVISORY ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: FINAL REJECTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE AFTER FINAL ACTION FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: ADVISORY ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: FINAL REJECTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE AFTER FINAL ACTION FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: ADVISORY ACTION MAILED

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION