US20200413048A1

US20200413048A1 - Interaction between ibc and dmvr

Info

Publication number: US20200413048A1
Application number: US17/019,629
Authority: US
Inventors: Kai Zhang; Li Zhang; Hongbin Liu; Yue Wang
Original assignee: Beijing ByteDance Network Technology Co Ltd; ByteDance Inc
Current assignee: Beijing ByteDance Network Technology Co Ltd; ByteDance Inc
Priority date: 2018-06-05
Filing date: 2020-09-14
Publication date: 2020-12-31
Also published as: TWI750477B; TWI708503B; GB202018254D0; WO2019234598A1; CN115529458B; US20210006780A1; CN110572671A; US11973962B2; TWI704802B; US11509915B2; US20240121410A1; US20220217363A1; CN110572670B; CN110572658A; TWI715993B; EP3788787A1; US12407835B2; TW202005394A; WO2019234638A1; GB202018255D0

Abstract

Devices, systems and methods for applying intra-block copy (IBC) in video coding are described. In general, methods for integrating IBC with existing motion compensation algorithms for video encoding and decoding are described. In a representative aspect, a method for video encoding using IBC includes determining whether a current block of the current picture is to be encoded using a motion compensation algorithm, and encoding, based on the determining, the current block by selectively applying an intra-block copy to the current block. In a representative aspect, another method for video encoding using IBC includes determining whether a current block of the current picture is to be encoded using an intra-block copy, and encoding, based on the determining, the current block by selectively applying a motion compensation algorithm to the current block.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of International Application No. PCT/IB2019/054650, filed on Jun. 5, 2019, which claims the priority to and benefits of International Patent Application No. PCT/CN2018/089920, filed on Jun. 5, 2018. All the aforementioned patent applications are hereby incorporated by reference in their entireties.

TECHNICAL FIELD

This patent document is directed generally to video coding technologies.

BACKGROUND

Motion compensation is a technique in video processing to predict a frame in a video, given the previous and/or future frames by accounting for motion of the camera and/or objects in the video. Motion compensation can be used in the encoding and decoding of video data for video compression.

SUMMARY

Devices, systems and methods related to intra-block copy for motion compensation are described.
In one representative aspect, the disclosed technology may be used to provide a method for video encoding using intra-block copy. This method includes determining whether a current block of the current picture is to be encoded using a motion compensation algorithm, and encoding, based on the determining, the current block by selectively applying an intra-block copy to the current block.
In another representative aspect, the disclosed technology may be used to provide another method for video encoding using intra-block copy. This method includes determining whether a current block of the current picture is to be encoded using an intra-block copy, and encoding, based on the determining, the current block by selectively applying a motion compensation algorithm to the current block.
In yet another representative aspect, the disclosed technology may be used to provide a method for video decoding using intra-block copy. This method includes determining whether a current block of the current picture is to be decoded using a motion compensation algorithm, and decoding, based on the determining, the current block by selectively applying an intra-block copy to the current block.
In yet another representative aspect, the disclosed technology may be used to provide another method for video decoding using intra-block copy. This method includes determining whether a current block of the current picture is to be decoded using an intra-block copy, and decoding, based on the determining, the current block by selectively applying a motion compensation algorithm to the current block.
In another example aspect, a method of video processing is disclosed. The method includes determining, from a coded representation, that a block being decoded representing a portion of the visual information is coded using a first coding technique; and decoding the coded representation by using a first decoding technique corresponding to the first coding technique and by excluding use of a second decoding technique corresponding to the second coding technique; wherein one of the two techniques corresponds to a coding technique that uses a same video picture for coding the block being decoded as a reference picture and the other of the two coding techniques corresponds to a Frame-Rate Up Conversion (FRUC) technique that uses reference pictures associated with the visual information to refine a motion information for coding the block being decoded.
In another example aspect, a method of video processing is disclosed. The method includes determining, from a coded representation, that a block being decoded representing a portion of the visual information is coded using a first coding technique; and decoding the coded representation by using a first decoding technique corresponding to the first coding technique and by excluding use of a second decoding technique corresponding to the second coding technique; wherein one of two techniques corresponds to a coding technique that uses a same video picture for coding the block being decoded as a reference picture and the other of the two coding techniques corresponds to a Decoder-side Motion Vector Refinement (DMVR) technique that uses a first reference block of a first reference picture associated with the visual information and a second reference block of a second reference picture associated with visual information to derive a motion information for coding the block being decoded.
In another example aspect, a method of video processing is disclosed. The method includes encoding a block being encoded of a picture of the visual information by using a first encoding technique and by excluding use of a second encoding technique; and wherein one of the two techniques corresponds to an encoding technique that uses a same video picture for coding the block being encoded as a reference picture and the other of the two coding techniques corresponds to a Frame-Rate Up Conversion (FRUC) technique that uses reference pictures associated with the visual information to refine a motion information for encoding the block being encoded.
In another example aspect, a method of video processing is disclosed. The method includes encoding a block being encoded of a picture of the visual information by using a first encoding technique and by excluding use of a second encoding technique; and wherein one of two techniques corresponds to an encoding technique that uses a same video picture for coding the block being encoded as a reference picture and the other of the two coding techniques corresponds to a Decoder-side Motion Vector Refinement (DMVR) technique that uses a first reference block of a first reference picture associated with the visual information and a second reference block of a second reference picture associated with visual information to derive a motion information for coding the block being encoded.
In yet another representative aspect, the above-described method is embodied in the form of processor-executable code and stored in a computer-readable program medium.
In yet another representative aspect, a device that is configured or operable to perform the above-described method is disclosed. The device may include a processor that is programmed to implement this method.
In yet another representative aspect, a video decoder apparatus may implement a method as described herein.
The above and other aspects and features of the disclosed technology are described in greater detail in the drawings, the description and the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows an example of an intra-block copy technique.

FIG. 2 shows an example of bilateral matching in the frame-rate up conversion (FRUC) algorithm.

FIG. 3 shows an example of template matching in the FRUC algorithm.

FIG. 4 shows an example of unilateral motion estimation in the FRUC algorithm.

FIG. 5 shows an example of the decoder-side motion vector refinement (DMVR) algorithm based on bilateral template matching.

FIG. 6 shows a flowchart of an example method for video encoding using intra-block copy in accordance with the disclosed technology.

FIG. 7 shows a flowchart of another example method for video encoding using intra-block copy in accordance with the disclosed technology.

FIG. 8 shows a flowchart of an example method for video decoding using intra-block copy in accordance with the disclosed technology.

FIG. 9 shows a flowchart of another example method for video decoding using intra-block copy in accordance with the disclosed technology.

FIG. 10 is a block diagram illustrating an example of the architecture for a computer system or other control device that can be utilized to implement various portions of the presently disclosed technology.

FIG. 11 shows a block diagram of an example embodiment of a mobile device that can be utilized to implement various portions of the presently disclosed technology.

FIG. 12 is a flowchart for an example method of video processing.

FIG. 13 is a flowchart for another example method of video processing.

DETAILED DESCRIPTION

Section headings are used in the present document for the ease of understanding and do not limit scope of the technologies and embodiments discussed in each section to just that section.
Due to the increasing demand of higher resolution visual information, such as video, images, three-dimensional scenes, etc., video coding methods and techniques are ubiquitous in modern technology. The techniques described in this application can apply to various visual information including video, images, three-dimensional scenes, etc. A picture of the visual information can be a frame in a video, a portion of an image, an object in a three-dimensional scene, a portion of the three-dimensional scene, etc. A block can be portion of the picture of the visual information such as a coding unit (CU), a largest coding unit (LCU), a sample, a prediction unit (PU) etc. as described in this application. A sub-block of the visual information can be a PU such as a sub-CU, a sample, etc. The PU can be a pixel, a voxel, or a smallest quantum of resolution of the visual information. Video codecs typically include an electronic circuit or software that compresses or decompresses digital video and are continually being improved to provide higher coding efficiency. A video codec converts uncompressed video to a compressed format or vice versa. There are complex relationships between the video quality, the amount of data used to represent the video (determined by the bit rate), the complexity of the encoding and decoding algorithms, sensitivity to data losses and errors, ease of editing, random access, and end-to-end delay (latency). The compressed format usually conforms to a standard video compression specification, e.g., the High Efficiency Video Coding (HEVC) standard (also known as H.265 or MPEG-H Part 2), the Versatile Video Coding standard to be finalized, or other current and/or future video coding standards.
Embodiments of the disclosed technology may be applied to existing video coding standards (e.g., HEVC, H.265) and future standards to improve runtime performance. Section headings are used in the present document to improve readability of the description and do not in any way limit the discussion or the embodiments (and/or implementations) to the respective sections only.

1. Examples of Reference Pictures and Reference Picture Lists

In HEVC, there are two types of reference pictures, short-term and long-term. A reference picture may be marked as “unused for reference” when it becomes no longer needed for prediction reference. A completely new approach for reference picture management, referred to as reference picture set (RPS) or buffer description has been introduced by HEVC.
The process of marking pictures as “used for short-term reference”, “used for long-term reference”, or “unused for reference” is done using the RPS concept. An RPS is a set of picture indicators that is signaled in each slice header and consists of one set of short-term pictures and one set of long-term pictures. After the first slice header of a picture has been decoded, the pictures in the DPB are marked as specified by the RPS. The pictures in the DPB that are indicated in the short-term picture part of the RPS are kept as short-term pictures. The short-term or long-term pictures in the DPB that are indicated in the long-term picture part in the RPS are converted to or kept as long-term pictures. And finally, pictures in the DPB for which there is no indicator in the RPS are marked as unused for reference. Thus, all pictures that have been decoded that may be used as references for prediction of any subsequent pictures in decoding order must be included in the RPS.
An RPS consists of a set of picture order count (POC) values that are used for identifying the pictures in the DPB. Besides signaling POC information, the RPS also signals one flag for each picture. Each flag indicates whether the corresponding picture is available or unavailable for reference for the current picture. Note that even though a reference picture is signaled as unavailable for the current picture, it is still kept in the DPB and may be made available for reference later on and used for decoding future pictures.
From the POC information and the availability flag, five lists of reference pictures as shown in Table 1 can be created. The list RefPicSetStCurrBefore consists of short-term pictures that are available for reference for the current picture and have POC values that are lower than the POC value of the current picture. RefPicSetStCurrAfter consist of available short-term pictures with a POC value that is higher than the POC value of the current picture. RefPicSetStFoll is a list that contains all short-term pictures that are made unavailable for the current picture but may be used as reference pictures for decoding subsequent pictures in decoding order. Finally, the lists RefPicSetLtCurr and RefPicSetLtFoll contain long-term pictures that are available and unavailable for reference for the current picture, respectively.

TABLE 1

List of Reference Picture lists

	Long-term or	Availability
List name	short-term	flag	POC

RefPicSetStCurrBefore	Short-term	Available	Lower
RefPicSetStCurrAfter	Short-term	Available	Higher
RefPicSetStFoll	Short-term	Unavailable	—
RefPicSetLtCurr	Long-term	Available	—
RefPicSetLtFoll	Long-term	Unavailable	—

1.1 Examples of Short-Term and Long-Term Reference Pictures

The syntax for the general sequence parameter set is shown below:


	Descriptor

seq_parameter_set_rbsp( ) {
sps_video_parameter_set_id	u(4)
sps_max_sub_layers_minus1	u(3)
sps_temporal_id_nesting_flag	u(1)
profile_tier_level( 1, sps_max_sub_layers_minus1 )
sps_seq_parameter_set_id	ue(v)
chroma_format_idc	ue(v)
if( chroma_format_idc = = 3 )
...
}
...
amp_enabled_flag	u(1)
sample_adaptive_offset_enabled_flag	u(1)
pcm_enabled_flag	u(1)
if( pcm_enabled_flag) {
...
}
num_short_term_ref_pic_sets	ue(v)
for( i = 0; i < num_short_term_ref_pic_sets; i++)
st_ref pic_set( i )
long_term_ref_pics_present_flag	u(1)
if( long_term_ref_pics_present_flag ) {
num_long_term_ref_pics_sps	ue(v)
for( i = 0; i < num_long_term_ref pics_sps; i++) {
It_ref_pic_poc_lsb_sps[ i ]	u(v)
used_by_curr_pic_lt_sps_flag[ i ]	u(1)
}
}
sps_temporal_mvp_enabled_flag	u(1)
...
}

The syntax for the general slice segment header is shown below:


	Descriptor

slice_segment_header( ) {
first_slice_segment_in_pic_flag	u(1)
if( nal_unit_type >= BLA_W_LP && nal_unit_type <=
RSV_IRAP_VCL23 )
no_output_of_prior_pics_flag	u(1)
slice_pic_parameter_set_id	ue(v)
if( !first_slice_segment_in_pic_flag ) {
if( dependent_slice_segments_enabled_flag )
dependent_slice_segment_flag	u(1)
slice_segment_address	u(v)
}
if( !dependent_slice_segment_flag ) {
for( i = 0; i < num_extra_slice_header_bits; i++)
slice_reserved_flag[ i ]	u(1)
slice_type	ue(v)
if( output_flag_present_flag )
pic_output_flag	u(1)
if( separate_colour_plane_flag = = 1)
colour_plane_id	u(2)
if( nal_unit_type != IDR_W_RADL && nal_unit_type !=
IDR_N_LP ) {
slice_pic_order_cnt_lsb	u(v)
short_term_ref_pic_set_sps_flag	u(1)
if( !short_term_ref_pic_set_sps_flag)
st_ref pic_set( num_short_term_ref_pic_sets )
else if( num_short_term_ref_pic_sets > 1)
short_term_ref_pic_set_idx	u(v)
if( long_term_ref pics_present_flag ) {
if( num_long_term_ref pics_sps > 0)
num_long_term_sps	ue(v)
num_long_term_pics	ue(v)
for( i = 0; i < num_long_term_sps + num_long_
term_pics; i++) {
if( i < num_long_term_sps ) {
if( num_long_term_ref_pics_sps > 1 )
lt_idx_sps[ i ]	u(v)
} else {
poc_lsb_lt[ i ]	u(v)
used_by_curr_pic_lt_flag[ i ]	u(1)
}
delta_poc_msb_present_flag[ i ]	u(1)
if( delta_poc_msb_present_flag[ i ] )
delta_poc_msb_cycle_lt[ i ]	ue(v)
}
}
...

The semantics used in the syntax tables above are defined as:
num_short_term_ref_pic_sets specifies the number of st_ref_pic_set( )syntax structures included in the SPS. The value of num_short_term_ref_pic_sets shall be in the range of 0 to 64, inclusive.
In some embodiments, a decoder may allocate memory for a total number of num_short_term_ref_pic_sets+1 st_ref_pic_set( )syntax structures since there may be a st_ref_pic_set( )syntax structure directly signaled in the slice headers of a current picture. A st_ref_pic_set( )syntax structure directly signaled in the slice headers of a current picture has an index equal to num_short_term_ref_pic_sets.
long_term_ref_pies_present_flag equal to 0 specifies that no long-term reference picture is used for inter prediction of any coded picture in the CVS.
long_term_ref_pics_present_flag equal to 1 specifies that long-term reference pictures may be used for inter prediction of one or more coded pictures in the CVS.
num_long_term_ref_pics_sps specifies the number of candidate long-term reference pictures that are specified in the SPS. The value of num_long_term_ref_pics_sps shall be in the range of 0 to 32, inclusive.
lt_ref_pic_poc_lsb_sps[i] specifies the picture order count modulo MaxPicOrderCntLsb of the i-th candidate long-term reference picture specified in the SPS. The number of bits used to represent lt_ref_pic_poc_lsb_sps[i] is equal to log2_max_pic_order_cnt_lsb_minus4+4.
used_by_curr_pic_lt_sps_flag[i] equal to 0 specifies that the i-th candidate long-term reference picture specified in the SPS is not used for reference by a picture that includes in its long-term reference picture set (RPS) the i-th candidate long-term reference picture specified in the SPS.
short_term_ref_pic_set_sps_flag equal to 1 specifies that the short-term RPS of the current picture is derived based on one of the st_ref_pic_set( )syntax structures in the active SPS that is identified by the syntax element short_term_ref_pic_set_idx in the slice header.
short_term_ref pic_set_sps_flag equal to 0 specifies that the short-term RPS of the current picture is derived based on the st_ref_pic_set( )syntax structure that is directly included in the slice headers of the current picture. When num_short_term_ref pic_sets is equal to 0, the value of short_term_ref_pic_set_sps_flag shall be equal to 0.
short_term_ref_pic_set_idx specifies the index, into the list of the st_ref_pic_set( ) syntax structures included in the active SPS, of the st_ref_pic_set( )syntax structure that is used for derivation of the short-term RPS of the current picture. The syntax element short_term_ref_pic_set_idx is represented by Ceil(Log2(num_short_term_ref_pic_sets)) bits. When not present, the value of short_term_ref_pic_set_idx is inferred to be equal to 0. The value of short_term_ref_pic_set_idx shall be in the range of 0 to num_short_term_ref pic_sets−1, inclusive.
In some embodiments, the variable CurrRpsIdx is derived as follows:

- If short_term_ref_pic_set_sps_flag is equal to 1, CurrRpsIdx is set equal to short_term_ref_pic_set_idx.
- Otherwise, CurrRpsIdx is set equal to num_short_term_ref_pic_sets.

num_long_term_sps specifies the number of entries in the long-term RPS of the current picture that are derived based on the candidate long-term reference pictures specified in the active SPS. The value of num_long_term_sps shall be in the range of 0 to num_long_term_ref_pics_sps, inclusive. When not present, the value of num_long_term_sps is inferred to be equal to 0.
num_long_term_pics specifies the number of entries in the long-term RPS of the current picture that are directly signaled in the slice header. When not present, the value of num_long_term_pics is inferred to be equal to 0.
In some embodiments, when nuh_layer_id is equal to 0, the value of num_long_term_pics shall be less than or equal to sps_max_dec_pic_buffering_minus1[TemporalID]−NumNegativePics[CurrRpsIdx]−NumPositivePics[CurrRpsIdx]−num_long_term_sps−TwoVersionsOfCurrDecPicFlag.
lt_idx_sps[i] specifies an index, into the list of candidate long-term reference pictures specified in the active SPS, of the i-th entry in the long-term RPS of the current picture. The number of bits used to represent lt_idx_sps[i] is equal to Ceil(Log2(num_long_term_ref pics_sps)). When not present, the value of lt_idx_sps[i] is inferred to be equal to 0. The value of lt_idx_sps[i] shall be in the range of 0 to num_long_term_ref_pics_sps −1, inclusive.
poc_lsb_lt[i] specifies the value of the picture order count modulo MaxPicOrderCntLsb of the i-th entry in the long-term RPS of the current picture. The length of the poc_lsb_lt[i] syntax element is log2_max_pic_order_cnt_lsb_minus4+4 bits.
used_by_curr_pic_lt_flag[ i ] equal to 0 specifies that the i-th entry in the long-term RPS of the current picture is not used for reference by the current picture.
In some embodiments, the variables PocLsbLt[i] and UsedByCurrPicLt[i] are derived as follows:

- If i is less than num_long_term_sps, PocLsbLt[i] is set equal to lt_ref_pic_poc_lsb_sps[lt_idx_sps[i]] and UsedByCurrPicLt[i] is set equal to used_by_curr_pic_lt_sps_flag[lt_idx_sps[i]].
- Otherwise, PocLsbLt[i] is set equal to poc_lsb_lt[i] and UsedByCurrPicLt[i] is set equal to used_by_curr_pic_lt_flag[i].

delta_poc_msb_present_flag[i] equal to 1 specifies that delta_poc_msb_cycle_lt[i] is present. delta_poc_msb_present_flag[i] equal to 0 specifies that delta_poc_msb_cycle_lt[i] is not present.
In some embodiments, let prevTid0Pic be the previous picture in decoding order that has TemporalId equal to 0 and is not a RASL, RADL or SLNR picture. Let setOfPrevPocVals be a set consisting of the following:

- the PicOrderCntVal of prevTidOPic,
- the PicOrderCntVal of each picture in the RPS of prevTidOPic,
- the PicOrderCntVal of each picture that follows prevTidOPic in decoding order and precedes the current picture in decoding order.

In some embodiments, when there is more than one value in setOfPrevPocVals for which the value modulo MaxPicOrderCntLsb is equal to PocLsbLt[i], delta_poc_msb_present_flag[i] shall be equal to 1.
delta_poc_msb_cycle_lt[i] is used to determine the value of the most significant bits of the picture order count value of the i-th entry in the long-term RPS of the current picture. When delta_poc_msb_cycle_lt[i] is not present, it is inferred to be equal to 0.
In some embodiments, the variable DeltaPocMsbCycleLt[i] is derived as follows:
if(i==0||i==num_long_term_sps) DeltaPocMsbCycleLt[i]=delta_poc_msb_cycle_lt[i] else DeltaPocMsbCycleLt[i]=delta_poc_msb_cycle_lt[i]+DeltaPocMsbCycleLt[i−1]

1.2 Examples of Motion Vector Prediction (MVP) between Short-Term and Long-Term Reference Pictures

In some embodiments, the motion vector prediction is only allowed if the target reference picture type and the predicted reference picture type is the same. In other words, when the types are different, motion vector prediction is disallowed.
Advanced Motion Vector Prediction (AMVP) is an example of motion vector prediction that includes an existing implementation. The relevant portion of the existing AMVP implementation is detailed below.
The motion vector mvLXA and the availability flag availableFlagLXA are derived in the following ordered steps:
(1) The sample location (xNbA0, yNbA0) is set equal to (xPb−1, yPb+nPbH) and the sample location (xNbA1, yNbA1) is set equal to (xNbA0,yNbA0−1).
(7) When availableFlagLXA is equal to 0, the following applies for (xNbAk, yNbAk) from (xNbA0, yNbA0) to (xNbA1, yNbA1) or until availableFlagLXA is equal to 1:
When availableAk is equal to TRUE and availableFlagLXA is equal to 0, the following applies:
If PredFlagLX[xNbAk][yNbAk] is equal to 1 and LongTermRefPic(currPic, currPb, refldxLX, RefPicListX) is equal to LongTermRefPic(currPic, currPb, RefldxLX[xNbAk][yNbAk], RefPicListX), availableFlagLXA is set equal to 1 and the following assignments are made:
mvLXA=MvLX[xNbAk][yNbAk]
refIdxA=RefIdxLX[xNbAk][yNbAk]
refPicListA=RefPicListX
Otherwise, when PredFlagLY[xNbAk][yNbAk](with Y=!X) is equal to 1 and LongTermRefPic(currPic, currPb, refldxLX, RefPicListX) is equal to LongTermRefPic( currPic, currPb, RefIdxLY[xNbAk][yNbAk], RefPicListY), availableFlagLXA is set to 1.
The motion vector mvLXB and the availability flag availableFlagLXB are derived in the following ordered steps:

- (1) The sample locations (xNbB0,yNbB0), (xNbB1, yNbB1) and (xNbB2, yNbB2) are set equal to (xPb+nPbW, yPb−1), (xPb+nPbW−1, yPb−1) and (xPb−1, yPb−1), respectively.

(5) When isScaledFlagLX is equal to 0, availableFlagLXB is set equal to 0 and the following applies for (xNbBk, yNbBk) from (xNbB0, yNbB0) to (xNbB2, yNbB2) or until availableFlagLXB is equal to 1:
The availability derivation process for a prediction block as specified in clause 6.4.2 is invoked with the luma location (xCb, yCb), the current luma coding block size nCbS, the luma location (xPb, yPb), the luma prediction block width nPbW, the luma prediction block height nPbH, the luma location (xNbY, yNbY) set equal to (xNbBk, yNbBk) and the partition index partldx as inputs, and the output is assigned to the prediction block availability flag availableBk.
When availableBk is equal to TRUE and availableFlagLXB is equal to 0, the following applies:

- If PredFlagLX[xNbBk][yNbBk] is equal to 1 and LongTermRefPic(currPic, currPb, refIdxLX, RefPicListX) is equal to LongTermRefPic(currPic, currPb, RefIdxLX[ xNbBk][yNbBk], RefPicListX), availableFlagLXB is set equal to 1 and the following assignments are made:

mvLXB=MvLX[xNbBk][yNbBk ]
refldxB=RefIdxLX[xNbBk][yNbBk ]
refPicListB=RefPicListX
Otherwise, when PredFlagLY[xNbBk][yNbBk] (with Y=!X) is equal to 1 and LongTermRefPic(currPic, currPb, refIdxLX, RefPicListX) is equal to LongTermRefPic( currPic, currPb, RefldxLY[xNbBk][yNbBk], RefPicListY), availableFlagLXB is set equal to 1 and the following assignments are made:
mvLXB=MvLY[xNbBk][yNbBk].
Temporal Motion Vector Prediction (TMVP) is another example of motion vector prediction that includes an existing implementation. The relevant portion of the existing TMVP implementation is detailed below.
The variables mvLXCol and availableFlagLXCol are derived as follows:
If LongTermRefPic(currPic, currPb, refIdxLX, LX) is not equal to LongTermRefPic(ColPic, colPb, refIdxCol, listCol), both components of mvLXCol are set equal to 0 and availableFlagLXCol is set equal to 0.
Otherwise, the variable availableFlagLXCol is set equal to 1, refPicListCol[refIdxCol] is set to be the picture with reference index refIdxCol in the reference picture list listCol of the slice containing prediction block colPb in the collocated picture specified by ColPic.

2. Example Embodiments of Intra-Block Copy (IBC)

Intra-block copy (IBC) has been extends the concept of motion compensation from inter-frame coding to intra-frame coding. As shown in FIG. 1, the current block is predicted by a reference block in the same picture when IBC is applied. The samples in the reference block must have been already reconstructed before the current block is coded or decoded. Although IBC is not so efficient for most camera-captured sequences, it shows significant coding gains for screen content. The reason is that there are lots of reduplicated patterns, such as icons and text characters in a screen content picture. IBC can remove the redundancy between these reduplicated patterns effectively.
In HEVC-SCC, an inter-coded coding unit (CU) can apply IBC if it chooses the current picture as its reference picture. The MV is renamed as block vector (BV) in this case, and a BV always has an integer-pixel precision. To be compatible with main profile HEVC, the current picture is marked as a “long-term” reference picture in the Decoded Picture Buffer (DPB). It should be noted that similarly, in multiple view/3D video coding standards, the interview reference picture is also marked as a “long-term” reference picture.

2.1 Embodiments of Picture Marking when IBC is Enabled

Semantics related to IBC in PPS. pps_curr_pic_ref_enabled_flag equal to 1 specifies that a picture referring to the PPS may be included in a reference picture list of a slice of the picture itself. pps_curr_pic_ref_enabled_flag equal to 0 specifies that a picture referring to the PPS is never included in a reference picture list of a slice of the picture itself. When not present, the value of pps_curr_pic_ref_enabled_flag is inferred to be equal to 0.
It is a requirement of bitstream conformance that when sps_curr_pic_ref_enabled_flag is equal to 0, the value of pps_curr_pic_ref_enabled_flag shall be equal to 0.
The variable TwoVersionsOfCurrDecPicFlag is derived as follows:
TwoVersionsOfCurrDecPicFlag=pps_curr_pic_ref enabled_flag && ( sample_adaptive_offset_enabled_flag||!pps_deblocking_filter_disabled_flag||deblocking_filter_override_enabled_flag)
When sps_max_dec_pic_buffering_minus1[TemporalId] is equal to 0, the value of TwoVersionsOfCurrDecPicFlag shall be equal to 0.
Decoding process. The current decoded picture after the invocation of the in-loop filter process is stored in the DPB in an empty picture storage buffer, the DPB fullness is incremented by one and this picture is marked as “used for short-term reference”.
When TwoVersionsOfCurrDecPicFlag is equal to 1, the current decoded picture before the invocation of the in-loop filter process as specified in clause F.8.7 [1] is stored in the DPB in an empty picture storage buffer, the DPB fullness is incremented by one, and this picture is marked as “used for long-term reference”.

3. Examples of the Joint Exploration Model (JEM)

In some embodiments, future video coding technologies are explored using a reference software known as the Joint Exploration Model (JEM). In JEM, sub-block based prediction is adopted in several coding tools, such as affine prediction, alternative temporal motion vector prediction (ATMVP), spatial-temporal motion vector prediction (STMVP), bi-directional optical flow (BIO), Frame-Rate Up Conversion (FRUC), Locally Adaptive Motion Vector Resolution (LAMVR), Overlapped Block Motion Compensation (OBMC), Local Illumination Compensation (LIC), and Decoder-side Motion Vector Refinement (DMVR).

3.1 Examples of Frame-Rate up Conversion (FRUC)

A FRUC flag can be signaled for a CU when its merge flag is true. When the FRUC flag is false, a merge index can be signaled and the regular merge mode is used. When the FRUC flag is true, an additional FRUC mode flag can be signaled to indicate which method (e.g., bilateral matching or template matching) is to be used to derive motion information for the block.
At the encoder side, the decision on whether using FRUC merge mode for a CU is based on RD cost selection as done for normal merge candidate. For example, multiple matching modes (e.g., bilateral matching and template matching) are checked for a CU by using RD cost selection. The one leading to the minimal cost is further compared to other CU modes. If a FRUC matching mode is the most efficient one, FRUC flag is set to true for the CU and the related matching mode is used.
Typically, motion derivation process in FRUC merge mode has two steps: a CU-level motion search is first performed, then followed by a Sub-CU level motion refinement. At CU level, an initial motion vector is derived for the whole CU based on bilateral matching or template matching. First, a list of MV candidates is generated and the candidate that leads to the minimum matching cost is selected as the starting point for further CU level refinement. Then a local search based on bilateral matching or template matching around the starting point is performed. The MV results in the minimum matching cost is taken as the MV for the whole CU. Subsequently, the motion information is further refined at sub-CU level with the derived CU motion vectors as the starting points.
For example, the following derivation process is performed for a W×H CU motion information derivation. At the first stage, MV for the whole W×H CU is derived. At the second stage, the CU is further split into M×M sub-CUs. The value of M is calculated as in (16), D is a predefined splitting depth which is set to 3 by default in the JEM. Then the MV for each sub-CU is derived.
$\begin{matrix} M = \max {4, \min {\frac{M}{2^{D}}, \frac{N}{2^{D}}}} & Eq . (13) \end{matrix}$
FIG. 2 shows an example of bilateral matching used in the Frame-Rate Up Conversion (FRUC) method. The bilateral matching is used to derive motion information of the current CU by finding the closest match between two blocks along the motion trajectory of the current CU (1000) in two different reference pictures (1010, 1011). Under the assumption of continuous motion trajectory, the motion vectors MV0(1001) and MV1 (1002) pointing to the two reference blocks are proportional to the temporal distances, e.g., TD0 (1003) and TD1 (1004), between the current picture and the two reference pictures. In some embodiments, when the current picture 1000 is temporally between the two reference pictures (1010, 1011) and the temporal distance from the current picture to the two reference pictures is the same, the bilateral matching becomes mirror based bi-directional MV.
FIG. 3 shows an example of template matching used in the Frame-Rate Up Conversion (FRUC) method. Template matching can be used to derive motion information of the current CU 1100 by finding the closest match between a template (e.g., top and/or left neighboring blocks of the current CU) in the current picture and a block (e.g., same size to the template) in a reference picture 1110. Except the aforementioned FRUC merge mode, the template matching can also be applied to AMVP mode. In both JEM and HEVC, AMVP has two candidates. With the template matching method, a new candidate can be derived. If the newly derived candidate by template matching is different to the first existing AMVP candidate, it is inserted at the very beginning of the AMVP candidate list and then the list size is set to two (e.g., by removing the second existing AMVP candidate). When applied to AMVP mode, only CU level search is applied.
The MV candidate set at CU level can include the following: (1) original AMVP candidates if the current CU is in AMVP mode, (2) all merge candidates, (3) several MVs in the interpolated MV field (described later), and top and left neighboring motion vectors.
When using bilateral matching, each valid MV of a merge candidate can be used as an input to generate a MV pair with the assumption of bilateral matching. For example, one valid MV of a merge candidate is (MVa, ref_a) at reference list A. Then the reference picture ref_bof its paired bilateral MV is found in the other reference list B so that ref_aand ref_bare temporally at different sides of the current picture. If such a refb is not available in reference list B, refb is determined as a reference which is different from ref_aand its temporal distance to the current picture is the minimal one in list B. After ref_bis determined, MVb is derived by scaling MVa based on the temporal distance between the current picture and ref_a, ref_b.
In some implementations, four MVs from the interpolated MV field can also be added to the CU level candidate list. More specifically, the interpolated MVs at the position (0, 0), (W/2, 0), (0, H/2) and (W/2, H/2) of the current CU are added. When FRUC is applied in AMVP mode, the original AMVP candidates are also added to CU level MV candidate set. In some implementations, at the CU level, 15 MVs for AMVP CUs and 13 MVs for merge CUs can be added to the candidate list.
The MV candidate set at sub-CU level includes an MV determined from a CU-level search, (2) top, left, top-left and top-right neighboring MVs, (3) scaled versions of collocated MVs from reference pictures, (4) one or more ATMVP candidates (e.g., up to four), and (5) one or more STMVP candidates (e.g., up to four). The scaled MVs from reference pictures are derived as follows. The reference pictures in both lists are traversed. The MVs at a collocated position of the sub-CU in a reference picture are scaled to the reference of the starting CU-level MV. ATMVP and STMVP candidates can be the four first ones. At the sub-CU level, one or more MVs (e.g., up to 17) are added to the candidate list.
Generation of an interpolated MV field. Before coding a frame, interpolated motion field is generated for the whole picture based on unilateral ME. Then the motion field may be used later as CU level or sub-CU level MV candidates.
In some embodiments, the motion field of each reference pictures in both reference lists is traversed at 4×4 block level. FIG. 4 shows an example of unilateral Motion Estimation (ME) 1200 in the FRUC method. For each 4×4 block, if the motion associated to the block passing through a 4×4 block in the current picture and the block has not been assigned any interpolated motion, the motion of the reference block is scaled to the current picture according to the temporal distance TDO and TD1 (the same way as that of MV scaling of TMVP in HEVC) and the scaled motion is assigned to the block in the current frame. If no scaled MV is assigned to a 4×4 block, the block's motion is marked as unavailable in the interpolated motion field.
Interpolation and matching cost. When a motion vector points to a fractional sample position, motion compensated interpolation is needed. To reduce complexity, bi-linear interpolation instead of regular 8-tap HEVC interpolation can be used for both bilateral matching and template matching.
The calculation of matching cost is a bit different at different steps. When selecting the candidate from the candidate set at the CU level, the matching cost can be the absolute sum difference (SAD) of bilateral matching or template matching. After the starting MV is determined, the matching cost C of bilateral matching at sub-CU level search is calculated as follows:
C=SAD+w·(|MV_x−MV_x ^s|+|MV_y−MV_y ^s|) Eq. (14)
Here, w is a weighting factor. In some embodiments, w can be empirically set to 4. MV and MV^Sindicate the current MV and the starting MV, respectively. SAD may still be used as the matching cost of template matching at sub-CU level search.
In FRUC mode, MV is derived by using luma samples only. The derived motion will be used for both luma and chroma for MC inter prediction. After MV is decided, final MC is performed using 8-taps interpolation filter for luma and 4-taps interpolation filter for chroma.
MV refinement is a pattern based MV search with the criterion of bilateral matching cost or template matching cost. In the JEM, two search patterns are supported—an unrestricted center-biased diamond search (UCBDS) and an adaptive cross search for MV refinement at the CU level and sub-CU level, respectively. For both CU and sub-CU level MV refinement, the MV is directly searched at quarter luma sample MV accuracy, and this is followed by one-eighth luma sample MV refinement. The search range of MV refinement for the CU and sub-CU step are set equal to 8 luma samples.
In the bilateral matching merge mode, bi-prediction is applied because the motion information of a CU is derived based on the closest match between two blocks along the motion trajectory of the current CU in two different reference pictures. In the template matching merge mode, the encoder can choose among uni-prediction from list0, uni-prediction from listl, or bi-prediction for a CU. The selection ca be based on a template matching cost as follows:


	If costBi <= factor * min (cost0, cost1)

bi-prediction is used;

Otherwise, if cost0 <= cost1

uni-prediction from list0 is used;

Otherwise,

	uni-prediction from list1 is used;

Here, cost0 is the SAD of list0 template matching, cost1 is the SAD of list1 template matching and costBi is the SAD of bi-prediction template matching. For example, when the value of factor is equal to 1.25, it means that the selection process is biased toward bi-prediction. The inter prediction direction selection can be applied to the CU-level template matching process.

3.2 Examples of decoder-side motion vector refinement (DMVR)

In a bi-prediction operation, for the prediction of one block region, two prediction blocks, formed using a motion vector (MV) of list0 and a MV of list1, respectively, are combined to form a single prediction signal. In the decoder-side motion vector refinement (DMVR) method, the two motion vectors of the bi-prediction are further refined by a bilateral template matching process. The bilateral template matching applied in the decoder to perform a distortion-based search between a bilateral template and the reconstruction samples in the reference pictures in order to obtain a refined MV without transmission of additional motion information.
In DMVR, a bilateral template is generated as the weighted combination (i.e. average) of the two prediction blocks, from the initial MV0 of list0 and MV1 of list1,respectively, as shown in FIG. 5. The template matching operation consists of calculating cost measures between the generated template and the sample region (around the initial prediction block) in the reference picture. For each of the two reference pictures, the MV that yields the minimum template cost is considered as the updated MV of that list to replace the original one. In the JEM, nine MV candidates are searched for each list. The nine MV candidates include the original MV and 8 surrounding MVs with one luma sample offset to the original MV in either the horizontal or vertical direction, or both. Finally, the two new MVs, i.e., MV0′ and MV1′ as shown in FIG. 5, are used for generating the final bi-prediction results. A sum of absolute differences (SAD) is used as the cost measure.
DMVR is applied for the merge mode of bi-prediction with one MV from a reference picture in the past and another from a reference picture in the future, without the transmission of additional syntax elements. In the JEM, when LIC, affine motion, FRUC, or sub-CU merge candidate is enabled for a CU, DMVR is not applied.

4. Exemplary Methods for IBC in Video Coding

FIG. 6 shows a flowchart of an exemplary method for video encoding using intra-block copy. The method 1600 includes, at step 1610, determining whether a current block of the current picture is to be encoded using a motion compensation algorithm. The method 1600 includes, in step 1620, encoding, based on the determining, the current block by selectively applying an intra-block copy to the current block. More generally, whether or not to apply the intra-block copy to the current block is based on whether the current block is to be encoded using a specific motion compensation algorithm.
FIG. 7 shows a flowchart of another exemplary method video encoding using intra-block copy. The method 1700 includes, at step 1710, determining whether a current block of the current picture is to be encoded using an intra-block copy. The method 1700 includes, in step 1720, encoding, based on the determining, the current block by selectively applying a motion compensation algorithm to the current block. More generally, whether or not to encode the current block using the motion compensation algorithm is based on whether the current block is to be encoded using the intra-block copy.
FIG. 8 shows a flowchart of an exemplary method for video decoding using intra-block copy. The method 1800 includes, at step 1810, determining whether a current block of the current picture is to be decoded using a motion compensation algorithm. The method 1800 includes, in step 1820, decoding, based on the determining, the current block by selectively applying an intra-block copy to the current block. More generally, whether or not to apply the intra-block copy to the current block is based on whether the current block is to be decoded using a specific motion compensation algorithm.
FIG. 9 shows a flowchart of another exemplary method video decoding using intra-block copy. The method 1900 includes, at step 1910, determining whether a current block of the current picture is to be decoded using an intra-block copy. The method 1900 includes, in step 1920, decoding, based on the determining, the current block by selectively applying a motion compensation algorithm to the current block. More generally, whether or not to decode the current block using the motion compensation algorithm is based on whether the current block is to be decoded using the intra-block copy.
The methods 1600, 1700, 1800 and 1900, described in the context of FIGS. 6-11, may further include are further the step of determining whether the motion compensation algorithm is compatible with the intra-block copy. The compatibility of the intra-block copy and the motion compensation algorithms are elucidated in the following examples described for different specific motion compensation algorithms.
Example 1. It is proposed that bilateral matching in FRUC is not valid if there is at least one reference picture identical to the current picture in the reference list. In this case, the FRUC mode flag is not signaled when the FRUC flag is 1. The FRUC mode is always inferred as template matching.
Example 2. It is proposed that template matching in FRUC only searches integer-pixels without searching the sub-pixels if the reference picture is the current picture.
Example 3. It is proposed that DMVR cannot be applied for IBC coded blocks. In one example, if at least one reference picture of the current block is the current picture, DMVR is not conducted in the current block.

5. Example Implementations of the Disclosed Technology

FIG. 10 is a block diagram illustrating an example of the architecture for a computer system or other control device 2000 that can be utilized to implement various portions of the presently disclosed technology, including (but not limited to) methods 1600, 1700, 1800 and 1900. In FIG. 10, the computer system 2000 includes one or more processors 2005 and memory 2010 connected via an interconnect 2025. The interconnect 2025 may represent any one or more separate physical buses, point to point connections, or both, connected by appropriate bridges, adapters, or controllers. The interconnect 2025, therefore, may include, for example, a system bus, a Peripheral Component Interconnect (PCI) bus, a HyperTransport or industry standard architecture (ISA) bus, a small computer system interface (SCSI) bus, a universal serial bus (USB), IIC (I2C) bus, or an Institute of Electrical and Electronics Engineers (IEEE) standard 674 bus, sometimes referred to as “Firewire.”
The processor(s) 2005 may include central processing units (CPUs) to control the overall operation of, for example, the host computer. In certain embodiments, the processor(s) 2005 accomplish this by executing software or firmware stored in memory 2010. The processor(s) 2005 may be, or may include, one or more programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application specific integrated circuits (ASICs), programmable logic devices (PLDs), or the like, or a combination of such devices.
The memory 2010 can be or include the main memory of the computer system. The memory 2010 represents any suitable form of random access memory (RAM), read-only memory (ROM), flash memory, or the like, or a combination of such devices. In use, the memory 2010 may contain, among other things, a set of machine instructions which, when executed by processor 2005, causes the processor 2005 to perform operations to implement embodiments of the presently disclosed technology.
Also connected to the processor(s) 2005 through the interconnect 2025 is a (optional) network adapter 2015. The network adapter 2015 provides the computer system 2000 with the ability to communicate with remote devices, such as the storage clients, and/or other storage servers, and may be, for example, an Ethernet adapter or Fiber Channel adapter.
FIG. 11 shows a block diagram of an example embodiment of a mobile device 2100 that can be utilized to implement various portions of the presently disclosed technology, including (but not limited to) methods 1600, 1700, 1800 and 1900. The mobile device 2100 can be a laptop, a smartphone, a tablet, a camcorder, or other types of devices that are capable of processing videos. The mobile device 2100 includes a processor or controller 2101 to process data, and memory 2102 in communication with the processor 2101 to store and/or buffer data. For example, the processor 2101 can include a central processing unit (CPU) or a microcontroller unit (MCU). In some implementations, the processor 2101 can include a field-programmable gate-array (FPGA). In some implementations, the mobile device 2100 includes or is in communication with a graphics processing unit (GPU), video processing unit (VPU) and/or wireless communications unit for various visual and/or communications data processing functions of the smartphone device. For example, the memory 2102 can include and store processor-executable code, which when executed by the processor 2101, configures the mobile device 2100 to perform various operations, e.g., such as receiving information, commands, and/or data, processing information and data, and transmitting or providing processed information/data to another device, such as an actuator or external display.
To support various functions of the mobile device 2100, the memory 2102 can store information and data, such as instructions, software, values, images, and other data processed or referenced by the processor 2101. For example, various types of Random-Access Memory (RAM) devices, Read Only Memory (ROM) devices, Flash Memory devices, and other suitable storage media can be used to implement storage functions of the memory 2102. In some implementations, the mobile device 2100 includes an input/output (I/O) unit 2103 to interface the processor 2101 and/or memory 2102 to other modules, units or devices. For example, the I/O unit 2103 can interface the processor 2101 and memory 2102 with to utilize various types of wireless interfaces compatible with typical data communication standards, e.g., such as between the one or more computers in the cloud and the user device. In some implementations, the mobile device 2100 can interface with other devices using a wired connection via the I/O unit 2103. The mobile device 2100 can also interface with other external interfaces, such as data storage, and/or visual or audio display devices 2104, to retrieve and transfer data and information that can be processed by the processor, stored in the memory, or exhibited on an output unit of a display device 2104 or an external device. For example, the display device 2104 can display a video frame that includes a block (a CU, PU or TU) that applies the intra-block copy based on whether the block is encoded using a motion compensation algorithm, and in accordance with the disclosed technology.
Listed below are some examples of the technology described in this application. A block, as used in this application, can be a contiguous or a noncontiguous collection of pixels, voxels, sub-pixels, and/or sub-voxels. For example, a block can be rectilinear, such as a 4×4 square, 6×4 rectangle, or curvilinear, such as an ellipse.
A portion of the visual information, as used in this application, can be a subset of visual information. A coded representation, as used in this application, can be a bitstream representing the visual information that has been encoded using one of the techniques described in this application. An indicator, as used in this application, can be a flag or a field in the coded representation or can be multiple separate flags or fields.
A decoding technique, as used in this application can be applied by a decoder and can be implemented in hardware or software. The decoding technique can undo in reverse sequence everything a coder does. When an appropriate decoding technique is applied to an encoded representation, a visual information can be obtained as a result.
An initial block in the plurality of blocks, as used in this application, is a block occurring before the first block in the coded representation.
As used in this specification, the cost measure can be a sum of absolute differences (SAD) is used as the cost measure. The sample region can include, nine motion vector (MV) candidates in each list. The nine MV candidates include the original MV and eight surrounding MVs with one luma sample offset to the original MV in either the horizontal or vertical direction, or both.
1. A method of decoding visual information (e.g., method 1200 as depicted in FIG. 12), comprising: determining (1202), from a coded representation, that a block being decoded representing a portion of the visual information is coded using a first coding technique; and decoding (1204) the coded representation by using a first decoding technique corresponding to the first coding technique and by excluding use of a second decoding technique corresponding to the second coding technique; wherein one of the two techniques corresponds to a coding technique that uses a same video picture for coding the block being decoded as a reference picture and the other of the two coding techniques corresponds to a Frame-Rate Up Conversion (FRUC) technique that uses reference pictures associated with the visual information to refine a motion information for coding the block being decoded.
2. The method of clause 1, comprising decoding the second block using the FRUC decoding technique by: obtaining a plurality of blocks including the block being encoded, a merge flag indicating that FRUC merge mode is used to encode the block being decoded, and a FRUC mode flag indicating whether a bilateral matching or a template matching is used to encode the block being decoded; and based on the FRUC mode flag, decoding the block being decoded using the bilateral matching or the template matching.
3. The method of any of clauses 1-2, comprising: obtaining the merge flag indicating that FRUC merge mode is used to encode the block being decoded; and in case that at least one reference picture is identical to a picture containing the block being decoded, inferring to use the template matching to decode the block being decoded.
4. The method of any of clauses 1-3, comprising: in case that the reference picture is the picture containing the block being decoded, decoding the FRUC technique that uses the template matching by only searching integer-pixels without searching the sub-pixels.
5. A method of decoding visual information (e.g., method 1300 as depicted in FIG. 13), comprising: determining (1302), from a coded representation, that a block being decoded representing a portion of the visual information is coded using a first coding technique; and decoding (1304) the coded representation by using a first decoding technique corresponding to the first coding technique and by excluding use of a second decoding technique corresponding to the second coding technique; wherein one of two techniques corresponds to a coding technique that uses a same video picture for coding the block being decoded as a reference picture and the other of the two coding techniques corresponds to a Decoder-side Motion Vector Refinement (DMVR) technique that uses a first reference block of a first reference picture associated with the visual information and a second reference block of a second reference picture associated with visual information to derive a motion information for coding the block being decoded.
6. The method of clauses 1 or 5, comprising, deciding, based on the determining, that the coded representation excludes an indicator of use of a second coding technique for the block.
7. The method of clauses 1 or 5, wherein the coding technique that uses a same video picture for coding the block being decoded as a reference picture comprises the intra-block copy (IBC).
8. The method of clause 1 or 5, wherein the first coding technique corresponds to intra-block copy (IBC) that uses a second block of a same video picture for coding the block being decoded.
9. The method of clause 1 or 5, comprising decoding a first block encoded using the IBC technique by: obtaining a first plurality of encoded blocks representing the first picture; decoding an initial block in the first plurality of encoded blocks; and upon decoding the initial block, decoding a first block in the first plurality of encoded blocks based on the initial block.
10. The method of any of clauses 5 to 8, comprising decoding a second block of a second picture encoded using the DMVR technique by: decoding the first reference block and the second reference block from the coded presentation; applying a bilateral template matching based on the first reference block and the second reference block to obtain a refined motion vector associated with the second block.
11. The method of any of clauses 1 to 10, comprising: when at least one of the first reference picture and the second reference picture is the second picture, excluding using the DMVR technique to decode the block being decoded.
12. A method for encoding a visual information, comprising: encoding a block being encoded of a picture of the visual information by using a first encoding technique and by excluding use of a second encoding technique; and wherein one of the two techniques corresponds to an encoding technique that uses a same video picture for coding the block being encoded as a reference picture and the other of the two coding techniques corresponds to a Frame-Rate Up Conversion (FRUC) technique that uses reference pictures associated with the visual information to refine a motion information for encoding the block being encoded.
13. The method of clause 12, comprising encoding the block being encoded using the FRUC technique by: dividing the picture into a plurality of blocks including the block being encoded; determining whether a merge flag for the block being encoded indicates to use a merge mode comprising a regular merge mode or a FRUC merge mode, wherein the FRUC merge mode comprises a bilateral matching or a template matching; deciding whether to use the regular merge mode, the bilateral matching or the template matching based on a computational cost associated with each merge mode; and upon said deciding to perform the FRUC merge mode, encoding the FRUC indicator indicating that FRUC merge mode was used to encode the block being encoded and a FRUC mode flag indicating whether the bilateral matching or the template matching was used.
14. The method of clauses 12-13, comprising: when at least one reference picture is identical to the picture and the merge flag indicates to use the FRUC merge mode, excluding signaling the FRUC mode flag thereby expecting a decoder to infer that the merge flag indicates to use the template matching.
15. The method of any of clauses 12 to 14, comprising: when the reference picture is the picture, performing the template matching in FRUC by only searching integer-pixels without searching the sub-pixels.
16. A method for encoding a visual information, comprising: encoding a block being encoded of a picture of the visual information by using a first encoding technique and by excluding use of a second encoding technique; and wherein one of two techniques corresponds to an encoding technique that uses a same video picture for coding the block being encoded as a reference picture and the other of the two coding techniques corresponds to a Decoder-side Motion Vector Refinement (DMVR) technique that uses a first reference block of a first reference picture associated with the visual information and a second reference block of a second reference picture associated with visual information to derive a motion information for coding the block being encoded.
17. The method of any of clauses 12 or 16, wherein the encoding technique that uses the same video picture for encoding the block being encoded as a reference picture comprises the intra-block copy (IBC).
18. The method of any of clauses 12 and 16, comprising encoding the block being encoded using the IBC technique by: dividing the first picture into a first plurality of blocks; encoding an initial block in the first plurality of blocks; and upon encoding the initial block, encoding the block being encoded in the first plurality of blocks based on the initial block.
19. The method of any of clauses 16 to 18, comprising encoding a second block being encoded using the DMVR technique by: obtaining a first motion vector associated with the first reference block and a second motion vector associated with the second reference block; and decoding the first reference block and the second reference block from the coded presentation with the first motion vector and second motion vector; applying a bilateral template matching based on the first reference block and the second reference block to obtain a refined motion vector associated with the second block without transmission of additional motion information between an encoder and decoder.
20. The method of any of clauses 16-19, comprising:
avoiding encoding the block being encoded using the DMVR technique.
21. The method of any of clauses 16 to 20, comprising:
when at least one of the first reference picture and the second reference picture is the picture, excluding using the DMVR technique to encode the block being encoded.
22. A video processing apparatus comprising a processor configured to implement a method recited in any one or more of clauses 1 to 21.
23. A computer readable medium having code stored thereon, the code, upon execution, causing a processor to implement a method recited in any one or more of clauses 1 to 22.
In some embodiments, a video decoder apparatus may implement a method of video decoding in which the intra-block copy as described herein is used for video decoding. The method may be similar to the above-described methods 1200, 1300, 1600, 1700, 1800 and 1900.
In some embodiments, a decoder-side method of video decoding may use the intra-block copy for improving video quality by determining whether a current block of the current picture is to be decoded using a motion compensation algorithm, and decoding, based on the determining, the current block by selectively applying an intra-block copy to the current block.
In other embodiments, a decoder-side method of video decoding may use the intra-block copy for improving video quality by determining whether a current block of the current picture is to be decoded using an intra-block copy, and decoding, based on the determining, the current block by selectively applying a motion compensation algorithm to the current block.
In some embodiments, the video decoding methods may be implemented using a decoding apparatus that is implemented on a hardware platform as described with respect to FIG. 10 and FIG. 11.
Below are improvements measured by incorporating IBC into VTM-1.0, which is a reference software for the video coding standard named Versatile Video Coding (VVC). VTM stands for VVC Test Model.


	Over VTM-1.0

	Y	U	V	EncT	DecT

Class A1	−0.33%	−0.50%	−0.49%	162%	100%
Class A2	−0.96%	−1.17%	−0.77%	159%	98%
Class B	−0.94%	−1.14%	−1.34%	162%	102%
Class C	−1.03%	−1.58%	−1.92%	160%	101%
Class E	−1.48%	−1.46%	−1.80%	160%	104%
Overall	−0.95%	−1.19%	−1.31%	161%	101%
Class D	−0.57%	−0.73%	−0.91%	161%	100%
Class F (optional)	−20.25%	−20.15%	−20.93%	194%	95%
Class SCC	−52.94%	−53.26%	−53.37%	217%	74%
1080p

In the above table, “Y”, “U”, “V” represent colors in the YUV color encoding system which encodes a color image or video taking human perception into account. The EncT and DecT represent a ratio of the encoding and decoding time using the IBC compared to the encoding and decoding time without the IBC, respectively. Specifically,
EncT=TestEncodingTime/anchorEncodingTime
DecT=TestEncodingTime/anchorEncodingTime.
The various classes, such as Class A1, Class A2, etc., represent a grouping of standard video sequences used in testing performance of various video coding techniques. The negative percentages under the “Y”, “U”, “V” columns represent bit-rate savings when IBC is added to VTM-1.0. The percentages under the EncT and DecT columns that are over 100% show how much the encoding/decoding with IBC is slower than encoding/decoding without IBC. For example, a percentage of 150% means that the encoding/decoding with IBC is 50% slower than the encoding/decoding without the IBC. The percentage below 100% shows how much the encoding/decoding with IBC is faster than encoding/decoding without the IBC. Two classes, class F and class SCC, highlighted in green in the table above, show that bit-rate savings exceed 3%.
From the foregoing, it will be appreciated that specific embodiments of the presently disclosed technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the scope of the invention. Accordingly, the presently disclosed technology is not limited except as by the appended claims.
Implementations of the subject matter and the functional operations described in this patent document can be implemented in various systems, digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. Implementations of the subject matter described in this specification can be implemented as one or more computer program products, i.e., one or more modules of computer program instructions encoded on a tangible and non-transitory computer readable medium for execution by, or to control the operation of, data processing apparatus. The computer readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, a composition of matter effecting a machine-readable propagated signal, or a combination of one or more of them. The term “data processing unit” or “data processing apparatus” encompasses all apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. The apparatus can include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.
A computer program (also known as a program, software, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub programs, or portions of code). A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a communication network.
The processes and logic flows described in this specification can be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit).
Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read only memory or a random access memory or both. The essential elements of a computer are a processor for performing instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto optical disks, or optical disks. However, a computer need not have such devices. Computer readable media suitable for storing computer program instructions and data include all forms of nonvolatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.
It is intended that the specification, together with the drawings, be considered exemplary only, where exemplary means an example. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Additionally, the use of “or” is intended to include “and/or”, unless the context clearly indicates otherwise.
While this patent document contains many specifics, these should not be construed as limitations on the scope of any invention or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this patent document in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.
Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Moreover, the separation of various system components in the embodiments described in this patent document should not be understood as requiring such separation in all embodiments.
Only a few implementations and examples are described and other implementations, enhancements and variations can be made based on what is described and illustrated in this patent document.

Claims

What is claimed is:

1. A method of coding video data, comprising:

determining, for a conversion between a current video block of a video and a bitstream representation of the video, that a first technique is applied for the current video block; and

performing the conversion by applying the first technique and by excluding applying a second technique;

wherein one of the first and the second techniques corresponds to an intra-block copy (IBC) technique, and the other of the first and the second techniques corresponds to a Decoder-side Motion Vector Refinement (DMVR) technique.

2. The method of claim 1, wherein in response to the IBC technique being applied during the conversion, a prediction of the current video block is derived based on sample values from a same video slice with the current video block, and wherein the sample values are determined by block vectors.

3. The method of claim 1, wherein in response to the DMVR technique being applied during the conversion, a refined motion vector for the current video block is derived based on a cost calculation between prediction samples of the current video block in different reference pictures of the current video block.

4. The method of claim 3, wherein the cost calculation is based on a sum of absolute difference (SAD).

5. The method of claim 1, further comprising:

in response to at least one of reference pictures of the current video block is a current picture which includes the current video block, excluding applying the DMVR technique for the current video block during the conversion.

6. The method of claim 1, wherein the first technique corresponds to the IBC technique, and the second technique corresponds to the DMVR technique.

7. The method of claim 1, wherein the first technique corresponds to the DMVR technique, and the second technique corresponds to the IBC technique.

8. The method of claim 1, wherein the conversion includes encoding the current video block into the bitstream representation.

9. The method of claim 1, wherein the conversion includes decoding the current video block from the bitstream representation.

10. An apparatus for coding video data comprising a processor and a non-transitory memory with instructions thereon, wherein the instructions upon execution by the processor, cause the processor to:

11. The apparatus of claim 10, wherein in response to the IBC technique being applied during the conversion, a prediction of the current video block is derived based on sample values from a same video slice with the current video block, and wherein the sample values are determined by block vectors.

14. The apparatus of claim 10, wherein in response to the DMVR technique being applied during the conversion, a refined motion vector for the current video block is derived based on a cost calculation between prediction samples of the current video block in different reference pictures of the current video block.

15. The apparatus of claim 14, wherein the cost calculation is based on a sum of absolute difference (SAD).

16. The apparatus of claim 10, further comprising:

17. The apparatus of claim 10, wherein the conversion includes encoding the current video block into the bitstream representation.

18. The apparatus of claim 10, wherein the conversion includes decoding the current video block from the bitstream representation.

19. A non-transitory computer-readable storage medium storing instructions that cause a processor to:

20. A non-transitory computer-readable recording medium storing a bitstream representation which is generated by a method performed by a video processing apparatus, wherein the method comprises:

generating the bitstream representation from the current video block by using the first technique and by excluding applying a second technique;