[go: up one dir, main page]

US20190318966A1 - High k metal gate stack with single work-function metal - Google Patents

High k metal gate stack with single work-function metal Download PDF

Info

Publication number
US20190318966A1
US20190318966A1 US16/454,178 US201916454178A US2019318966A1 US 20190318966 A1 US20190318966 A1 US 20190318966A1 US 201916454178 A US201916454178 A US 201916454178A US 2019318966 A1 US2019318966 A1 US 2019318966A1
Authority
US
United States
Prior art keywords
opening
gate
work function
integrated circuit
doped high
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US16/454,178
Inventor
Takashi Ando
Balaji Kannan
Siddarth Krishnan
Unoh Kwon
Shahab Siddiqui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Adeia Semiconductor Solutions LLC
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to US16/454,178 priority Critical patent/US20190318966A1/en
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KRISHNAN, SIDDARTH, SIDDIQUI, SHAHAB, ANDO, TAKASHI, KANNAN, BALAJI, KWON, UNOH
Publication of US20190318966A1 publication Critical patent/US20190318966A1/en
Assigned to TESSERA, INC. reassignment TESSERA, INC. ASSIGNMENT OF ASSIGNOR'S INTEREST Assignors: INTERNATIONAL BUSINESS MACHINES CORPORATION
Assigned to BANK OF AMERICA, N.A. reassignment BANK OF AMERICA, N.A. SECURITY INTEREST Assignors: DTS, INC., IBIQUITY DIGITAL CORPORATION, INVENSAS BONDING TECHNOLOGIES, INC., INVENSAS CORPORATION, PHORUS, INC., ROVI GUIDES, INC., ROVI SOLUTIONS CORPORATION, ROVI TECHNOLOGIES CORPORATION, TESSERA ADVANCED TECHNOLOGIES, INC., TESSERA, INC., TIVO SOLUTIONS INC., VEVEO, INC.
Assigned to TESSERA, INC. reassignment TESSERA, INC. CORRECTIVE ASSIGNMENT TO CORRECT THE 16/161,111 PREVIOUSLY RECORDED ON REEL 051489 FRAME 0324. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Assignors: INTERNATIONAL BUSINESS MACHINES CORPORATION
Assigned to TESSERA LLC reassignment TESSERA LLC CERTIFICATE OF CONVERSION & CHANGE OF NAME Assignors: TESSERA, INC.
Assigned to ADEIA SEMICONDUCTOR SOLUTIONS LLC reassignment ADEIA SEMICONDUCTOR SOLUTIONS LLC CHANGE OF NAME Assignors: TESSERA LLC
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H01L21/823828—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28238—Making the insulator with sacrificial oxide
    • H01L21/823842—
    • H01L21/823857—
    • H01L27/092—
    • H01L29/42372—
    • H01L29/4966—
    • H01L29/517—
    • H01L29/66545—
    • H10D64/01318—
    • H10D64/0134—
    • H10D64/01352—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0177—Manufacturing their gate conductors the gate conductors having different materials or different implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0181—Manufacturing their gate insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/8314—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] the IGFETs characterised by having gate insulating layers with different properties
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10P32/14—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/83135—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] the IGFETs characterised by having different gate conductor materials or different gate conductor implants

Definitions

  • the present invention generally relates to Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) made on a semiconductor substrate.
  • MOSFETs Metal Oxide Semiconductor Field Effect Transistors
  • the invention relates to making MOSFETs having a single work-function metal for both the N-FET and the P-FET in a replacement metal gate structure.
  • the gate may be made from a “replacement metal gate” (RMG) process which requires forming a gate opening in a dielectric layer and filling the gate opening with gate materials as opposed to patterning the gate materials and then surrounding them with a dielectric. Due to the number of work function materials required in current gates, the openings may be difficult to subsequently fill with the bulk material and may result in high gate resistances.
  • RMG replacement metal gate
  • the current invention is a novel structure to both simplify and improve the performance of the replacement metal gate stack for advanced node FETs, and the method of making the same.
  • the current invention allows the correct work functions to be set for N-FETs and P-FETs, while simultaneously allowing substantial space in the gate opening for the bulk fill material which results in lower gate resistance. More specifically, doping of a high-k dielectric film of the gates allows both the N-FET and P-FET gates to share the same, thin, work function metal (single work function metal).
  • An object of the current invention is a method to form high-k metal gates of a N-FET and a P-FETs by a replacement metal gate process in advanced nodes
  • the replacement metal gate process may be a “high-k first” or a “high-k last” (an embodiment illustrated by the figures) process.
  • the node may be 14 nm and below such that the gate opening may be less than 20 nanometers wide.
  • a further object of the current invention is that the gates of the N-FET and the P-FET share the same, thin work function metal.
  • Another object of the current invention is that the gate oxide is doped.
  • the dopants differ in the N-FET gate oxide and the P-FET gate oxide.
  • Yet a further object of the current invention is to provide a low resistance gate structure by increasing the amount of bulk fill material in the gate opening lined by the work function metal.
  • the bulk fill width may be 20-70% of the gate opening width.
  • An object of the present invention is to form an integrated circuit (IC) including a first gate of an N-FET and a second gate of a P-FET on the substrate wherein the first and second gates have a gate opening width of less than 20 nanonmeters.
  • the IC also includes a work function metal lining both the first gate opening and the second gate opening.
  • a high dielectric material is between the work function metal and the substrate wherein the high dielectric material is doped with an n-dopant in the first gate and is doped with a p-dopant in the second gate.
  • a bulk fill material fills a remainder of gate opening.
  • Another object of the current invention is a method of forming an N-FET metal gate and a P-FET metal gate sharing the same work function metal, the method comprising.
  • the method provides a dielectric layer over a substrate wherein the dielectric layer has a first opening over an N-FET region of the substrate and a second opening over a P-FET region of the substrate.
  • a high dielectric constant material is formed so as to be in contact with the substrate in the N-FET region and in the P-FET region.
  • a work function metal lines the first and second openings which are subsequently a bulk fill material.
  • FIG. 1 is a flow chart of an embodiment to create oppositely doped gates of FETs sharing the same work function (herein “WF”) metal;
  • WF work function
  • FIG. 2 illustrates a substrate having an overlying dielectric material and openings in the dielectric material according to an embodiment of the present invention
  • FIG. 3 illustrates a high dielectric constant material lining the openings according to an embodiment of the present invention
  • FIG. 4 a illustrates a p-dopant stack formed over the second region of the substrate according to an embodiment of the present invention
  • FIG. 4 b illustrates a n-dopant stack formed over the substrate according to an embodiment of the present invention
  • FIG. 5 illustrates the substrate after annealing and removal of dopant and annealing stacks according to an another embodiment of the present invention.
  • FIG. 6 illustrates oppositely doped high-k replacement metal gates having single work function metal according to an embodiment of the present invention.
  • the basic principle of the invention is a method forming oppositely doped high dielectric constant replacement metal gates which have the same work function (WF) metal stack. This is in contrast to normal methods in which work function tuning of an FET is achieved by varying the WF metal materials and thicknesses of materials. Work function tuning is a way to adjust threshold voltages of a device, thus creating two work function regions which, in turn creates two threshold voltage regions.
  • step 10 dummy gates over the N-FET and P-FET gate regions of the substrate are removed to leave gate openings (which can also be referred to as gate trenches).
  • gate openings which can also be referred to as gate trenches.
  • step 15 a high dielectric constant material is formed in the gate openings.
  • step 20 p and n dopant stacks are formed as well as an annealing stack.
  • step 25 an anneal diffuses the respective dopants into each of the high dielectric constant materials to form first and second gate dielectric stacks.
  • step 30 following the anneal, the dopant stacks are removed.
  • step 40 a shared, thin, work function metal is used in both the N-FET and the P-FET. Finally, either with or without a subsequent wetting layer, a bulk fill material is used to fill the opening to complete the gate structure. Then next figures will illustrate embodiments of the structures during the steps of FIG. 1 .
  • a substrate 100 has a two regions, first region 101 and second region 102 .
  • the substrate 100 may be a semiconductor or semiconductor on insulator substrate.
  • the substrate 100 may be planar or may have fins.
  • the first and second regions are oppositely doped regions which will become the N-FET and P-FETs.
  • the substrate 100 has a dielectric layer or layers 105 over it.
  • the dielectric layer has at least one dummy gate opening ( 110 - 1 and 110 - 2 ) over each of the first and second regions ( 101 and 102 ) of the substrate.
  • the substrate 100 may have source and drain regions on either side of the openings 110 - 1 and 110 - 2 , which, for simplification, have been omitted from FIG. 1 .
  • the oppositely doped regions of the substrate 100 may be separated by an isolation (insulation) region which, for simplification, is also not illustrated.
  • the dummy gate openings 110 - 1 and 110 - 2 were formed when a dummy gate material was removed.
  • the dummy gate opening dimensions will vary with node, but in a 14 nm node example the openings may be from about 18 to 13 nm wide and ranges in between while the height may be 100 nm to 200 nm high over a buried oxide region in a semiconductor on insulator substrate embodiment.
  • the high dielectric constant (herein “high-k”) material 115 is formed in the dummy gate openings 110 - 1 and 110 - 2 .
  • high-k refers to dielectric constants greater than 4 (i.e. greater than the dielectric constant of SiO 2 ).
  • the high-k material 115 may include more than one layer, for example the high-k material may include both an interfacial layer next to the substrate and a higher k material above the interfacial layer.
  • An example interfacial layer may be a silicon oxide or a silicon oxynitride.
  • Examples of higher-k materials include hafnium oxide, hafnium silicate, zirconium oxide, zirconium silicate, aluminum oxide, titanium oxide, yttrium oxide among others.
  • the high-k material lines the dummy gate openings 110 - 1 / 110 - 2 , which is a “high-k” last embodiment of a replacement metal gate.
  • the high-k material could have also been formed in a “high-k first process”. In such a case, the high-k material would only appear at the bottom of the dummy gate openings and not line the sidewalls.
  • the “high-k last” process shown in FIG. 3 has the advantage that the high-k material is not damaged during dummy gate removal.
  • the high-k material 115 may be formed by one or more of an atomic layer deposition, chemical vapor deposition, thermal oxidation, and others.
  • the higher-k portion of the high-k material 115 may be from about 10 ⁇ to about 25 ⁇ thick, and ranges therebetween.
  • the thickness range of the higher-k material is critical for proper subsequent dopant diffusion. Specifically, too thick of a higher-k material results in inadequate diffusion of dopant. Too thin of a higher-k material results in dopants in direct contact with interfacial layer and increase the Tiny (inverse of gate capacitance) or cause gate leakage issues.
  • first and second dopant layers will be formed.
  • the first region 101 of the substrate 100 may be an N-FET region and the second region 102 may be a P-FET region.
  • a p-dopant stack 120 - 2 may be initially formed everywhere and then removed over the N-FET region 101 .
  • the p-dopant 120 - 2 may be a tri-layer, from bottom to top, of a (a) first titanium nitride layer, (b) aluminum (Al) or an aluminum containing layer, and a (c) second titanium nitride layer.
  • the thickness of the first titanium nitride layer ( 120 - 2 a ) is from about 5 ⁇ to about 30 ⁇ and ranges therebetween.
  • the thickness of the aluminum containing layer ( 120 - 2 b ) is from about 5 ⁇ to about 30 ⁇ ranges therebetween.
  • the thickness of the second titanium nitride layer ( 120 - 2 c ) is from about 5 ⁇ to about 30 ⁇ and ranges therebetween. If the p-dopant stack 120 - 2 is too thick the dummy gate opening 110 - 2 will be clogged. If there is too little or too much (depending on the specific layer) the threshold voltage (Vt) will shift too much or too little because the dopant will diffuse too much or too little.
  • the second TiN layer ( 120 - 2 c ) is too thin Lanthanum get into the PFET gate stack.
  • these layers are too thin or too thick, gate leakage may increases due to suboptimal subsequent dopant diffusion.
  • too much dopant for example, Aluminum
  • an n-dopant stack 120 - 1 may be formed everywhere on the substrate along with an annealing stack 125 .
  • the n-dopant stack 120 - 1 in the N-FET region 101 of the substrate 100 there exists one dopant stack (the n-dopant stack 120 - 1 ) while in the P-FET region 102 of the substrate 100 there exist two dopant stacks (p-dopant 120 - 2 under the n-dopant 120 - 1 ).
  • the n-dopant stack may be lanthanum (La) or a lanthanum containing film such as lanthanum oxide (La 2 O 3 ), or some other rare earth dopant such as yttrium which shifts the effective work function to towards the conduction band-edge.
  • the thickness of the n-dopant stack 120 - 1 is from about 1 ⁇ to about 10 ⁇ and ranges therebetween.
  • gate leakage, Vt shift and blocking of the dummy gate opening 110 - 1 may occur.
  • the annealing stack 125 may comprise a bottom cap titanium nitride (e) film and a top amorphous silicon film (f).
  • the thickness of the cap film (e) may be from about 5 ⁇ to about 30 ⁇ and ranges therebetween.
  • the thickness of the top amorphous silicon film may be from about 20 ⁇ to about 200 ⁇ and ranges therebetween.
  • the purpose of the stack is to block extrinsic oxygen from diffusing into the gate stack during the anneal. Oxygen in the gate stack increases Tiny.
  • an buffer layer for example TiN
  • Silicides can lead to surface roughing and gate leakage.
  • the structure shown in FIG. 4 b is annealed to drive the n and p dopants from their respective stacks 120 - 1 and 120 - 2 into the high-k material 115 of each FET region. Thereafter, the dopant and annealing stacks are removed to yield FIG. 5 .
  • the anneal may be from about 800 C to about 1300 C and ranges therebetween. If the temperature is too low the dopants will not diffuse sufficiently into the high-k material 115 and there will be no shift in the threshold voltage. If the temperature is too high, too much dopant moves close to the substrate 100 causing a change in crystallization of the high-k material which may lead to severe gate leakage.
  • the anneal may be performed by a soak anneal (several seconds), spike/rapid thermal anneal (RTA) which is a few seconds, or a laser anneal (LSA) which is milliseconds.
  • the anneal is performed in inert ambient such as nitrogen and/or argon.
  • the anneal moves the n-dopant, for example lanthanum, of the n-dopant stack 120 - 1 into the high k material to form an n-doped high-k material 131 .
  • the p-dopant preferably Aluminum
  • the p-dopant stack 120 - 2 also migrates into the high-k material 115 upon anneal to form a p-doped high-k material 132 .
  • the n-dopant of the n-dopant stack 120 - 1 is not able to migrate to the high k material in because it is blocked by the tri-layer p-dopant stack 120 - 2 .
  • the dopant may migrate toward the interfacial layer and higher-k material interface of the high-k material.
  • the dopant may form an oxide or silicate or both.
  • the dopant stacks 120 - 1 and 120 - 2 and the annealing stack 125 are removed. Removal is using a sequence of wets processes, typically involving ammonia based chemistry to remove silicon, peroxide and HCl and ammonia based chemistries (SC 1 , SC 2 ) to remove the TiN and the dopant materials. Choice of chemistry is motivated by efficiency in removing these materials while retaining high selectivity to the High-k material.
  • a shared work function metal 135 is formed in the openings of both FET regions followed by a bulk fill material 140 and planarization.
  • shared work function metal refers to the fact is the same work function metal is used for both the N-FET and the P-FET. This is in contrast to other methods in which the gate of the N-FET and the P-FET received different stacks of materials as the work function metals.
  • the shared work function metal 135 may be a stack of several layers of material, but in a preferred embodiment, the shared work function metal 135 may be a titanium nitride (TiN) layer which is deposited and thermally annealed to set the work-function.
  • the bulk fill 140 material is a relatively low resistance material compared to the WF metal.
  • An example of a bulk fill 140 material is tungsten which may have a bulk resistivity less than about 10 um-cm.
  • the bulk fill 140 material may include a wetting material between the shared WF metal 135 and the lower resistivity metal, for example tungsten.
  • the widths of various features of the replacement metal gate are referenced.
  • the dummy gate opening width 150 is indicated by the double arrow as is the doped gate oxide width 155 (in a high-k last embodiment), shared work function metal width 160 and the bulk fill width 165 .
  • a first important feature of the present invention is that the shared work-function metal 135 itself is only a few tens of Angstroms ( ⁇ ) thick.
  • the thickness of the WF metal 135 in an embodiment may be about 25-50 ⁇ , with a typical thickness about 30 ⁇ . Referring to FIG. 6 , a 30 ⁇ thickness of WF metal means that across the width of the gate opening 150 , the work function metal 135 width 160 would be a total of 6 nm (3 nm on each side). Thus, the remaining space in the gate opening may be used for the bulk fill 140 (in a high-k first embodiment).
  • a replacement metal gate process which does not have the shared WF metal 135 of the present invention would have one gate type with additional WF metals which consume a substantial amount of the opening width so that only about 0-10% space is available as the bulk fill width 165 .
  • a “high-k first” process with a shared work function metal 135 will allow for about 40-70% and ranges therebetween of space to be bulk fill width 165 .
  • replacement metal gate process which does not have the shared WF metal 135 of the present invention would have at least one gate type (P-FET, for example) only having about 30% space available as the bulk fill width 165 .
  • Similar calculations for a 14 nm gate opening width 150 allow for up to about 45% of the opening to be occupied by bulk fill width 165 in a “high-k last” replacement gate process having a shared work function metal 135 in accordance with the present invention.
  • a “high-k first” replacement gate process having a shared work function metal 135 in accordance to the present invention may have about 30% to about 65% and ranges therebetween of opening dedicated to bulk fill width 165 .
  • the effective work function of the N-FET is a combination of the inherent work function of the work function metal (TiN of the preferred embodiment) and the additional work function reduction caused by the electric dipole/charges due to the n-dopant (for example, lanthanum) diffused into the high k material.
  • Effective work functions of the N-FET have been demonstrated to be 5.5 to 4.35 eV and ranges therebetween.
  • the effective work function of the P-FET is a combination of the inherent work function of the work function metal (TiN of the preferred embodiment) and the additional work function increase caused by the electric dipole/charges due to the p-dopant (for example, aluminum) diffused into the high k material.
  • the present invention allows the use of a work function metal that has substantially higher work function because the NFET Vt can be reduced using a dipole-induced Vt shift that lanthanum provides. Therefore, a low NFET Vt that is needed for optimal device performance is achieved, but simultaneously improved PBTI through the use of a high work function metal is also achieved.

Landscapes

  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Materials Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)

Abstract

A integrated circuit including an n-doped high-k dielectric layer conformally within a first opening in a dielectric layer such that the n-doped high-k dielectric layer is in direct contact with a portion of a substrate exposed at a bottom of the first opening, a p-doped high-k dielectric layer conformally within a second opening in the dielectric layer such that the p-doped high-k dielectric layer is in direct contact with a portion of the substrate exposed at a bottom of the second opening, a shared work function metal conformally within the first opening and the second opening above and in direct contact with both the p-doped high-k dielectric layer and the n-doped high-k dielectric layer, and a bulk fill material above and in direct contact with the shared work function metal.

Description

    BACKGROUND OF THE INVENTION Field of the Invention
  • The present invention generally relates to Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) made on a semiconductor substrate. In particular, the invention relates to making MOSFETs having a single work-function metal for both the N-FET and the P-FET in a replacement metal gate structure.
    • Description of Related Art
  • In conjunction with Moore's law, gates of MOSFETs shrink with each technology node. In advanced MOSFETs, the gate may be made from a “replacement metal gate” (RMG) process which requires forming a gate opening in a dielectric layer and filling the gate opening with gate materials as opposed to patterning the gate materials and then surrounding them with a dielectric. Due to the number of work function materials required in current gates, the openings may be difficult to subsequently fill with the bulk material and may result in high gate resistances.
  • Attempts to create more room for a bulk fill material of a replacement metal gate structure included removing the stack of traditionally used WF metals from the sidewall of the opening. However, there are several drawbacks to work function metal recess: first, it requires several additional photolithography masks, patterning and etch steps; second, the wet etch and reactive ion etch (RIE) processes that are integral to this recess process alter the inherent work functions of the work function metals materials which remain at the bottom of the opening which leads to threshold voltage shifts; third, the repeatability and uniformity of the process is not very good, especially, with varying gate lengths of the transistors within each chip and across the entire wafer; and fourth, with the move to shorter gates (smaller vertical height of the opening) to reduce gate capacitance, the variability and control of work function recess process becomes worse. Thus, there is a need to create more space in the gate opening which provides substantial space for the bulk fill material to achieve low gate resistance while simultaneously providing that the correct work functions are set for N-FETs and P-FETs.
    • BRIEF SUMMARY OF THE INVENTION
  • The current invention is a novel structure to both simplify and improve the performance of the replacement metal gate stack for advanced node FETs, and the method of making the same. The current invention allows the correct work functions to be set for N-FETs and P-FETs, while simultaneously allowing substantial space in the gate opening for the bulk fill material which results in lower gate resistance. More specifically, doping of a high-k dielectric film of the gates allows both the N-FET and P-FET gates to share the same, thin, work function metal (single work function metal).
  • An object of the current invention is a method to form high-k metal gates of a N-FET and a P-FETs by a replacement metal gate process in advanced nodes The replacement metal gate process may be a “high-k first” or a “high-k last” (an embodiment illustrated by the figures) process. The node may be 14 nm and below such that the gate opening may be less than 20 nanometers wide.
  • A further object of the current invention is that the gates of the N-FET and the P-FET share the same, thin work function metal.
  • Another object of the current invention is that the gate oxide is doped. The dopants differ in the N-FET gate oxide and the P-FET gate oxide.
  • Yet a further object of the current invention is to provide a low resistance gate structure by increasing the amount of bulk fill material in the gate opening lined by the work function metal. Despite the gate opening being less than 20 nm, the bulk fill width may be 20-70% of the gate opening width.
  • An object of the present invention is to form an integrated circuit (IC) including a first gate of an N-FET and a second gate of a P-FET on the substrate wherein the first and second gates have a gate opening width of less than 20 nanonmeters. The IC also includes a work function metal lining both the first gate opening and the second gate opening. Furthermore, a high dielectric material is between the work function metal and the substrate wherein the high dielectric material is doped with an n-dopant in the first gate and is doped with a p-dopant in the second gate. Finally a bulk fill material fills a remainder of gate opening.
  • Another object of the current invention is a method of forming an N-FET metal gate and a P-FET metal gate sharing the same work function metal, the method comprising. The method provides a dielectric layer over a substrate wherein the dielectric layer has a first opening over an N-FET region of the substrate and a second opening over a P-FET region of the substrate. A high dielectric constant material is formed so as to be in contact with the substrate in the N-FET region and in the P-FET region. A work function metal lines the first and second openings which are subsequently a bulk fill material.
  • Other characteristics and advantages of the invention will become obvious in combination with the description of accompanying drawings, wherein the same number represents the same or similar parts in all figures.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a flow chart of an embodiment to create oppositely doped gates of FETs sharing the same work function (herein “WF”) metal;
  • FIG. 2 illustrates a substrate having an overlying dielectric material and openings in the dielectric material according to an embodiment of the present invention;
  • FIG. 3 illustrates a high dielectric constant material lining the openings according to an embodiment of the present invention;
  • FIG. 4a illustrates a p-dopant stack formed over the second region of the substrate according to an embodiment of the present invention;
  • FIG. 4b illustrates a n-dopant stack formed over the substrate according to an embodiment of the present invention;
  • FIG. 5 illustrates the substrate after annealing and removal of dopant and annealing stacks according to an another embodiment of the present invention; and
  • FIG. 6 illustrates oppositely doped high-k replacement metal gates having single work function metal according to an embodiment of the present invention.
    •  DETAILED DESCRIPTION OF THE INVENTION
  • The basic principle of the invention is a method forming oppositely doped high dielectric constant replacement metal gates which have the same work function (WF) metal stack. This is in contrast to normal methods in which work function tuning of an FET is achieved by varying the WF metal materials and thicknesses of materials. Work function tuning is a way to adjust threshold voltages of a device, thus creating two work function regions which, in turn creates two threshold voltage regions.
  • Referring to FIG. 1 a flow chart of steps to create a substrate in which the gates of oppositely doped FETs share the same WF metal according to an embodiment of the present invention is presented. In step 10, dummy gates over the N-FET and P-FET gate regions of the substrate are removed to leave gate openings (which can also be referred to as gate trenches). In step 15 a high dielectric constant material is formed in the gate openings. In step 20, p and n dopant stacks are formed as well as an annealing stack. In step 25 an anneal diffuses the respective dopants into each of the high dielectric constant materials to form first and second gate dielectric stacks. In step 30, following the anneal, the dopant stacks are removed. Next, in step 40 a shared, thin, work function metal is used in both the N-FET and the P-FET. Finally, either with or without a subsequent wetting layer, a bulk fill material is used to fill the opening to complete the gate structure. Then next figures will illustrate embodiments of the structures during the steps of FIG. 1.
  • Referring to FIG. 2, a substrate 100 has a two regions, first region 101 and second region 102. The substrate 100 may be a semiconductor or semiconductor on insulator substrate. The substrate 100 may be planar or may have fins. The first and second regions are oppositely doped regions which will become the N-FET and P-FETs. The substrate 100 has a dielectric layer or layers 105 over it. The dielectric layer has at least one dummy gate opening (110-1 and 110-2) over each of the first and second regions (101 and 102) of the substrate. At this point, the substrate 100 may have source and drain regions on either side of the openings 110-1 and 110-2, which, for simplification, have been omitted from FIG. 1. Likewise, the oppositely doped regions of the substrate 100 may be separated by an isolation (insulation) region which, for simplification, is also not illustrated. The dummy gate openings 110-1 and 110-2 were formed when a dummy gate material was removed. The dummy gate opening dimensions will vary with node, but in a 14 nm node example the openings may be from about 18 to 13 nm wide and ranges in between while the height may be 100 nm to 200 nm high over a buried oxide region in a semiconductor on insulator substrate embodiment.
  • Referring to FIG. 3, the high dielectric constant (herein “high-k”) material 115 is formed in the dummy gate openings 110-1 and 110-2. Here, high-k refers to dielectric constants greater than 4 (i.e. greater than the dielectric constant of SiO2). The high-k material 115 may include more than one layer, for example the high-k material may include both an interfacial layer next to the substrate and a higher k material above the interfacial layer. An example interfacial layer may be a silicon oxide or a silicon oxynitride. Examples of higher-k materials include hafnium oxide, hafnium silicate, zirconium oxide, zirconium silicate, aluminum oxide, titanium oxide, yttrium oxide among others.
  • As shown in FIG. 3, the high-k material lines the dummy gate openings 110-1/110-2, which is a “high-k” last embodiment of a replacement metal gate. However, the high-k material could have also been formed in a “high-k first process”. In such a case, the high-k material would only appear at the bottom of the dummy gate openings and not line the sidewalls. The “high-k last” process shown in FIG. 3 has the advantage that the high-k material is not damaged during dummy gate removal. The high-k material 115 may be formed by one or more of an atomic layer deposition, chemical vapor deposition, thermal oxidation, and others. The higher-k portion of the high-k material 115 may be from about 10 Å to about 25 Å thick, and ranges therebetween. The thickness range of the higher-k material is critical for proper subsequent dopant diffusion. Specifically, too thick of a higher-k material results in inadequate diffusion of dopant. Too thin of a higher-k material results in dopants in direct contact with interfacial layer and increase the Tiny (inverse of gate capacitance) or cause gate leakage issues.
  • Referring to the FIG. 4 series, first and second dopant layers will be formed. For the purposes of this example, the first region 101 of the substrate 100 may be an N-FET region and the second region 102 may be a P-FET region. In FIG. 4a , a p-dopant stack 120-2 may be initially formed everywhere and then removed over the N-FET region 101. Here, the p-dopant 120-2 may be a tri-layer, from bottom to top, of a (a) first titanium nitride layer, (b) aluminum (Al) or an aluminum containing layer, and a (c) second titanium nitride layer. The thickness of the first titanium nitride layer (120-2 a) is from about 5 Å to about 30 Å and ranges therebetween. The thickness of the aluminum containing layer (120-2 b) is from about 5 Å to about 30 Å ranges therebetween. The thickness of the second titanium nitride layer (120-2 c) is from about 5 Å to about 30 Å and ranges therebetween. If the p-dopant stack 120-2 is too thick the dummy gate opening 110-2 will be clogged. If there is too little or too much (depending on the specific layer) the threshold voltage (Vt) will shift too much or too little because the dopant will diffuse too much or too little. For example, if the second TiN layer (120-2 c) is too thin Lanthanum get into the PFET gate stack. Likewise, if these layers are too thin or too thick, gate leakage may increases due to suboptimal subsequent dopant diffusion. Specifically, too much dopant (for example, Aluminum) will reduce the dielectric constant of the high-k material which inturn increases gate leakage.
  • Referring to FIG. 4b , an n-dopant stack 120-1 may be formed everywhere on the substrate along with an annealing stack 125. Thus, in the N-FET region 101 of the substrate 100 there exists one dopant stack (the n-dopant stack 120-1) while in the P-FET region 102 of the substrate 100 there exist two dopant stacks (p-dopant 120-2 under the n-dopant 120-1). The n-dopant stack may be lanthanum (La) or a lanthanum containing film such as lanthanum oxide (La2O3), or some other rare earth dopant such as yttrium which shifts the effective work function to towards the conduction band-edge. The thickness of the n-dopant stack 120-1 is from about 1 Å to about 10 Å and ranges therebetween. Like the p-dopant, if the n-dopant layer is too thick or thin, gate leakage, Vt shift and blocking of the dummy gate opening 110-1 may occur.
  • Still referring to FIG. 4b , the annealing stack 125 may comprise a bottom cap titanium nitride (e) film and a top amorphous silicon film (f). The thickness of the cap film (e) may be from about 5 Å to about 30 Å and ranges therebetween. The thickness of the top amorphous silicon film may be from about 20 Å to about 200 Å and ranges therebetween. The purpose of the stack is to block extrinsic oxygen from diffusing into the gate stack during the anneal. Oxygen in the gate stack increases Tiny. When the oxygen blocking component of the anneal stack is silicon, an buffer layer (for example TiN) is formed between the silicon and the high-k material to prevent the silicon from forming a silicide with the high-k material. Silicides can lead to surface roughing and gate leakage.
  • The structure shown in FIG. 4b is annealed to drive the n and p dopants from their respective stacks 120-1 and 120-2 into the high-k material 115 of each FET region. Thereafter, the dopant and annealing stacks are removed to yield FIG. 5. The anneal may be from about 800 C to about 1300 C and ranges therebetween. If the temperature is too low the dopants will not diffuse sufficiently into the high-k material 115 and there will be no shift in the threshold voltage. If the temperature is too high, too much dopant moves close to the substrate 100 causing a change in crystallization of the high-k material which may lead to severe gate leakage. The anneal may be performed by a soak anneal (several seconds), spike/rapid thermal anneal (RTA) which is a few seconds, or a laser anneal (LSA) which is milliseconds. Typically, the anneal is performed in inert ambient such as nitrogen and/or argon.
  • Referring to the left side of FIG. 5 (the N-FET region 101 in this example), the anneal moves the n-dopant, for example lanthanum, of the n-dopant stack 120-1 into the high k material to form an n-doped high-k material 131. Turning to the right side of FIG. 5 (the P-FET region 102 in this example), the p-dopant, preferably Aluminum, of the p-dopant stack 120-2 also migrates into the high-k material 115 upon anneal to form a p-doped high-k material 132. However, in the P-FET region 102, the n-dopant of the n-dopant stack 120-1 is not able to migrate to the high k material in because it is blocked by the tri-layer p-dopant stack 120-2. In either case, the dopant may migrate toward the interfacial layer and higher-k material interface of the high-k material. There, the dopant may form an oxide or silicate or both.
  • Referring to FIGS. 4b and 5, after the anneal, the dopant stacks 120-1 and 120-2 and the annealing stack 125 are removed. Removal is using a sequence of wets processes, typically involving ammonia based chemistry to remove silicon, peroxide and HCl and ammonia based chemistries (SC1, SC2) to remove the TiN and the dopant materials. Choice of chemistry is motivated by efficiency in removing these materials while retaining high selectivity to the High-k material.
  • Referring to FIG. 6, a shared work function metal 135 is formed in the openings of both FET regions followed by a bulk fill material 140 and planarization. Here, “shared work function metal” refers to the fact is the same work function metal is used for both the N-FET and the P-FET. This is in contrast to other methods in which the gate of the N-FET and the P-FET received different stacks of materials as the work function metals. The shared work function metal 135 may be a stack of several layers of material, but in a preferred embodiment, the shared work function metal 135 may be a titanium nitride (TiN) layer which is deposited and thermally annealed to set the work-function. A typical thickness of such a film could be about 25 Å to about 50 Å and ranges therebetween. Work function setting anneal conditions and methods similar to those previously described in conjunction with dopant drive in. In preferred embodiment, the bulk fill 140 material is a relatively low resistance material compared to the WF metal. An example of a bulk fill 140 material is tungsten which may have a bulk resistivity less than about 10 um-cm. The bulk fill 140 material may include a wetting material between the shared WF metal 135 and the lower resistivity metal, for example tungsten.
  • Referring to the lower portion of FIG. 6, the widths of various features of the replacement metal gate are referenced. For example, the dummy gate opening width 150 is indicated by the double arrow as is the doped gate oxide width 155 (in a high-k last embodiment), shared work function metal width 160 and the bulk fill width 165.
  • A first important feature of the present invention is that the shared work-function metal 135 itself is only a few tens of Angstroms (Å) thick. As mentioned above, the thickness of the WF metal 135 in an embodiment may be about 25-50 Å, with a typical thickness about 30 Å. Referring to FIG. 6, a 30 Å thickness of WF metal means that across the width of the gate opening 150, the work function metal 135 width 160 would be a total of 6 nm (3 nm on each side). Thus, the remaining space in the gate opening may be used for the bulk fill 140 (in a high-k first embodiment). This reduction of WF metal to 6 nm, as opposed to over 10 nm expected for conventional methods, provides additional room for the bulk fill material, which can have a significant impact on device performance through reduction of RC time delay. For example, if the dummy gate opening width 150 is 17 nm, using a “high-k last” process as illustrated in FIGS. 2-6, the present invention would allow for about 20%-55% of the gate opening width 150 to be bulk fill width 165 in both the N-FET and P-FET gate (the range depending on doped oxide width 155 and work function metal width 160). In contrast, a replacement metal gate process which does not have the shared WF metal 135 of the present invention would have one gate type with additional WF metals which consume a substantial amount of the opening width so that only about 0-10% space is available as the bulk fill width 165. For the same gate opening width 150 of 17 nm, a “high-k first” process with a shared work function metal 135 will allow for about 40-70% and ranges therebetween of space to be bulk fill width 165. In contrast, replacement metal gate process which does not have the shared WF metal 135 of the present invention would have at least one gate type (P-FET, for example) only having about 30% space available as the bulk fill width 165. Similar calculations for a 14 nm gate opening width 150, allow for up to about 45% of the opening to be occupied by bulk fill width 165 in a “high-k last” replacement gate process having a shared work function metal 135 in accordance with the present invention. In a “high-k first” replacement gate process having a shared work function metal 135 in accordance to the present invention may have about 30% to about 65% and ranges therebetween of opening dedicated to bulk fill width 165.
  • A second important point of the present invention is that the effective work function of the N-FET is a combination of the inherent work function of the work function metal (TiN of the preferred embodiment) and the additional work function reduction caused by the electric dipole/charges due to the n-dopant (for example, lanthanum) diffused into the high k material. Effective work functions of the N-FET have been demonstrated to be 5.5 to 4.35 eV and ranges therebetween. Similarly, the effective work function of the P-FET is a combination of the inherent work function of the work function metal (TiN of the preferred embodiment) and the additional work function increase caused by the electric dipole/charges due to the p-dopant (for example, aluminum) diffused into the high k material.
  • Taken together, these two points mean that there is a substantial amount of room in the gate opening to fill the bulk metal while the work function is set by doping. The result is a lower resistance gate contact. Another advantage of the above described method is that only a single mask was needed to incorporate the dopants and set separate N-FET and P-FET work functions. In addition, there is a substantial benefit of PBTI (positive bias temperature instability) with the same Tiny (inverse of gate capacitance) and threshold voltage (Vt). PBTI directly depends on the work function of the NFET work function metal stack that is deposited on the NFET. The higher the work function the lower (i.e. better) the PBTI. The present invention allows the use of a work function metal that has substantially higher work function because the NFET Vt can be reduced using a dipole-induced Vt shift that lanthanum provides. Therefore, a low NFET Vt that is needed for optimal device performance is achieved, but simultaneously improved PBTI through the use of a high work function metal is also achieved.
  • While the present invention has been described with reference to what are presently considered to be the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. The scope of the following claims is to be accorded the broadcast interpretation so as to encompass all such modifications and equivalent structures and functions.

Claims (19)

We claim:
1. An integrated circuit comprising:
a first gate of an N-FET and a second gate of a P-FET on a substrate, wherein the first gate and the second gate each have a gate opening width of less than 20 nanometers;
a work function metal lining both the first gate opening and the second gate opening;
a high dielectric material between the work function metal and the substrate wherein the high dielectric material is doped with an n-dopant in the first gate and is doped with a p-dopant in the second gate; and
a bulk fill material filling a remainder of the gate opening.
2. The integrated circuit of claim 1, wherein the work function metal is a titanium nitride layer having a thickness from about 25 angstroms to about 50 angstroms.
3. The integrated circuit of claim 1, wherein the high dielectric material lines the sidewalls of the first gate opening and the second gate opening.
4. The integrated circuit of claim 1, wherein the high dielectric material includes an interfacial layer.
5. The integrated circuit of claim 1, wherein the p-dopant is aluminum.
6. The integrated circuit of claim 1, wherein the n-dopant is lanthanum.
7. The integrated circuit of claim 1, wherein the bulk fill material comprises tungsten.
8. The integrated circuit of claim 1, wherein the width of the bulk fill material is about 20 to about 70% of the width of the gate opening in each of the first and second gates.
9. The integrated circuit of claim 1, wherein a width of the bulk fill material is about 20 percent to about 50 percent of the width of the gate opening in each of the first gate and the second gate, and wherein the gate opening width is less than about 17 nanometers.
10. An integrated circuit having an N-FET metal gate and a P-FET metal gate sharing the same work function metal, the integrated circuit comprising:
an n-doped high dielectric constant material only along a bottom of a first opening in a dielectric layer, the n-doped high dielectric constant material is in direct contact with a portion of a substrate exposed at the bottom of the first opening;
a p-doped high dielectric constant material only along a bottom of a second opening in the dielectric layer, the p-doped high dielectric constant material is in direct contact with a portion of the substrate exposed at the bottom of the second opening;
a work function metal above and in direct contact with the p-doped high dielectric constant material and the n-doped high dielectric constant material; and
a bulk fill material directly on top of the work function metal, wherein a width of the bulk fill material comprises more than about 30% of the width of each of the first opening and the second opening, wherein the work function metal is less than about 40 angstroms thick, and wherein the width of the first opening and the second opening are each less than 20 nanometers.
11. The integrated circuit of claim 10, wherein the p-doped high dielectric constant material comprises aluminum.
12. The integrated circuit of claim 10, wherein the n-doped high dielectric constant material comprises lanthanum.
13. The integrated circuit of claim 10, wherein an effective work function of the N-FET metal gate is a combination of an inherent work function of the work function metal and the additional work function reduction caused by n-dopants of the n-doped high dielectric constant material, and an effective work function of the P-FET metal gate is a combination of an inherent work function of the work function metal and the additional work function increase caused by p-dopants of the p-doped high dielectric constant material.
14. A integrated circuit comprising:
an n-doped high-k dielectric layer conformally within a first opening in a dielectric layer such that the n-doped high-k dielectric layer is in direct contact with a portion of a substrate exposed at a bottom of the first opening;
a p-doped high-k dielectric layer conformally within a second opening in the dielectric layer such that the p-doped high-k dielectric layer is in direct contact with a portion of the substrate exposed at a bottom of the second opening;
a shared work function metal conformally within the first opening and the second opening above and in direct contact with both the p-doped high-k dielectric layer and the n-doped high-k dielectric layer; and
a bulk fill material above and in direct contact with the shared work function metal.
15. The integrated circuit of claim 14, wherein the first opening is in an N-FET region of the substrate and the second opening is in a P-FET region of the substrate.
16. The integrated circuit of claim 14, wherein the p-doped high-k dielectric layer comprises aluminum.
17. The integrated circuit of claim 14, wherein the n-doped high-k dielectric layer comprises lanthanum.
18. The integrated circuit of claim 14, wherein the shared work function metal comprises titanium nitride and the bulk fill material comprises tungsten.
19. The integrated circuit of claim 14, wherein a width of the first opening and the second opening are each less than 20 nanometers, a thickness of the shared work function metal is less than about 40 angstroms, and a width of the bulk fill material is more than 45% of the width of each of the first opening and the second opening.
US16/454,178 2014-03-06 2019-06-27 High k metal gate stack with single work-function metal Abandoned US20190318966A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/454,178 US20190318966A1 (en) 2014-03-06 2019-06-27 High k metal gate stack with single work-function metal

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/198,976 US9515164B2 (en) 2014-03-06 2014-03-06 Methods and structure to form high K metal gate stack with single work-function metal
US15/284,567 US10395993B2 (en) 2014-03-06 2016-10-04 Methods and structure to form high K metal gate stack with single work-function metal
US16/454,178 US20190318966A1 (en) 2014-03-06 2019-06-27 High k metal gate stack with single work-function metal

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US15/284,567 Division US10395993B2 (en) 2014-03-06 2016-10-04 Methods and structure to form high K metal gate stack with single work-function metal

Publications (1)

Publication Number Publication Date
US20190318966A1 true US20190318966A1 (en) 2019-10-17

Family

ID=54018143

Family Applications (3)

Application Number Title Priority Date Filing Date
US14/198,976 Active US9515164B2 (en) 2014-03-06 2014-03-06 Methods and structure to form high K metal gate stack with single work-function metal
US15/284,567 Active 2035-01-18 US10395993B2 (en) 2014-03-06 2016-10-04 Methods and structure to form high K metal gate stack with single work-function metal
US16/454,178 Abandoned US20190318966A1 (en) 2014-03-06 2019-06-27 High k metal gate stack with single work-function metal

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US14/198,976 Active US9515164B2 (en) 2014-03-06 2014-03-06 Methods and structure to form high K metal gate stack with single work-function metal
US15/284,567 Active 2035-01-18 US10395993B2 (en) 2014-03-06 2016-10-04 Methods and structure to form high K metal gate stack with single work-function metal

Country Status (1)

Country Link
US (3) US9515164B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12062702B2 (en) 2020-12-30 2024-08-13 Changxin Memory Technologies, Inc. Method for manufacturing semiconductor structure and semiconductor structure

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9515164B2 (en) 2014-03-06 2016-12-06 International Business Machines Corporation Methods and structure to form high K metal gate stack with single work-function metal
KR102162733B1 (en) * 2014-05-29 2020-10-07 에스케이하이닉스 주식회사 Dual work function bruied gate type transistor, method for manufacturing the same and electronic device having the same
KR102271003B1 (en) * 2014-07-11 2021-06-29 삼성전자주식회사 Fabricating method of Semiconductor device
US9349652B1 (en) * 2014-12-12 2016-05-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor device with different threshold voltages
US9685532B2 (en) 2015-03-24 2017-06-20 International Business Machines Corporation Replacement metal gate structures
US10170477B2 (en) 2015-11-06 2019-01-01 International Business Machines Corporation Forming MOSFET structures with work function modification
CN106024893B (en) * 2016-05-30 2019-03-19 上海华力微电子有限公司 High-K metal gate device and preparation method thereof
US20170373142A1 (en) * 2016-06-23 2017-12-28 Littelfuse, Inc. Semiconductor device having side-diffused trench plug
US11114347B2 (en) * 2017-06-30 2021-09-07 Taiwan Semiconductor Manufacturing Co., Ltd. Self-protective layer formed on high-k dielectric layers with different materials
US10665450B2 (en) * 2017-08-18 2020-05-26 Applied Materials, Inc. Methods and apparatus for doping engineering and threshold voltage tuning by integrated deposition of titanium nitride and aluminum films
US10176997B1 (en) 2017-09-11 2019-01-08 International Business Machines Corporation Direct gate patterning for vertical transport field effect transistor
US10559676B2 (en) 2018-04-23 2020-02-11 International Business Machines Corporation Vertical FET with differential top spacer
US11201227B2 (en) * 2018-04-27 2021-12-14 Taiwan Semiconductor Manufacturing Co., Ltd. Gate structure with barrier layer and method for forming the same
US11302794B2 (en) 2020-03-17 2022-04-12 International Business Machines Corporation FinFET with dual work function metal
US11244872B2 (en) 2020-04-15 2022-02-08 International Business Machines Corporation FinFET complementary metal-oxide-semiconductor (CMOS) devices
CN114695097B (en) * 2020-12-30 2025-04-04 长鑫存储技术有限公司 Semiconductor structure manufacturing method and semiconductor structure
US12100595B2 (en) * 2021-02-08 2024-09-24 Applied Materials, Inc. Amorphous silicon-based scavenging and sealing EOT
TW202301484A (en) * 2021-05-28 2023-01-01 美商應用材料股份有限公司 Amorphous silicon-based scavenging and sealing eot
US12094937B2 (en) 2021-09-22 2024-09-17 International Business Machines Corporation Stacked field effect transistor devices with replacement gate
US12501698B2 (en) 2022-12-22 2025-12-16 International Business Machines Corporation Stacked transistors having self aligned backside contact with backside replacement metal gate

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060124974A1 (en) * 2004-12-15 2006-06-15 International Business Machines Corporation Structure and method to generate local mechanical gate stress for mosfet channel mobility modification
US20130043592A1 (en) * 2011-08-19 2013-02-21 Globalfoundries Inc. Methods of Forming a Replacement Gate Comprised of Silicon and a Device Including Same
US20130168773A1 (en) * 2011-12-29 2013-07-04 Globalfoundries Inc. High-K Metal Gate Electrode Structure Formed by Removing a Work Function on Sidewalls in Replacement Gate Technology
US20140197480A1 (en) * 2013-01-11 2014-07-17 Semiconductor Manufacturing International (Shanghai) Corporation Semiconductor structure having common gate and fabrication method thereof
US20150279745A1 (en) * 2012-11-30 2015-10-01 Institute of Microelectronics, Chinese Academy of Sciences Methods for manufacturing semiconductor devices

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6436774B1 (en) * 2001-01-26 2002-08-20 Chartered Semiconductor Manufacturing Ltd. Method for forming variable-K gate dielectric
US7838908B2 (en) 2009-01-26 2010-11-23 International Business Machines Corporation Semiconductor device having dual metal gates and method of manufacture
US8309419B2 (en) 2009-02-04 2012-11-13 Freescale Semiconductor, Inc. CMOS integration with metal gate and doped high-K oxides
DE102009031155B4 (en) 2009-06-30 2012-02-23 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG Adjusting a threshold voltage for complex transistors by diffusing a metal species into the gate dielectric prior to the gate patterning
US8890260B2 (en) 2009-09-04 2014-11-18 Taiwan Semiconductor Manufacturing Company, Ltd. Polysilicon design for replacement gate technology
US8378498B2 (en) 2010-09-09 2013-02-19 International Business Machines Corporation Chip assembly with a coreless substrate employing a patterned adhesive layer
US8653602B2 (en) 2010-09-11 2014-02-18 International Business Machines Corporation Transistor having replacement metal gate and process for fabricating the same
US8946006B2 (en) 2010-10-28 2015-02-03 International Business Machines Corporation Replacement gate MOSFET with raised source and drain
US8546211B2 (en) 2010-11-17 2013-10-01 International Business Machines Corporation Replacement gate having work function at valence band edge
US8420473B2 (en) * 2010-12-06 2013-04-16 International Business Machines Corporation Replacement gate devices with barrier metal for simultaneous processing
US8581351B2 (en) 2011-01-14 2013-11-12 International Business Machines Corporation Replacement gate with reduced gate leakage current
US8450946B1 (en) 2011-02-07 2013-05-28 Universal Lighting Technologies, Inc. Zone addressing circuit for an electronic ballast
US20120280288A1 (en) 2011-05-04 2012-11-08 International Business Machines Corporation Inversion thickness reduction in high-k gate stacks formed by replacement gate processes
US20130049123A1 (en) 2011-08-23 2013-02-28 Globalfoundries Inc. Semiconductor Device with DRAM Word Lines and Gate Electrodes in Non-Memory Regions of the Device Comprised of a Metal, and Methods of Making Same
US20130082332A1 (en) 2011-09-30 2013-04-04 Globalfoundries Singapore Pte. Ltd. Method for forming n-type and p-type metal-oxide-semiconductor gates separately
US20130187236A1 (en) 2012-01-20 2013-07-25 Globalfoundries Inc. Methods of Forming Replacement Gate Structures for Semiconductor Devices
US20130256802A1 (en) 2012-03-27 2013-10-03 International Business Machines Corporation Replacement Gate With Reduced Gate Leakage Current
US8987126B2 (en) * 2012-05-09 2015-03-24 GlobalFoundries, Inc. Integrated circuit and method for fabricating the same having a replacement gate structure
US9029959B2 (en) * 2012-06-29 2015-05-12 International Business Machines Corporation Composite high-k gate dielectric stack for reducing gate leakage
US8865581B2 (en) * 2012-10-19 2014-10-21 Tokyo Electron Limited Hybrid gate last integration scheme for multi-layer high-k gate stacks
US9040404B2 (en) 2012-11-14 2015-05-26 International Business Machines Corporation Replacement metal gate structure for CMOS device
US9105497B2 (en) * 2013-09-04 2015-08-11 Globalfoundries Inc. Methods of forming gate structures for transistor devices for CMOS applications
US9515164B2 (en) 2014-03-06 2016-12-06 International Business Machines Corporation Methods and structure to form high K metal gate stack with single work-function metal

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060124974A1 (en) * 2004-12-15 2006-06-15 International Business Machines Corporation Structure and method to generate local mechanical gate stress for mosfet channel mobility modification
US20130043592A1 (en) * 2011-08-19 2013-02-21 Globalfoundries Inc. Methods of Forming a Replacement Gate Comprised of Silicon and a Device Including Same
US20130168773A1 (en) * 2011-12-29 2013-07-04 Globalfoundries Inc. High-K Metal Gate Electrode Structure Formed by Removing a Work Function on Sidewalls in Replacement Gate Technology
US20150279745A1 (en) * 2012-11-30 2015-10-01 Institute of Microelectronics, Chinese Academy of Sciences Methods for manufacturing semiconductor devices
US20140197480A1 (en) * 2013-01-11 2014-07-17 Semiconductor Manufacturing International (Shanghai) Corporation Semiconductor structure having common gate and fabrication method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12062702B2 (en) 2020-12-30 2024-08-13 Changxin Memory Technologies, Inc. Method for manufacturing semiconductor structure and semiconductor structure

Also Published As

Publication number Publication date
US20150255463A1 (en) 2015-09-10
US10395993B2 (en) 2019-08-27
US20170025315A1 (en) 2017-01-26
US9515164B2 (en) 2016-12-06

Similar Documents

Publication Publication Date Title
US10395993B2 (en) Methods and structure to form high K metal gate stack with single work-function metal
CN101661883B (en) Manufacturing method of semiconductor element
US9082853B2 (en) Bulk finFET with punchthrough stopper region and method of fabrication
US7902599B2 (en) Integrated circuit having long and short channel metal gate devices and method of manufacture
US8193586B2 (en) Sealing structure for high-K metal gate
US20220310595A1 (en) Gate structure with additional oxide layer and method for manufacturing the same
US7655516B2 (en) Semiconductor device and method of manufacturing the same
US20150035073A1 (en) Enabling enhanced reliability and mobility for replacement gate planar and finfet structures
US20130256802A1 (en) Replacement Gate With Reduced Gate Leakage Current
US20070052037A1 (en) Semiconductor devices and methods of manufacture thereof
US9343372B1 (en) Metal stack for reduced gate resistance
US9059315B2 (en) Concurrently forming nFET and pFET gate dielectric layers
US9196706B2 (en) Method for manufacturing P-type MOSFET
US20200135589A1 (en) Method of metal gate formation and structures formed by the same
US11430652B2 (en) Controlling threshold voltages through blocking layers
US20140015063A1 (en) Method for Forming Gate Structure, Method for Forming Semiconductor Device, and Semiconductor Device
JP2013532382A (en) High voltage transistor with thinned drain
US20160247917A1 (en) Semiconductor device
US20240371958A1 (en) Field effect transistor with fin isolation structure and method
US20120313158A1 (en) Semiconductor structure and method for manufacturing the same
US20220406909A1 (en) Field effect transistor with dual silicide and method
US8420489B2 (en) High-performance semiconductor device and method of manufacturing the same
US9029225B2 (en) Method for manufacturing N-type MOSFET
US8803254B2 (en) Methods of forming replacement gate structures for NFET semiconductor devices and devices having such gate structures
CN110610855B (en) Method for manufacturing semiconductor device

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ANDO, TAKASHI;KANNAN, BALAJI;KRISHNAN, SIDDARTH;AND OTHERS;SIGNING DATES FROM 20140220 TO 20140304;REEL/FRAME:049606/0637

STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

AS Assignment

Owner name: TESSERA, INC., CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:051489/0324

Effective date: 20191227

AS Assignment

Owner name: BANK OF AMERICA, N.A., NORTH CAROLINA

Free format text: SECURITY INTEREST;ASSIGNORS:ROVI SOLUTIONS CORPORATION;ROVI TECHNOLOGIES CORPORATION;ROVI GUIDES, INC.;AND OTHERS;REEL/FRAME:053468/0001

Effective date: 20200601

AS Assignment

Owner name: TESSERA, INC., CALIFORNIA

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE 16/161,111 PREVIOUSLY RECORDED ON REEL 051489 FRAME 0324. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:053389/0252

Effective date: 20191227

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: FINAL REJECTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: FINAL REJECTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

AS Assignment

Owner name: TESSERA LLC, CALIFORNIA

Free format text: CERTIFICATE OF CONVERSION & CHANGE OF NAME;ASSIGNOR:TESSERA, INC.;REEL/FRAME:060940/0552

Effective date: 20211001

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: FINAL REJECTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: FINAL REJECTION MAILED

AS Assignment

Owner name: ADEIA SEMICONDUCTOR SOLUTIONS LLC, CALIFORNIA

Free format text: CHANGE OF NAME;ASSIGNOR:TESSERA LLC;REEL/FRAME:069067/0410

Effective date: 20220815

STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION