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US20190051632A1 - Fan-out wafer level multilayer wiring package structure - Google Patents

Fan-out wafer level multilayer wiring package structure Download PDF

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Publication number
US20190051632A1
US20190051632A1 US16/044,496 US201816044496A US2019051632A1 US 20190051632 A1 US20190051632 A1 US 20190051632A1 US 201816044496 A US201816044496 A US 201816044496A US 2019051632 A1 US2019051632 A1 US 2019051632A1
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Prior art keywords
interposer
multilayer
semiconductor chip
vertical interconnection
interconnection
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US10580755B2 (en
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Yong Ji
Rongzhen Zhang
Chongchong Mao
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CETC 58 Research Institute
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    • H10W72/20—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0655—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H10W70/05—
    • H10W70/611—
    • H10W70/635—
    • H10W70/65—
    • H10W70/685—
    • H10W72/073—
    • H10W72/30—
    • H10W74/019—
    • H10W90/00—
    • H10W90/401—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H10W74/117—
    • H10W90/701—
    • H10W90/734—

Definitions

  • the invention belongs to the field of the packaging technology for integrated circuits, specifically relating to fan-out wafer level package.
  • Fan-out wafer-level packaging technology as a solution to the miniaturization and low-cost application of electronic system components, is currently developing into a major advanced packaging process with high integration flexibility.
  • This technology can reduce weight by more than 40% without LTCC substrate; and wafer level integration can achieve micron-scale manufacturing precision, improve production efficiency, and meet the urgent needs of modern electronic equipment systems for miniaturization, low cost, and high integration.
  • the key process technologies for fan-out wafer level packaging are solder bump fabrication and redistribution layer (RDL) technology.
  • RDL technology is used to realize the signal interconnection between semiconductor chips and the transfer of signal terminals (I/O).
  • I/O signal terminals
  • the RDL technology is limited by the number of wiring layers, making it difficult to meet the more complex design of the fan-out wafer level package.
  • the invention provides fan-out wafer level multi-layer wiring package structure and a method for preparing the package structure, which are used to solve the problem that the fan-out wafer level package existing in the prior art is difficult to meet the complicated interconnection relationship.
  • the package structure comprises a plurality of semiconductor chips, a multilayer interposer, a vertical interconnection interposer, molding materials and a redistribution layer;
  • the back surface of the semiconductor chip is bonded to the back surface of the multilayer interposer with the bonding material, and is placed on the same horizontal plane with the vertical interconnection interposer and packaged as a whole with the molding material, and the redistribution layer is provided on the surface of the structure;
  • the semiconductor chip, the multilayer interposer, the conductive material of the vertical interconnection interproser and the solder ball are connected by the conductive metal layer of the redistribution layer to achieve the signal interconnection between the semiconductor chip and the multilayer interposer and the I/O signal transfer of the semiconductor chip.
  • the multilayer interposer is manufactured by using the CMOS process according to the electrical interconnection design requirements of the system.
  • the multilayer interposer combines with the semiconductor chip, then the combination and the vertical interconnection interposer are integrated after being placed on the same horizontal plane, to achieve the electrical interconnection between the semiconductor chip or the multilayer interposer and the conductive material of the vertical interconnection interposer and the solder ball by rewiring the conductive metal.
  • the vertical interconnection interposer is obtained by cutting the corresponding size of the vertical interconnection interposer wafers fixed with the prefabricated through-hole pitch according to the electrical interconnection design requirements between the semiconductor chips.
  • a method for manufacturing fan-out wafer level package structure wherein: the wafer level CMOS process is used to fabricate the multilayer interposer according to the signal interconnection design requirements between the semiconductor chips; the vertical interconnection interposer wafers fixed with the prefabricated through-hole pitch are cut with the wafer saw to obtain the corresponding size of the vertical interconnection interposer according to the signal interconnection design requirements between the semiconductor chips and the specific requirements for the number of signal leading-out terminals of the system; the back surface of the semiconductor chip is bonded to the back surface of the multilayer interposer by using the bonding process with the bonding material; the bonded semiconductor chip and multilayer interposer and the vertical interconnection interposer are temporarily bonded on a carrier, and the front surface of the semiconductor chip faces away from the carrier and the vertical interconnection interposer is placed on the side of the semiconductor chip and the multilayer interposer; the semiconductor chip, the multilayer interposer and the vertical interconnection interposer on the carrier are packaged, and then the carrier is removed; the redistribution layer (
  • the multilayer interposer is provided to increase the number of wiring layers of the fan-out wafer level package, making up for the defect of the wafer level package limited by the number of redistribution layers, which can meet the development requirements for high-density and high-complexity wiring of current microelectronic systems and can be used for microsystem packaging with high complexity.
  • the signal interconnection between the leading-out terminal (I/O) of the semiconductor chip and the multilayer interposer is realized by the vertical interconnection interposer at the side, thus simplifying the interconnection mode.
  • the vertical interconnection interposer wafers fixed with the prefabricated through-hole pitch are cut to obtain the corresponding vertical interconnection interposer according to the signal interconnection design requirements between the semiconductor chips, thus simplifying and fixing the process and improving the packaging efficiency.
  • FIG. 1 is a multilayer interposer wafer of fan-out wafer level multilayer wiring package structure according to the invention
  • FIG. 2 is a vertical interconnection interposer wafer fixed with the prefabricated through-hole pitch of fan-out wafer level multilayer wiring package structure according to the invention
  • FIG. 3 is a schematic diagram showing the integration of the bonded semiconductor chip and multilayer interposer and the vertical interconnection interposer of fan-out wafer level multilayer wiring package structure according to the invention
  • FIG. 4 is a schematic diagram of fan-out wafer level multilayer wiring package structure according to the invention.
  • 1 semiconductor chip
  • 2 multilayer interposer
  • 3 redistribution layer
  • 4 molding material
  • 5 vertical interconnection interposer
  • 6 wiring layer of multilayer interposer
  • 7 bonding material
  • 8 solder ball
  • 9 carrier.
  • fan-out wafer level multilayer wiring package structure wherein the package structure comprises a plurality of semiconductor chips 1 , a multilayer interposer 2 , a vertical interconnection interposer 5 , molding materials 4 and a redistribution layer 3 ;
  • the back surface of the semiconductor chip 1 is bonded to the back surface of the multilayer interposer 2 with the bonding material 7 , and is placed on the same horizontal plane as the vertical interconnection interposer 5 and packaged as a whole with the molding material 4 , and the redistribution layer 3 is provided on the surface of the structure;
  • the signal I/O of the semiconductor chip 1 is connected to the vertical interconnection interposer 5 through the upper surface RDL, and then connected to the multilayer interposer 2 through the conductive material of the vertical interconnection interposer 5 and the lower surface RDL, or directly connected to the bottom solder ball 8 through the conductive material of the vertical interconnection interposer 2 .
  • the package structure realizes an increase in the number of wiring layers by the multilayer interposer 2 ; the multilayer interposer 2 is manufactured by using the CMOS process according to the electrical interconnection design requirements of the system.
  • the multilayer interposer 2 combines with the semiconductor chip 1 , then the combination and the vertical interconnection interposer 5 are integrated after being placed on the same horizontal plane, to achieve the electrical interconnection between the semiconductor chip 1 or the multilayer interposer 2 and the conductive material of the vertical interconnection interposer 5 and the solder ball 8 by rewiring the conductive metal.
  • the molding material 4 is one of the filler material, but not limited in the filler material.
  • the vertical interconnection interposer 5 is obtained by cutting the corresponding size of the vertical interconnection interposer 5 wafers fixed with the prefabricated through-hole pitch according to the electrical interconnection design requirements between the semiconductor chips 1 .
  • a method for manufacturing fan-out wafer level package structure including the following steps:
  • the wafer level CMOS process is used to fabricate the multilayer interposer 2 according to the signal interconnection design requirements between the semiconductor chips 1 ;
  • the vertical interconnection interposer 5 wafers fixed with the prefabricated through-hole pitch are cut with the wafer saw to obtain the corresponding size of the vertical interconnection interposer 5 according to the signal interconnection design requirements between the semiconductor chips 1 and the specific requirements for the number of signal leading-out terminals of the system;
  • the bonded semiconductor chip 1 and multilayer interposer 2 and the vertical interconnection interposer 5 are temporarily mounted on a carrier 9 , and the front surface of the semiconductor chip 1 faces away from the carrier 9 and the vertical interconnection interposer 5 is placed on the side of the semiconductor chip 1 and the multilayer interposer 2 (using the method of lateral vertical interconnect interposer);
  • the redistribution layer (RDL) 3 is provided on the surface of the above structure, and the signal I/O of the semiconductor chip 1 is connected to the vertical interconnection interposer 5 through the upper surface RDL, and then connected to the multilayer interposer 2 through the conductive material of the vertical interconnection interposer 5 and the lower surface RDL, or directly connected to the bottom solder ball 8 through the conductive material of the vertical interconnection interposer 5 .
  • the present invention increases the number of wiring layers of the fan-out wafer level package, making up for the defect of the wafer level package limited by the number of RDL wiring layers, which can meet the development requirements for high-density and high-complexity wiring of current microelectronic systems and can be used for microsystem packaging with high complexity.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A fan-out wafer level multilayer wiring package structure, wherein the package structure comprises a plurality of semiconductor chips, a multilayer interposer, a vertical interconnection interposer, molding materials and a redistribution layer; the back surface of the semiconductor chip is bonded to the back surface of the multilayer wiring interposer with the bonding material, and is placed on the same horizontal plane as the vertical interconnection interposer and packaged as a whole with the molding material, the redistribution layer is provided on the surface of the structure; the semiconductor chip, the multilayer interposer, the conductive material of the vertical interconnection interproser and the solder ball are connected by the conductive metal layer of the redistribution layer to achieve the signal interconnection between the semiconductor chip and the multilayer interposer and the I/O signal transfer of the semiconductor chip.

Description

    BACKGROUND OF THE INVENTION 1. Field of the Invention
  • The invention belongs to the field of the packaging technology for integrated circuits, specifically relating to fan-out wafer level package.
    • 2. Description of the Related Art
  • Fan-out wafer-level packaging technology, as a solution to the miniaturization and low-cost application of electronic system components, is currently developing into a major advanced packaging process with high integration flexibility. This technology can reduce weight by more than 40% without LTCC substrate; and wafer level integration can achieve micron-scale manufacturing precision, improve production efficiency, and meet the urgent needs of modern electronic equipment systems for miniaturization, low cost, and high integration. The key process technologies for fan-out wafer level packaging are solder bump fabrication and redistribution layer (RDL) technology. Among them, RDL technology is used to realize the signal interconnection between semiconductor chips and the transfer of signal terminals (I/O). As electronic systems become more powerful, their wiring and mounting density are also increasing. However, the RDL technology is limited by the number of wiring layers, making it difficult to meet the more complex design of the fan-out wafer level package.
  • In order to meet the wiring design requirements of current microelectronic systems, it is urgent to develop fan-out wafer level multilayer wiring package structure.
    • SUMMARY OF THE INVENTION
  • The invention provides fan-out wafer level multi-layer wiring package structure and a method for preparing the package structure, which are used to solve the problem that the fan-out wafer level package existing in the prior art is difficult to meet the complicated interconnection relationship.
  • fan-out wafer level multilayer wiring package structure, wherein the package structure comprises a plurality of semiconductor chips, a multilayer interposer, a vertical interconnection interposer, molding materials and a redistribution layer;
  • the back surface of the semiconductor chip is bonded to the back surface of the multilayer interposer with the bonding material, and is placed on the same horizontal plane with the vertical interconnection interposer and packaged as a whole with the molding material, and the redistribution layer is provided on the surface of the structure;
  • the semiconductor chip, the multilayer interposer, the conductive material of the vertical interconnection interproser and the solder ball are connected by the conductive metal layer of the redistribution layer to achieve the signal interconnection between the semiconductor chip and the multilayer interposer and the I/O signal transfer of the semiconductor chip.
  • Furthermore, wherein the package structure realizes an increase in the number of wiring layers by the multilayer interposer; the multilayer interposer is manufactured by using the CMOS process according to the electrical interconnection design requirements of the system.
  • Furthermore, wherein the multilayer interposer combines with the semiconductor chip, then the combination and the vertical interconnection interposer are integrated after being placed on the same horizontal plane, to achieve the electrical interconnection between the semiconductor chip or the multilayer interposer and the conductive material of the vertical interconnection interposer and the solder ball by rewiring the conductive metal.
  • Furthermore, wherein the vertical interconnection interposer is obtained by cutting the corresponding size of the vertical interconnection interposer wafers fixed with the prefabricated through-hole pitch according to the electrical interconnection design requirements between the semiconductor chips.
  • A method for manufacturing fan-out wafer level package structure, wherein: the wafer level CMOS process is used to fabricate the multilayer interposer according to the signal interconnection design requirements between the semiconductor chips; the vertical interconnection interposer wafers fixed with the prefabricated through-hole pitch are cut with the wafer saw to obtain the corresponding size of the vertical interconnection interposer according to the signal interconnection design requirements between the semiconductor chips and the specific requirements for the number of signal leading-out terminals of the system; the back surface of the semiconductor chip is bonded to the back surface of the multilayer interposer by using the bonding process with the bonding material; the bonded semiconductor chip and multilayer interposer and the vertical interconnection interposer are temporarily bonded on a carrier, and the front surface of the semiconductor chip faces away from the carrier and the vertical interconnection interposer is placed on the side of the semiconductor chip and the multilayer interposer; the semiconductor chip, the multilayer interposer and the vertical interconnection interposer on the carrier are packaged, and then the carrier is removed; the redistribution layer (RDL) is provided on the surface of the above structure, and the signal I/O of the semiconductor chip is connected to the vertical interconnection interposer through the upper surface RDL, and then connected to the multilayer interposer through the conductive material of the vertical interconnection interposer and the lower surface RDL, or directly connected to the bottom solder ball through the conductive material of the vertical interconnection interposer.
  • According to the signal interconnection design requirements between the semiconductor chips, the multilayer interposer is provided to increase the number of wiring layers of the fan-out wafer level package, making up for the defect of the wafer level package limited by the number of redistribution layers, which can meet the development requirements for high-density and high-complexity wiring of current microelectronic systems and can be used for microsystem packaging with high complexity. The signal interconnection between the leading-out terminal (I/O) of the semiconductor chip and the multilayer interposer is realized by the vertical interconnection interposer at the side, thus simplifying the interconnection mode. The vertical interconnection interposer wafers fixed with the prefabricated through-hole pitch are cut to obtain the corresponding vertical interconnection interposer according to the signal interconnection design requirements between the semiconductor chips, thus simplifying and fixing the process and improving the packaging efficiency.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without paying for inventive labor.
  • FIG. 1 is a multilayer interposer wafer of fan-out wafer level multilayer wiring package structure according to the invention;
  • FIG. 2 is a vertical interconnection interposer wafer fixed with the prefabricated through-hole pitch of fan-out wafer level multilayer wiring package structure according to the invention;
  • FIG. 3 is a schematic diagram showing the integration of the bonded semiconductor chip and multilayer interposer and the vertical interconnection interposer of fan-out wafer level multilayer wiring package structure according to the invention;
  • FIG. 4 is a schematic diagram of fan-out wafer level multilayer wiring package structure according to the invention.
    •
  • Wherein, 1—semiconductor chip, 2—multilayer interposer, 3—redistribution layer, 4—molding material, 5—vertical interconnection interposer, 6—wiring layer of multilayer interposer, 7—bonding material, 8—solder ball, 9—carrier.
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail below with reference to the accompanying drawings. It is apparent that the described embodiments are only a part of the embodiments of the invention, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.
  • The present invention is further described as follows with reference to the drawings.
  • As shown in FIG. 3, fan-out wafer level multilayer wiring package structure, wherein the package structure comprises a plurality of semiconductor chips 1, a multilayer interposer 2, a vertical interconnection interposer 5, molding materials 4 and a redistribution layer 3;
  • the back surface of the semiconductor chip 1 is bonded to the back surface of the multilayer interposer 2 with the bonding material 7, and is placed on the same horizontal plane as the vertical interconnection interposer 5 and packaged as a whole with the molding material 4, and the redistribution layer 3 is provided on the surface of the structure;
  • the signal I/O of the semiconductor chip 1 is connected to the vertical interconnection interposer 5 through the upper surface RDL, and then connected to the multilayer interposer 2 through the conductive material of the vertical interconnection interposer 5 and the lower surface RDL, or directly connected to the bottom solder ball 8 through the conductive material of the vertical interconnection interposer 2.
  • Furthermore, the package structure realizes an increase in the number of wiring layers by the multilayer interposer 2; the multilayer interposer 2 is manufactured by using the CMOS process according to the electrical interconnection design requirements of the system.
  • Furthermore, the multilayer interposer 2 combines with the semiconductor chip 1, then the combination and the vertical interconnection interposer 5 are integrated after being placed on the same horizontal plane, to achieve the electrical interconnection between the semiconductor chip 1 or the multilayer interposer 2 and the conductive material of the vertical interconnection interposer 5 and the solder ball 8 by rewiring the conductive metal.
  • Furthermore, the molding material 4 is one of the filler material, but not limited in the filler material.
  • Furthermore, the vertical interconnection interposer 5 is obtained by cutting the corresponding size of the vertical interconnection interposer 5 wafers fixed with the prefabricated through-hole pitch according to the electrical interconnection design requirements between the semiconductor chips 1.
  • A method for manufacturing fan-out wafer level package structure, including the following steps:
  • (1) the wafer level CMOS process is used to fabricate the multilayer interposer 2 according to the signal interconnection design requirements between the semiconductor chips 1;
  • (2) Using a high-efficiency technology, see the FIG. 2, the vertical interconnection interposer 5 wafers fixed with the prefabricated through-hole pitch are cut with the wafer saw to obtain the corresponding size of the vertical interconnection interposer 5 according to the signal interconnection design requirements between the semiconductor chips 1 and the specific requirements for the number of signal leading-out terminals of the system;
  • (3) the back surface of the semiconductor chip 1 is bonded to the back surface of the multilayer interposer 2 by using the bonding process with the bonding material 7;
  • (4) the bonded semiconductor chip 1 and multilayer interposer 2 and the vertical interconnection interposer 5 are temporarily mounted on a carrier 9, and the front surface of the semiconductor chip 1 faces away from the carrier 9 and the vertical interconnection interposer 5 is placed on the side of the semiconductor chip 1 and the multilayer interposer 2 (using the method of lateral vertical interconnect interposer);
  • (5) the semiconductor chip 1, the multilayer interposer 2 and the vertical interconnection interposer 5 on the carrier 9 are packaged, and then the carrier 9 is removed;
  • (6) the redistribution layer (RDL) 3 is provided on the surface of the above structure, and the signal I/O of the semiconductor chip 1 is connected to the vertical interconnection interposer 5 through the upper surface RDL, and then connected to the multilayer interposer 2 through the conductive material of the vertical interconnection interposer 5 and the lower surface RDL, or directly connected to the bottom solder ball 8 through the conductive material of the vertical interconnection interposer 5. The present invention increases the number of wiring layers of the fan-out wafer level package, making up for the defect of the wafer level package limited by the number of RDL wiring layers, which can meet the development requirements for high-density and high-complexity wiring of current microelectronic systems and can be used for microsystem packaging with high complexity.
  • Although the preferred embodiment of the invention has been described, it will be understood by the person who is professinal in this technology field, the appended claims are intended to be interpreted as including the preferred embodiments and the modifications and modifications
  • It will be apparent that those skilled in the art can make various modifications and variations to the invention without departing from the spirit and scope of the invention. Thus, it is intended that the present invention cover the modifications and modifications of the invention.

Claims (5)

1. A fan-out wafer level multilayer wiring package structure, wherein the package structure comprises a plurality of semiconductor chips, a multilayer interposer, a vertical interconnection interposer, molding materials and a redistribution layer;
the back surface of the semiconductor chip is bonded to the back surface of the multilayer interposer with the bonding material, and is placed on the same horizontal plane with the vertical interconnection interposer and packaged as a whole with the molding material, and the redistribution layer is provided on the surface of the structure;
the semiconductor chip, the multilayer interposer, the conductive material of the vertical interconnection interproser and the solder ball are connected by the conductive metal layer of the redistribution layer to achieve the signal interconnection between the semiconductor chip and the multilayer interposer and the I/O signal transfer of the semiconductor chip.
2. The fan-out wafer level multilayer wiring package structure of claim 1, wherein the package structure realizes an increase in the number of wiring layers by the multilayer interposer; the multilayer interposer is manufactured by using the CMOS process according to the electrical interconnection design requirements of the system.
3. The fan-out wafer level multilayer wiring package structure of claim 1, wherein the multilayer interposer combines with the semiconductor chip, then the combination and the vertical interconnection interposer are integrated after being placed on the same horizontal plane, to achieve the electrical interconnection between the semiconductor chip or the multilayer interposer and the conductive material of the vertical interconnection interposer and the solder ball by rewiring the conductive metal.
4. The fan-out wafer level multilayer wiring package structure of claim 1, wherein the vertical interconnection interposer is obtained by cutting the corresponding size of the vertical interconnection interposer wafers fixed with the prefabricated through-hole pitch according to the electrical interconnection design requirements between the semiconductor chips.
5. A method for manufacturing a fan-out wafer level package structure, wherein:
the wafer level CMOS process is used to fabricate the multilayer interposer according to the signal interconnection design requirements between the semiconductor chips;
the vertical interconnection interposer wafers fixed with the prefabricated through-hole pitch are cut with the wafer saw to obtain the corresponding size of the vertical interconnection interposer according to the signal interconnection design requirements between the semiconductor chips and the specific requirements for the number of signal leading-out terminals of the system;
the back surface of the semiconductor chip is bonded to the back surface of the multilayer interposer by using the bonding process with the bonding material;
the bonded semiconductor chip and multilayer interposer and the vertical interconnection interposer are temporarily bonded on a carrier, and the front surface of the semiconductor chip faces away from the carrier and the vertical interconnection interposer is placed on the side of the semiconductor chip and the multilayer interposer;
the semiconductor chip, the multilayer interposer and the vertical interconnection interposer on the carrier are packaged, and then the carrier is removed;
the redistribution layer is provided on the surface of the above structure, and the signal I/O of the semiconductor chip is connected to the vertical interconnection interposer through the upper surface RDL, and then connected to the multilayer interposer through the conductive material of the vertical interconnection interposer and the lower surface RDL, or directly connected to the bottom solder ball through the conductive material of the vertical interconnection interposer.
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