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US20180342588A1 - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
US20180342588A1
US20180342588A1 US15/897,180 US201815897180A US2018342588A1 US 20180342588 A1 US20180342588 A1 US 20180342588A1 US 201815897180 A US201815897180 A US 201815897180A US 2018342588 A1 US2018342588 A1 US 2018342588A1
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Prior art keywords
layer
gan
semiconductor device
algan electron
recesses
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US15/897,180
Inventor
Kohei Miki
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Assigned to MITSUBISHI ELECTRIC CORPORATION reassignment MITSUBISHI ELECTRIC CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MIKI, KOHEI
Publication of US20180342588A1 publication Critical patent/US20180342588A1/en
Priority to US16/547,461 priority Critical patent/US10777643B2/en
Abandoned legal-status Critical Current

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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/015Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • H01L29/2003
    • H01L29/205
    • H01L29/66462
    • H01L29/778
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/40FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/40FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82Heterojunctions
    • H10D62/824Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
    • H01L29/401
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503Nitride Group III-V materials, e.g. AlN or GaN
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment

Definitions

  • the present invention relates to a GaN-based semiconductor device used for high speed, high frequency communication and a method for manufacturing the same.
  • a GaN cap layer is provided on a GaN channel layer and an AlGaN electron travel layer to suppress a current collapse phenomenon (e.g., see JP 5396911 B2).
  • a current collapse phenomenon e.g., see JP 5396911 B2
  • an electron concentration of a 2DEG decreases, contact resistance between source and drain electrodes, that is, element resistance increases, causing a high frequency characteristic to deteriorate.
  • a structure in which a gate is formed in a recessed part is generally proposed (e.g., see WO 2013/008422 A1).
  • damage to the 2DEG caused by dry etching results in a problem that an operation current decreases and a leakage current increases, and such a structure is insufficient as a solution to the problem
  • a conventional GaN-HEMT has a trade-off relationship between a high frequency characteristic and a current collapse phenomenon. For this reason, the layer thickness of the GaN cap layer needs to be designed within a current collapse phenomenon tolerable range, which results in a problem that a sufficient high frequency characteristic cannot be demonstrated.
  • the present invention has been implemented to solve the above-described problem and it is an object of the present invention to provide a semiconductor device capable of demonstrating a sufficient high frequency characteristic while suppressing a current collapse phenomenon and a method for manufacturing the same.
  • a semiconductor device includes: a semiconductor substrate; a buffer layer provided on the semiconductor substrate; a GaN channel layer provided on the buffer layer; an AlGaN electron travel layer provided on the GaN channel layer; a GaN cap layer provided on the AlGaN electron travel layer, having a nitrogen polarity, and on which a plurality of recesses are formed; and a gate electrode, a source electrode and a drain electrode provided in each of the plurality of recesses.
  • the gate electrode, the source electrode and the drain electrode are formed in each of the plurality of recesses formed in the GaN cap layer. In this way, even when the GaN cap layer is thickened, the element resistance is not affected, and it is thereby possible to demonstrate a sufficient high frequency characteristic while suppressing a current collapse phenomenon.
  • FIG. 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention.
  • FIGS. 2 to 4 are cross-sectional views illustrating a manufacturing method for the semiconductor device according to the embodiment of the present invention.
  • FIG. 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention.
  • This semiconductor device is a GaN-HEMT.
  • a semiconductor substrate 1 is a SiC substrate in which a GaN-based semiconductor film is allowed to grow.
  • a buffer layer 2 for GaN growth made of GaN or AlN is formed on the semiconductor substrate 1 .
  • a GaN channel layer 3 is formed on the buffer layer 2 .
  • An AlGaN electron travel layer 4 is formed on the GaN channel layer 3 .
  • a 2DEG (two-dimensional electron gas layer) 5 is formed between the GaN channel layer 3 and the AlGaN electron travel layer 4 .
  • a GaN cap layer 6 is formed on the AlGaN electron travel layer 4 .
  • the GaN cap layer 6 has not a gallium polarity but a nitrogen polarity, and suppresses current collapse. Part or a whole of the GaN cap layer 6 is removed and a plurality of recesses 7 are formed.
  • a gate electrode 8 , a source electrode 9 and a drain electrode 10 are formed in each of the plurality of recesses 7 .
  • FIGS. 2 to 4 are cross-sectional views illustrating a manufacturing method for the semiconductor device according to the embodiment of the present invention.
  • the buffer layer 2 , the GaN channel layer 3 and the AlGaN electron travel layer 4 are formed in order on the semiconductor substrate 1 using MOCVD.
  • the GaN cap layer 6 with a nitrogen polarity is fanned.
  • a resist mask 11 for recess formation is formed on the GaN cap layer 6 using photolithography.
  • the GaN cap layer 6 is selectively wet-etched down to the AlGaN electron travel layer 4 using KOH having a concentration on the order of 50% at a temperature of 100° C. or higher to form the plurality of recesses 7 .
  • the resist mask 11 is removed using an organic solvent or a resist stripping agent.
  • the gate electrode 8 , the source electrode 9 and the drain electrode 10 are formed respectively in the plurality of recesses 7 using a vapor deposition method.
  • the semiconductor device according to the present embodiment is manufactured in the steps as described so far.
  • the gate electrode 8 , the source electrode 9 and the drain electrode 10 are formed in each of the plurality of recesses 7 formed in the GaN cap layer 6 . In this way, even when the GaN cap layer 6 is thickened, the element resistance is not affected, and it is thereby possible to demonstrate a sufficient high frequency characteristic while suppressing a current collapse phenomenon.
  • KOH allows the GaN cap layer 6 to be etched free of damage down. to the AlGaN electron travel layer 4 which is an etching stop layer.
  • an insulating film such as SIN or SiO or a metal film such as TiW can also be used as a mask when etching the GaN cap layer 6 using KOH.
  • those films are patterned through dry etching using a patterned resist mask.
  • the films are removed using a chemical liquid such as BHF (buffered hydrofluoric acid).
  • the film formation method for the buffer layer 2 , the GaN channel layer 3 , the AlGaN electron travel layer 4 and the GaN cap layer 6 is used as the film formation method for the buffer layer 2 , the GaN channel layer 3 , the AlGaN electron travel layer 4 and the GaN cap layer 6 .
  • the material of the semiconductor substrate 1 is not limited to SEC, but may be Si, GaN, sapphire (Al 2 O 3 ) or GaAs.
  • the GaN cap layer 6 has a nitrogen polarity, the other layers may have either a nitrogen polarity or a gallium polarity.

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  • Junction Field-Effect Transistors (AREA)

Abstract

A semiconductor device includes: a semiconductor substrate; a buffer layer provided on the semiconductor substrate; a GaN channel layer provided on the buffer layer; an AlGaN electron travel layer provided on the GaN channel layer; a GaN cap layer provided on the AlGaN electron travel layer, having a nitrogen polarity, and on which a plurality of recesses are formed; and a gate electrode, a source electrode and a drain electrode provided in each of the plurality of recesses.

Description

    BACKGROUND OF THE INVENTION Field
  • The present invention relates to a GaN-based semiconductor device used for high speed, high frequency communication and a method for manufacturing the same.
  • Background
  • In an AlGaN/GaN-HEMT, a GaN cap layer is provided on a GaN channel layer and an AlGaN electron travel layer to suppress a current collapse phenomenon (e.g., see JP 5396911 B2). As the GaN cap layer becomes thicker, it is possible to suppress the current collapse phenomenon better, but this causes a region where an electrode is formed to become thicker as well. Thus, an electron concentration of a 2DEG decreases, contact resistance between source and drain electrodes, that is, element resistance increases, causing a high frequency characteristic to deteriorate. As a solution to this problem, a structure in which a gate is formed in a recessed part is generally proposed (e.g., see WO 2013/008422 A1). However, damage to the 2DEG caused by dry etching results in a problem that an operation current decreases and a leakage current increases, and such a structure is insufficient as a solution to the problem
  • SUMMARY
  • A conventional GaN-HEMT has a trade-off relationship between a high frequency characteristic and a current collapse phenomenon. For this reason, the layer thickness of the GaN cap layer needs to be designed within a current collapse phenomenon tolerable range, which results in a problem that a sufficient high frequency characteristic cannot be demonstrated.
  • The present invention has been implemented to solve the above-described problem and it is an object of the present invention to provide a semiconductor device capable of demonstrating a sufficient high frequency characteristic while suppressing a current collapse phenomenon and a method for manufacturing the same.
  • A semiconductor device according to the present invention includes: a semiconductor substrate; a buffer layer provided on the semiconductor substrate; a GaN channel layer provided on the buffer layer; an AlGaN electron travel layer provided on the GaN channel layer; a GaN cap layer provided on the AlGaN electron travel layer, having a nitrogen polarity, and on which a plurality of recesses are formed; and a gate electrode, a source electrode and a drain electrode provided in each of the plurality of recesses.
  • According to the present invention, the gate electrode, the source electrode and the drain electrode are formed in each of the plurality of recesses formed in the GaN cap layer. In this way, even when the GaN cap layer is thickened, the element resistance is not affected, and it is thereby possible to demonstrate a sufficient high frequency characteristic while suppressing a current collapse phenomenon.
  • Other and further objects, features and advantages of the invention will appear more fully from the following description,
  • BRIEF DESCRIPTION OF DRAWINGS
  • FIG. 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention. FIGS. 2 to 4 are cross-sectional views illustrating a manufacturing method for the semiconductor device according to the embodiment of the present invention.
  • DESCRIPTION OF EMBODIMENTS
  • FIG. 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention. This semiconductor device is a GaN-HEMT. A semiconductor substrate 1 is a SiC substrate in which a GaN-based semiconductor film is allowed to grow. A buffer layer 2 for GaN growth made of GaN or AlN is formed on the semiconductor substrate 1.
  • A GaN channel layer 3 is formed on the buffer layer 2. An AlGaN electron travel layer 4 is formed on the GaN channel layer 3. A 2DEG (two-dimensional electron gas layer) 5 is formed between the GaN channel layer 3 and the AlGaN electron travel layer 4.
  • A GaN cap layer 6 is formed on the AlGaN electron travel layer 4. The GaN cap layer 6 has not a gallium polarity but a nitrogen polarity, and suppresses current collapse. Part or a whole of the GaN cap layer 6 is removed and a plurality of recesses 7 are formed. A gate electrode 8, a source electrode 9 and a drain electrode 10 are formed in each of the plurality of recesses 7.
  • Next, manufacturing steps of the semiconductor device according to the present embodiment will be described. FIGS. 2 to 4 are cross-sectional views illustrating a manufacturing method for the semiconductor device according to the embodiment of the present invention. First, as shown in FIG. 2, the buffer layer 2, the GaN channel layer 3 and the AlGaN electron travel layer 4 are formed in order on the semiconductor substrate 1 using MOCVD. Next, the GaN cap layer 6 with a nitrogen polarity is fanned. Next, a resist mask 11 for recess formation is formed on the GaN cap layer 6 using photolithography.
  • Next, as shown in FIG. 3, using the AlGaN electron travel layer 4 as an etching stop layer, the GaN cap layer 6 is selectively wet-etched down to the AlGaN electron travel layer 4 using KOH having a concentration on the order of 50% at a temperature of 100° C. or higher to form the plurality of recesses 7. Next, as shown in FIG. 4, the resist mask 11 is removed using an organic solvent or a resist stripping agent. After that, the gate electrode 8, the source electrode 9 and the drain electrode 10 are formed respectively in the plurality of recesses 7 using a vapor deposition method. The semiconductor device according to the present embodiment is manufactured in the steps as described so far.
  • As described above, according to the present embodiment, the gate electrode 8, the source electrode 9 and the drain electrode 10 are formed in each of the plurality of recesses 7 formed in the GaN cap layer 6. In this way, even when the GaN cap layer 6 is thickened, the element resistance is not affected, and it is thereby possible to demonstrate a sufficient high frequency characteristic while suppressing a current collapse phenomenon.
  • Use of KOH allows the GaN cap layer 6 to be etched free of damage down. to the AlGaN electron travel layer 4 which is an etching stop layer. Instead of the resist mask 11, an insulating film such as SIN or SiO or a metal film such as TiW can also be used as a mask when etching the GaN cap layer 6 using KOH. In such a ease, those films are patterned through dry etching using a patterned resist mask. After forming the plurality of recesses 7 with KOH using those films as masks, the films are removed using a chemical liquid such as BHF (buffered hydrofluoric acid).
  • Note that at least one of MBE, sputtering, plasma CVD and vapor deposition method is used as the film formation method for the buffer layer 2, the GaN channel layer 3, the AlGaN electron travel layer 4 and the GaN cap layer 6. The material of the semiconductor substrate 1 is not limited to SEC, but may be Si, GaN, sapphire (Al2O3) or GaAs. Although the GaN cap layer 6 has a nitrogen polarity, the other layers may have either a nitrogen polarity or a gallium polarity.
  • Obviously many modifications and variations of the present invention are possible in the light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described. The entire disclosure of Japanese Patent Application No. 2017-105731, filed on May 29, 2017 including specification, claims, drawings and summary, on which the Convention priority of the present application is based, is incorporated herein by reference in its entirety,

Claims (5)

1. A semiconductor device comprising:
a semiconductor substrate;
a buffer layer provided on the semiconductor substrate;
a GaN channel layer provided on the buffer layer;
an AlGaN electron travel layer provided on the GaN channel layer;
a GaN cap layer provided on the AlGaN electron travel layer, having a nitrogen polarity, and on which a plurality of recesses are formed; and
a gate electrode, a source electrode and a drain electrode provided in each of the plurality of recesses.
2. A method for manufacturing a semiconductor device comprising:
forming a buffer layer, a GaN channel layer, an AlGaN electron travel layer and a GaN cap layer with a nitrogen polarity in order on a semiconductor substrate;
using the AlGaN electron travel layer as an etching stop layer and etching the GaN cap layer using KOH to form a plurality of recesses; and
forming a gate electrode, a source electrode and a drain electrode in each of the plurality of recesses.
3. The method for manufacturing a semiconductor device according to claim 2, wherein SiN or SiO or TiW is used as a mask when etching the GaN cap layer using the KOH.
4. The method for manufacturing a semiconductor device according to claim 2, wherein at least one of MBE, sputtering, plasma CVD and vapor deposition method is used as a film formation method for the buffer layer, the GaN channel layer, the AlGaN electron travel layer and the GaN cap layer.
5. The method for manufacturing a semiconductor device according to claim 3, wherein at least one of MBE, sputtering, plasma CVD and vapor deposition method is used as a film formation method for the buffer layer, the GaN channel layer, the AlGaN electron travel layer and the GaN cap layer.
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CN115548111A (en) * 2021-06-30 2022-12-30 苏州能讯高能半导体有限公司 Epitaxial structure and its preparation method, semiconductor device and its preparation method

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JP6957982B2 (en) 2021-11-02
US10777643B2 (en) 2020-09-15
US20190378897A1 (en) 2019-12-12

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