US20180323198A1

US20180323198A1 - Thyristor Memory Cell with Assist Device

Info

Publication number: US20180323198A1
Application number: US16/031,990
Authority: US
Inventors: Harry Luan; Bruce L. Bateman; Valery Axelrad; Charlie Cheng
Original assignee: TC Lab Inc
Current assignee: TC Lab Inc
Priority date: 2016-06-03
Filing date: 2018-07-10
Publication date: 2018-11-08
Also published as: EP3252816A1; CN107464808A; US20170352665A1; US10020308B2

Abstract

A vertical thyristor memory array including: a vertical thyristor memory cell, the vertical thyristor memory cell including: a p+ anode; an n-base located below the p+ anode; a p-base located below the n-base; a n+ cathode located below the p-base; an isolation trench located around the vertical thyristor memory cell; an assist gate located in the isolation trench adjacent the n-base wherein an entire vertical height of the assist gate is positioned within an entire vertical height of the n-base.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This patent application is a continuation of U.S. patent application Ser. No. 15/349,978, filed Nov. 11, 2016, issued as U.S. patent Ser. No. 10/020,308 on Jul. 10, 2018, which claims the benefit of U.S. patent application 62/345,203, filed Jun. 3, 2016 and is a continuation-in-part of U.S. patent application Ser. No. 15/197,640, filed Jun. 29, 2016, which are incorporated by reference along with all other references cited in this application.

BACKGROUND OF THE INVENTION

This invention is related to integrated circuit devices and, in particular, to semiconductor-based memory, such as static random access memory (SRAM) and dynamic random access memory (DRAM).
A DRAM is a type of random-access memory that stores a bit of data in a capacitor coupled to a transistor within the integrated circuit. Lithographic scaling and process enhancement may quadruple the number of bits of storage in a DRAM approximately every three years. However, the individual memory cells have become so small that maintaining the capacitance of each cell while reducing charge leakage may significantly limit further reductions in size.
What is needed is a memory unit cell that is smaller than the conventional one-capacitor one-transistor cell, that is readily scalable below 20 nm design rules, that is compatible with standard bulk silicon processing, and that consumes less power, both statically and dynamically.

BRIEF SUMMARY OF THE INVENTION

This invention provides a memory array suitable in which vertical PNPN thyristors are formed in bulk silicon substrate and isolated from each other by a shallow trench of insulating material in one direction and a deeper trench of insulating material in a perpendicular direction. The array of memory cells is arranged in a cross-point grid and interconnected by metal conductors and buried heavily doped layers.
In an embodiment of the present claimed invention, the memory array includes row lines and column lines with anode of thyristor connected to row line, such as bit line, and cathode of thyristor coupled to column line, such as word line. The substrate may be P-conductivity type with N-conductivity type buried layer extending in a first direction to provide a column line. Alternating P-conductivity type and N-conductivity type layers over the buried layer provide the bases of the thyristor, with an upper P-conductivity type layer providing the anode of the thyristor. A conductive layer coupled to the anode of the thyristor extends in a second direction orthogonal to the first direction to provide a row line.
A gate line may be formed in the trench to provide NMOS or PMOS transistors to assist write speed of adjacent thyristor memory cell.
In an embodiment, the gate line may be parallel to a bit line.
In an embodiment, the gate line may be parallel to a word line.
In an embodiment, the gate line may include an NMOS transistor.
In an embodiment, the gate line may include a PMOS transistor.
In an embodiment, the gate line may be shared by two adjacent thyristor memory cells.
In an embodiment, the gate line may be self-aligned.
In an embodiment, the gate line may be located nearer to one adjacent thyristor memory cell and located farther from the other adjacent thyristor memory cell.
Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plane view of a layout of a 2×2 vertical thyristor memory cell array as implemented in an integrated circuit according to an embodiment of a claimed invention.

FIG. 2A illustrates a perspective view of perpendicular cross-sections of a vertical thyristor memory cell with a PMOS assist gate parallel to word line according to an embodiment of a claimed invention.

FIG. 2B illustrates a perspective view of perpendicular cross-sections of a thyristor memory cell with an NMOS assist gate parallel to word line according to an embodiment of a claimed invention.

FIG. 3A illustrates a perspective view of perpendicular cross-sections of a vertical thyristor memory cell with a PMOS assist gate parallel to bit line according to an embodiment of a claimed invention.

FIG. 3B illustrates a perspective view of perpendicular cross-sections of a vertical thyristor memory cell with an NMOS assist gate parallel to bit line according to an embodiment of a claimed invention.

FIG. 4 illustrates doping profile of a vertical thyristor according to an embodiment of a claimed invention.

FIG. 5 illustrates cross-section of vertical thyristor with NMOS assist gate located below upper edge and above lower edge of p-base according to an embodiment of a claimed invention.

FIG. 6A illustrates a perspective view of perpendicular cross-sections of a vertical thyristor memory cell with a PMOS assist gate completely around the vertical thyristor according to an embodiment of a claimed invention.

FIG. 6B illustrates a perspective view of perpendicular cross-sections of a thyristor memory cell with an NMOS assist gate partially around the vertical thyristor according to an embodiment of a claimed invention.

DETAILED DESCRIPTION OF THE INVENTION

This invention discloses position of an assist gate relative to an upper edge and a lower edge of a base of a vertical thyristor memory cell in an array.
FIG. 1 shows a plane view of a layout of a 2×2 vertical thyristor memory cell array as implemented in an integrated circuit according to an embodiment of a claimed invention.
The four vertical thyristors, including anodes, are located at the corners of the layout. The thyristors are separated in two perpendicular directions with trenches filled with oxide.
A first set of parallel conductive lines provides a word line for each row of the memory array by being coupled to the cathodes of the thyristors in the row. A second set of parallel conductive lines provides a bit line for each column of the memory array by being coupled to the anodes of the thyristors in the column. The word lines are perpendicular to the bit lines.
FIG. 4 shows doping profile of a vertical thyristor according to an embodiment of a claimed invention. The doping concentration varies as a function of depth below the upper surface. In an embodiment of the present claimed invention, some peaks may include a shoulder (not shown). The dose may have a tolerance of +/−6% while the ion implantation energy may have a tolerance of +/−2%.
In an embodiment, an assist device, such as a gate, such as PMOS or NMOS, may be formed next to the sidewalls of the isolation trenches adjacent the thyristor. The assist gates may increase write speed and may reduce write voltage.
The sidewalls of the trench are oxidized, thus forming the gate oxide that isolates the gate electrodes from the doped regions. In an embodiment of the present claimed invention, the gate oxide may have a thickness of 3.0 (+/−0.3) nm.
The trenches are then partially filled with silicon dioxide, such as by a chemical vapor deposition process.
Then a conformal doped-polycrystalline silicon layer is deposited over the structure.
An anisotropic etching step removes the entire conformal polycrystalline silicon layer except for a desired thickness to form a gate (control) line that includes the assist gate.
Then, another trench filling operation is performed to finish filling the trenches.
Planarization steps are then performed, such as by using chemical mechanical polishing or other techniques.
Later, an electrical connection is made to couple the gate (control) lines.
As shown in FIG. 2(a), a PMOS assist gate 80 may be positioned adjacent to the n-base of the vertical thyristor. The PMOS assist gate 80 may run parallel to the word lines (WL) and orthogonal to the bit lines (BL). The word lines may be buried and connected with a conductor in (and through) the isolation trench.
As shown in FIG. 2 (b), an NMOS assist gate 86 may be positioned adjacent to the p-base of the vertical thyristor. The PMOS assist gate 86 may run parallel to the word lines. The word lines may be buried and connected with a conductor in (and through) the isolation trench.
As shown in FIG. 3(a), a PMOS assist gate 80 may be positioned adjacent to the n-base of the vertical thyristor. The PMOS assist gate 80 may run parallel to the bit lines. The bit lines may include an overlying M1.
As shown in FIG. 3(b), an NMOS assist gate 86 may be positioned adjacent to the p-base of the vertical thyristor. The PMOS assist gate 86 may run parallel to the bit lines. The bit lines may include an overlying M1.
In an embodiment of the present claimed invention, the p-base may have a height of 110.0 (+/−11.0) nm.
In an embodiment of the present claimed invention, the NMOS assist gate may have a gate length (vertical height) of 55.0 (+/−5.5) nm.
As shown in an embodiment of the present claimed invention in FIG. 5, an upper edge of the NMOS assist gate (G) may be positioned about 30.5 (+/−3.0) nm below an upper edge of the p-base sPW which in turn underlies sNW.
As shown in an embodiment of the present claimed invention in FIG. 5, a lower edge of the NMOS assist gate may be positioned about 24.5 (+/−2.5) nm above a lower edge of the p-base which in turn overlies bNW.
In other embodiments, the assist gates may be formed—partially, in separate segments, or completely—around the vertical thyristor, such as illustrated by FIGS. 6(a) and 6(b).
In other embodiments, the sidewall gates 80, 86 may be formed from other conductive material, such as metal, such as tungsten, or silicide(s), or combinations of different materials.
In an embodiment of the present claimed invention, p+ anodes are connected to bit lines (M1 layer) while n+ anodes are connected to word lines (M2 layer straps between drops for about every 32 vertical thyristors) are connected to N+ cathodes.
This description of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form described, and many modifications and variations are possible in light of the teaching above. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications. This description will enable others skilled in the art to best utilize and practice the invention in various embodiments and with various modifications as are suited to a particular use. The scope of the invention is defined by the following claims.

Claims

The invention claimed is:

1. A vertical thyristor memory array comprising:

a vertical thyristor memory cell, the vertical thyristor memory cell comprising:

a p+ anode;

an n-base disposed below the p+ anode;

a p-base disposed below the n-base;

a n+ cathode disposed below the p-base;

an isolation trench disposed around the vertical thyristor memory cell;

an assist gate disposed in the isolation trench adjacent the n-base wherein an entire vertical height of the assist gate is disposed within an entire vertical height of the n-base.

2. The vertical thyristor memory array of claim 1 wherein the assist gate comprises P-type coupling capacitor.

3. The vertical thyristor memory array of claim 1 wherein the assist gate runs orthogonal to the anode lines.

4. The vertical thyristor memory array of claim 1 wherein the assist gate runs parallel to the anode lines.

5. A vertical thyristor memory array comprising:

a p+ anode;

an n-base disposed below the p+ anode;

a p-base disposed below the n-base;

a n+ cathode disposed below the p-base;

an isolation trench disposed around the vertical thyristor memory cell;

an assist gate disposed in the isolation trench adjacent the p-base wherein an entire vertical height of the assist gate is disposed within an entire vertical height of the p-base.

6. The vertical thyristor memory array of claim 3 wherein the assist gate comprises NMOS.

7. The vertical thyristor memory array of claim 1 wherein the assist gate runs parallel to the anode lines.

8. The vertical thyristor memory array of claim 1 wherein the assist gate runs parallel to the anode lines.