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US20180151247A1 - Semiconductor device and semiconductor integrated system - Google Patents

Semiconductor device and semiconductor integrated system Download PDF

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Publication number
US20180151247A1
US20180151247A1 US15/801,018 US201715801018A US2018151247A1 US 20180151247 A1 US20180151247 A1 US 20180151247A1 US 201715801018 A US201715801018 A US 201715801018A US 2018151247 A1 US2018151247 A1 US 2018151247A1
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Prior art keywords
memory chip
serial bus
semiconductor device
memory
chip
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US15/801,018
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US10283214B2 (en
Inventor
Hajime Sato
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Renesas Electronics Corp
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Renesas Electronics Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • H10W90/00—
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
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    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
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    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
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    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
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    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
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    • G—PHYSICS
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    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
    • G—PHYSICS
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    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/18—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of the types provided for in two or more different main groups of the same subclass of H10B, H10D, H10F, H10H, H10K or H10N
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
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    • G11C—STATIC STORES
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    • G11C2029/0401—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals in embedded memories
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
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    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
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    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
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    • H01L2225/06596—Structural arrangements for testing
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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Definitions

  • the present disclosure relates to a semiconductor device and a semiconductor integrated system and relates to a semiconductor device including a memory chip.
  • MCP Multi Chip Package
  • MCM Multi-Chip Module
  • Japanese Unexamined Patent Application Publication No. 2003-77296 proposes an embodiment where a self-test circuit (BIST: Built-In Self-Test circuit) is mounted on a logic chip in an MCP and a test of a memory chip packaged in the same MCP is performed.
  • BIST Built-In Self-Test circuit
  • the embodiment is a method where the logic chip accesses the memory chip, and the embodiment does not disclose a method where the memory chip is directly accessed and the memory chip is tested and debugged.
  • the memory chip includes a memory chip testing circuit that performs an operation test of the memory chip and a serial bus interface circuit for transmitting and receiving data between the memory chip testing circuit and a serial bus provided outside the package.
  • the memory chip includes a serial bus interface circuit, so that it is possible to access the memory chip by a simple method.
  • FIG. 1 is a diagram for explaining a configuration of a semiconductor device 1 based on a first embodiment.
  • FIG. 2 is a diagram for explaining a cross-sectional structure of the semiconductor device 1 based on the first embodiment.
  • FIG. 3 is a diagram for explaining a configuration of a memory chip MD based on the first embodiment.
  • FIG. 4 is a diagram for explaining functional blocks of a base die based on the first embodiment.
  • FIG. 5 is a diagram for explaining a configuration of a serial bus interface circuit SIF based on the first embodiment.
  • FIG. 6 is a diagram for explaining a configuration of a system board SD based on the first embodiment.
  • FIG. 7 is a diagram for explaining a configuration of a memory chip MD# based on a modified example of the first embodiment.
  • FIG. 8 is a diagram for explaining a configuration of a semiconductor device l# based on a second embodiment.
  • FIG. 9 is a diagram for explaining a configuration of a system board SD# based on a third embodiment.
  • FIG. 1 is a diagram for explaining a configuration of a semiconductor device 1 based on a first embodiment.
  • the semiconductor device 1 is a semiconductor device that mounts a plurality of chips in a common package.
  • the semiconductor device 1 includes a logic chip PU and a memory chip MD.
  • the logic chip PU is a chip such as a processor unit which is incorporated in order to realize a predetermined function.
  • the memory chip MD is a chip composed of a memory element that stores data.
  • the logic chip PU is coupled with the memory chip MD and transmits and receives a clock, a control signal, an address, and data to and from the memory chip MD.
  • the memory chip MD operates in synchronization with a clock from the login chip PU.
  • the memory chip MD is accessed according to input of a control signal and an address from the logic chip PU. For example, data is read from the memory chip MD to the logic chip PU, or data is written to the memory chip from the logic chip PU.
  • the memory chip MD is incorporated with a test circuit TC and a serial bus interface circuit SIF.
  • the memory chip MD includes a DRAM (Dynamic Random Access Memory) element as an example.
  • DRAM Dynamic Random Access Memory
  • the test circuit TC of the semiconductor device 1 includes an external terminal SDAP and an external terminal SCLP through the serial bus interface circuit SIF.
  • the external terminal SDAP is a data terminal for performing serial data communication.
  • the external terminal SCLP is a clock terminal that specifies timing for performing serial data communication.
  • the external terminals SDAP and SCLP are coupled with a serial bus provided outside the semiconductor device 1 .
  • serial bus interface circuit SIF a standard serial bus interface circuit such as I2C (Inter-Integrated Circuit) is used as an example.
  • the test circuit TC is a BIST circuit and tests operation and the like of a DRAM element in the memory chip MD.
  • the semiconductor device 1 based on the first embodiment is mounted with the serial bus interface circuit SIF in the memory chip MD and can issue a test instruction to the test circuit TC through an external serial bus. Further, the semiconductor device 1 can acquire an output result (a test result) from the test circuit TC through the serial bus.
  • the semiconductor device 1 based on the first embodiment is provided with the external terminals SDAP and SCLP of a standard serial bus such as I2C for accessing the test circuit TC of the memory chip MD.
  • the external terminals SDAP and SCLP are coupled to the standard serial bus.
  • the memory chip MD of the first embodiment is a stacked type memory chip (a semiconductor storage device), and the semiconductor storage device is provided with the test circuit TC.
  • the test circuit TC is a circuit that performs a test of the DRAM element inside the memory chip MD from a signal of the standard serial bus such as I2C.
  • the test circuit TC is provided so as to be able to be directly controlled through the external terminals SDAP and SCLP.
  • the memory chip MD is controlled by the logic chip PU such as a processor unit in a normal operation. Specifically, the memory chip MD directly communicates with the logic chip PU such as a processor unit by transmitting and receiving a clock, a control signal, an address, and data, and the memory chip MD is not directly accessed from outside.
  • the memory chip MD is used as a cache memory and a packet buffer of a processor unit or the like.
  • FIG. 2 is a diagram for explaining a cross-sectional structure of the semiconductor device 1 based on the first embodiment.
  • the memory chip MD is coupled with the logic chip PU through a silicon interposer SIP.
  • the silicon interposer SIP couples between the memory chip MD and the logic chip PU by ultra-fine wiring.
  • the silicon interposer SIP is directly electrically coupled with an external package ball 13 through an organic substrate 10 .
  • the external package ball 13 functions as an external terminal.
  • the external package ball 13 functions as the external terminals SDAP and SCLP.
  • the memory chip MD is formed of a plurality of stacked type memory dies.
  • FIG. 3 is a diagram for explaining a configuration of the memory chip MD based on the first embodiment.
  • the memory chip MD includes a base die 102 provided at the lowest layer and a plurality of memory dies 100 provided above the base die 102 .
  • the base die 102 and the plurality of memory dies 100 are electrically coupled with each other through a vertical structure through electrode TSV.
  • the through electrode TSV is electrically coupled with the silicon interposer SIP through a bump BP provided under the base die 102 .
  • FIG. 4 is a diagram for explaining functional blocks of the base die 102 based on the first embodiment.
  • the base die 102 is mounted with the test circuit TC and the serial bus interface circuit SIF.
  • the serial bus interface circuit SIF is coupled with the external terminal SDAP and the external terminal SCLP.
  • the test circuit TC is controlled based on data inputted from the external terminal SDAP and the external terminal SCLP through the serial bus interface circuit SIF.
  • a test result from the test circuit TC is outputted to the external terminal SDAP through the serial bus interface circuit SIF.
  • FIG. 5 is a diagram for explaining a configuration of the serial bus interface circuit SIF based on the first embodiment.
  • the serial bus interface circuit SIF includes a clock buffer SCLB for a clock signal, a data buffer SDAB for a data signal, and a serial link unit SL.
  • the serial link unit SL is coupled with the clock buffer SCLB for a clock signal and the data buffer SDAB for a data signal.
  • the serial link unit SL receives a serial clock and serial data inputted through a serial bus and outputs a test instruction to the test circuit TC. Further, the serial link unit SL receives an output result (a test result) from the test circuit TC and outputs a serial clock and serial data to the serial bus.
  • the external terminal SCLP is coupled with the clock buffer SCLB.
  • the external terminal SDAP is coupled with the data buffer SDAB.
  • the clock buffer SCLB includes an amplifier AP 1 , an inverter IV 1 , and a transistor TR 1 .
  • the data buffer SDAB includes an amplifier AP 2 , an inverter IV 2 , and a transistor TR 2 .
  • serial clock SCL_DATA and SCL_OUT
  • serial data SDA_DATA and SDA_OUT
  • a data communication method between the serial link unit SL and the serial bus through the clock buffer SCLB and the data buffer SDAB is generally known, so that the method will not be described in detail.
  • FIG. 6 is a diagram for explaining a configuration of a system board SD based on the first embodiment.
  • an entire control unit MCU that controls the entire system board SD over a system board SD (mother board), an entire control unit MCU that controls the entire system board SD, a peripheral device 5 , the semiconductor device 1 , and a serial bus SB are mounted.
  • a peripheral device 5 a semiconductor device of various sensors may be mounted as an example.
  • the peripheral device 5 is not limited to a sensor.
  • the entire control unit MCU, the peripheral device 5 , and the semiconductor device 1 are coupled through the serial bus SB, and the serial bus SB is pulled up by a power supply voltage VCC through resistance elements R 0 and R 1 .
  • the serial bus SB includes a serial data bus SDB and a serial clock bus SCB.
  • the serial data bus SDB is provided for the serial data.
  • the serial clock bus SCB is provided for the serial clock.
  • the entire control unit MCU, the peripheral device 5 , and the semiconductor device 1 are provided with serial bus interfaces, respectively, and are able to communicate with each other.
  • serial bus interfaces respectively, and are able to communicate with each other.
  • the entire control unit MCU can access each semiconductor device 1 through the serial bus SB.
  • serial bus SB serial bus
  • FIG. 7 is a diagram for explaining a configuration of a memory chip MD# based on a modified example of the first embodiment.
  • the memory chip MD# includes a plurality of memory dies 100 #.
  • the memory chip MD# is different from the memory chip MD described in FIG. 3 in that the memory chip MD# has no base die.
  • the memory chip MD# is formed of only the plurality of memory dies 100 #.
  • the plurality of memory dies 100 # are electrically coupled with each other through the vertical structure through electrode TSV.
  • the through electrode TSV is electrically coupled with the silicon interposer SIP through the bump BP provided to the lowest memory die 100 #.
  • the lowest memory die 100 # is provided with the test circuit TC and the serial bus interface circuit SIF.
  • FIG. 8 is a diagram for explaining a configuration of a semiconductor device 1 # based on a second embodiment.
  • the semiconductor device 1 # mounts a plurality of memory chips MDA and MDB and a common logic chip PU in a common package.
  • Each of the memory chips MDA and MDB is configured to be able to be accessed from the logic chip PU.
  • the memory chip MDA includes a test circuit TCA and a serial bus interface circuit SIFA.
  • the memory chip MDB includes a test circuit TCB and a serial bus interface circuit SIFB.
  • test circuits TCA and TCB are basically the same as the test circuit TC.
  • serial bus interface circuits SIFA and SIFB are basically the same as the serial bus interface circuit SIF.
  • the external terminal SDAP and the external terminal SCLP are provided as common terminals of the serial bus interface circuits SIFA and SIFB.
  • identification information is assigned to each of the memory chips MDA and MDB.
  • identification information ID (0 ⁇ 0) is assigned to the memory chip MDA.
  • a device ID (0 ⁇ 0) of a serial bus is set corresponding to the memory chip MDA.
  • identification information ID (0 ⁇ 1) is assigned to the memory chip MDB.
  • a device ID (0 ⁇ 1) of a serial bus is set corresponding to the memory chip MDB.
  • the semiconductor device 1 # based on the second embodiment mounts the serial bus interface circuits SIFA and SIFB on the memory chips MDA and MDB, respectively.
  • the serial bus interface circuits SIFA and SIFB receive an input of test instruction inputted through an external serial bus according to identification information assigned to the memory chips MDA and MDB, respectively.
  • test circuits TCA and TCB performs test according to the test instruction.
  • the test circuits TCA and TCB can output an output result (a test result) through an external serial bus.
  • FIG. 9 is a diagram for explaining a configuration of a system board SD# based on a third embodiment.
  • the semiconductor device 1 A mounts a plurality of memory chips MDA, MDB, MDC, and MDD, and a logic chip PU in a common package.
  • Each of the memory chips MDA, MDB, MDC, and MDD is configured to be able to be accessed from the logic chip PU.
  • the other components are the same as those of FIG. 1 , so that the detailed description thereof will not be repeated.
  • identification info nation is assigned to each of the memory chips MDA to MDD. Further, a case is shown where identification information is also assigned to each of the plurality of semiconductor devices 1 A to 1 C.
  • a device ID of the serial bus is divided into upper bits and lower bits, and then the upper bits are assigned to a semiconductor device and the lower bits are assigned to the memory chip of the semiconductor device.
  • sets of upper bits ID 1 of the device ID of the serial bus are assigned corresponding to the semiconductor devices 1 A to 1 C, respectively.
  • the device ID 1 (0 ⁇ 0) is set corresponding to the semiconductor device 1 A.
  • the device ID 1 (0 ⁇ 1) is set corresponding to the semiconductor device 1 B.
  • the device ID 1 (0 ⁇ 2) is set corresponding to the semiconductor device 1 C.
  • sets of lower bits ID 0 of the device ID of the serial bus are assigned corresponding to the memory chips in each semiconductor device 1 A to 1 C, respectively.
  • the device ID 0 (0 ⁇ 0) of the serial bus is set corresponding to the memory chip MDA.
  • the device ID 0 (0 ⁇ 1) of the serial bus is set corresponding to the memory chip MDB.
  • the device ID 0 (0 ⁇ 2) of the serial bus is set corresponding to the memory chip MDC.
  • the device ID 0 (0 ⁇ 3) of the serial bus is set corresponding to the memory chip MDD.
  • peripheral device 5 may be further mounted over the system board SD#.
  • the peripheral device 5 is not limited to a sensor.
  • the entire control unit MCU and the semiconductor devices 1 A to 1 C are coupled through the serial bus SB, and the serial bus SB is pulled up by the power supply voltage VCC through the resistance elements R 0 and R 1 .
  • the entire control unit MCU and the semiconductor devices 1 A to 1 C are provided with serial bus interfaces, respectively, and are able to communicate with each other.
  • the entire control unit MCU can access each semiconductor device 1 through the serial bus SB by using the upper bits of the identification information. Further, the entire control unit MCU can access a corresponding memory chip in the semiconductor device through the serial bus SB by using the lower bits of the identification information.
  • test circuit BIST circuit

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Abstract

A semiconductor device is provided where it is possible to access and test a memory chip by a simple method.
The semiconductor device that mounts a plurality of chips in a common package includes a logic chip having a predetermined function and a memory chip that is coupled with the logic chip and stores data. The memory chip includes a memory chip testing circuit that performs an operation test of the memory chip and a serial bus interface circuit for transmitting and receiving data between the memory chip testing circuit and a serial bus provided outside the package.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • The disclosure of Japanese Patent Application No. 2016-232846 filed on Nov. 30, 2016 including the specification, drawings and abstract is incorporated herein by reference in its entirety.
    • BACKGROUND
  • The present disclosure relates to a semiconductor device and a semiconductor integrated system and relates to a semiconductor device including a memory chip.
  • Semiconductor devices called MCP (Multi Chip Package) or MCM (Multi-Chip Module) where a memory chip of large capacity and a logic chip having a specific function such as image processing are mounted in the same package are becoming pervasive.
  • In this regard, Japanese Unexamined Patent Application Publication No. 2003-77296 proposes an embodiment where a self-test circuit (BIST: Built-In Self-Test circuit) is mounted on a logic chip in an MCP and a test of a memory chip packaged in the same MCP is performed.
  • However, the embodiment is a method where the logic chip accesses the memory chip, and the embodiment does not disclose a method where the memory chip is directly accessed and the memory chip is tested and debugged.
    • SUMMARY
  • On the other hand, a mechanism for directly accessing the memory chip from pins outside the package is required.
  • The present disclosure is to solve the above problem and an object of the present disclosure is to provide a semiconductor device and a semiconductor integrated system where it is possible to access and test the memory chip by a simple method.
  • The other problems and novel features will become apparent from the description of the present specification and the accompanying drawings.
  • According to an embodiment, a semiconductor device that mounts a plurality of chips in a common package includes a logic chip having a predetermined function and a memory chip that is coupled with the logic chip and stores data. The memory chip includes a memory chip testing circuit that performs an operation test of the memory chip and a serial bus interface circuit for transmitting and receiving data between the memory chip testing circuit and a serial bus provided outside the package.
  • According to the embodiment, the memory chip includes a serial bus interface circuit, so that it is possible to access the memory chip by a simple method.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a diagram for explaining a configuration of a semiconductor device 1 based on a first embodiment.
  • FIG. 2 is a diagram for explaining a cross-sectional structure of the semiconductor device 1 based on the first embodiment.
  • FIG. 3 is a diagram for explaining a configuration of a memory chip MD based on the first embodiment.
  • FIG. 4 is a diagram for explaining functional blocks of a base die based on the first embodiment.
  • FIG. 5 is a diagram for explaining a configuration of a serial bus interface circuit SIF based on the first embodiment.
  • FIG. 6 is a diagram for explaining a configuration of a system board SD based on the first embodiment.
  • FIG. 7 is a diagram for explaining a configuration of a memory chip MD# based on a modified example of the first embodiment.
  • FIG. 8 is a diagram for explaining a configuration of a semiconductor device l# based on a second embodiment.
  • FIG. 9 is a diagram for explaining a configuration of a system board SD# based on a third embodiment.
    •  DETAILED DESCRIPTION
  • Embodiments will be described in detail with reference to the drawings. The same reference symbols are given to the same or corresponding parts in the drawings, and the description of the parts will not be repeated.
    • First Embodiment
  • FIG. 1 is a diagram for explaining a configuration of a semiconductor device 1 based on a first embodiment.
  • As shown in FIG. 1, the semiconductor device 1 is a semiconductor device that mounts a plurality of chips in a common package.
  • Specifically, the semiconductor device 1 includes a logic chip PU and a memory chip MD.
  • The logic chip PU is a chip such as a processor unit which is incorporated in order to realize a predetermined function.
  • The memory chip MD is a chip composed of a memory element that stores data.
  • The logic chip PU is coupled with the memory chip MD and transmits and receives a clock, a control signal, an address, and data to and from the memory chip MD. For example, the memory chip MD operates in synchronization with a clock from the login chip PU. The memory chip MD is accessed according to input of a control signal and an address from the logic chip PU. For example, data is read from the memory chip MD to the logic chip PU, or data is written to the memory chip from the logic chip PU.
  • In the present example, the memory chip MD is incorporated with a test circuit TC and a serial bus interface circuit SIF.
  • The memory chip MD includes a DRAM (Dynamic Random Access Memory) element as an example.
  • The test circuit TC of the semiconductor device 1 includes an external terminal SDAP and an external terminal SCLP through the serial bus interface circuit SIF.
  • The external terminal SDAP is a data terminal for performing serial data communication. The external terminal SCLP is a clock terminal that specifies timing for performing serial data communication.
  • The external terminals SDAP and SCLP are coupled with a serial bus provided outside the semiconductor device 1.
  • In the present example, as the serial bus interface circuit SIF, a standard serial bus interface circuit such as I2C (Inter-Integrated Circuit) is used as an example.
  • The test circuit TC is a BIST circuit and tests operation and the like of a DRAM element in the memory chip MD.
  • The semiconductor device 1 based on the first embodiment is mounted with the serial bus interface circuit SIF in the memory chip MD and can issue a test instruction to the test circuit TC through an external serial bus. Further, the semiconductor device 1 can acquire an output result (a test result) from the test circuit TC through the serial bus.
  • The semiconductor device 1 based on the first embodiment is provided with the external terminals SDAP and SCLP of a standard serial bus such as I2C for accessing the test circuit TC of the memory chip MD. The external terminals SDAP and SCLP are coupled to the standard serial bus.
  • The memory chip MD of the first embodiment is a stacked type memory chip (a semiconductor storage device), and the semiconductor storage device is provided with the test circuit TC. The test circuit TC is a circuit that performs a test of the DRAM element inside the memory chip MD from a signal of the standard serial bus such as I2C. The test circuit TC is provided so as to be able to be directly controlled through the external terminals SDAP and SCLP. The memory chip MD is controlled by the logic chip PU such as a processor unit in a normal operation. Specifically, the memory chip MD directly communicates with the logic chip PU such as a processor unit by transmitting and receiving a clock, a control signal, an address, and data, and the memory chip MD is not directly accessed from outside. The memory chip MD is used as a cache memory and a packet buffer of a processor unit or the like.
  • Therefore, it is possible to access the memory chip MD by a simple method by a configuration according to the first embodiment. Although a method for accessing the memory chip MD by using a test pin has been proposed, the method that uses the test pin increases a load of system designer and also increases cost. On the other hand, when using a method that uses an existing serial bus, the system designer can perform a test by a simple method while using the existing bus without introducing any special bus for a new test.
  • FIG. 2 is a diagram for explaining a cross-sectional structure of the semiconductor device 1 based on the first embodiment.
  • As shown in FIG. 2, the memory chip MD is coupled with the logic chip PU through a silicon interposer SIP.
  • The silicon interposer SIP couples between the memory chip MD and the logic chip PU by ultra-fine wiring.
  • The silicon interposer SIP is directly electrically coupled with an external package ball 13 through an organic substrate 10. The external package ball 13 functions as an external terminal. In the present example, the external package ball 13 functions as the external terminals SDAP and SCLP.
  • The memory chip MD is formed of a plurality of stacked type memory dies.
  • FIG. 3 is a diagram for explaining a configuration of the memory chip MD based on the first embodiment.
  • As shown in FIG. 3, the memory chip MD includes a base die 102 provided at the lowest layer and a plurality of memory dies 100 provided above the base die 102.
  • The base die 102 and the plurality of memory dies 100 are electrically coupled with each other through a vertical structure through electrode TSV.
  • The through electrode TSV is electrically coupled with the silicon interposer SIP through a bump BP provided under the base die 102.
  • FIG. 4 is a diagram for explaining functional blocks of the base die 102 based on the first embodiment.
  • As shown in FIG. 4, the base die 102 is mounted with the test circuit TC and the serial bus interface circuit SIF.
  • The serial bus interface circuit SIF is coupled with the external terminal SDAP and the external terminal SCLP.
  • The test circuit TC is controlled based on data inputted from the external terminal SDAP and the external terminal SCLP through the serial bus interface circuit SIF. A test result from the test circuit TC is outputted to the external terminal SDAP through the serial bus interface circuit SIF.
  • FIG. 5 is a diagram for explaining a configuration of the serial bus interface circuit SIF based on the first embodiment.
  • As shown in FIG. 5, the serial bus interface circuit SIF includes a clock buffer SCLB for a clock signal, a data buffer SDAB for a data signal, and a serial link unit SL.
  • The serial link unit SL is coupled with the clock buffer SCLB for a clock signal and the data buffer SDAB for a data signal.
  • The serial link unit SL receives a serial clock and serial data inputted through a serial bus and outputs a test instruction to the test circuit TC. Further, the serial link unit SL receives an output result (a test result) from the test circuit TC and outputs a serial clock and serial data to the serial bus.
  • The external terminal SCLP is coupled with the clock buffer SCLB. The external terminal SDAP is coupled with the data buffer SDAB.
  • The clock buffer SCLB includes an amplifier AP1, an inverter IV1, and a transistor TR1.
  • The data buffer SDAB includes an amplifier AP2, an inverter IV2, and a transistor TR2.
  • Regarding the serial clock (SCL_DATA and SCL_OUT) and the serial data (SDA_DATA and SDA_OUT), data is transmitted to and received from the serial link unit SL through the clock buffer SCLB and the data buffer SDAB.
  • A data communication method between the serial link unit SL and the serial bus through the clock buffer SCLB and the data buffer SDAB is generally known, so that the method will not be described in detail. As an example, it is possible to use a communication method of I2C serial bus.
  • FIG. 6 is a diagram for explaining a configuration of a system board SD based on the first embodiment.
  • As shown in FIG. 6, over a system board SD (mother board), an entire control unit MCU that controls the entire system board SD, a peripheral device 5, the semiconductor device 1, and a serial bus SB are mounted. As the peripheral device 5, a semiconductor device of various sensors may be mounted as an example. However, the peripheral device 5 is not limited to a sensor.
  • The entire control unit MCU, the peripheral device 5, and the semiconductor device 1 are coupled through the serial bus SB, and the serial bus SB is pulled up by a power supply voltage VCC through resistance elements R0 and R1. The serial bus SB includes a serial data bus SDB and a serial clock bus SCB. The serial data bus SDB is provided for the serial data. The serial clock bus SCB is provided for the serial clock.
  • Although not shown in the drawings, the entire control unit MCU, the peripheral device 5, and the semiconductor device 1, each of which are a device, are provided with serial bus interfaces, respectively, and are able to communicate with each other. As an example, it is possible to use a communication method of I2C serial bus.
  • The entire control unit MCU can access each semiconductor device 1 through the serial bus SB. When performing a test on the memory chip MD according to the embodiment over the system board SD, it is not necessary to introduce a special bus for the memory chip. It is possible to test the memory chip MD by using an existing standard serial bus. Further, the test circuit (BIST circuit) is controlled by using a standard serial bus, so that it is possible to reduce man-hour for developing a test program and debug software.
    • Modified Example
  • FIG. 7 is a diagram for explaining a configuration of a memory chip MD# based on a modified example of the first embodiment.
  • As shown in FIG. 7, the memory chip MD# includes a plurality of memory dies 100#.
  • The memory chip MD# is different from the memory chip MD described in FIG. 3 in that the memory chip MD# has no base die.
  • Specifically, the memory chip MD# is formed of only the plurality of memory dies 100#.
  • In the same manner as described above, the plurality of memory dies 100# are electrically coupled with each other through the vertical structure through electrode TSV.
  • The through electrode TSV is electrically coupled with the silicon interposer SIP through the bump BP provided to the lowest memory die 100#.
  • The lowest memory die 100# is provided with the test circuit TC and the serial bus interface circuit SIF.
  • The other components are the same as those of the first embodiment, so that the detailed description thereof will not be repeated.
  • In general, different process nodes are often respectively applied to the base die and the memory die. However, in the modified example of the first embodiment, it is possible to obtain the same effect as that of the first embodiment by only the process node of the memory die, so that it is possible to further reduce the cost.
    • Second Embodiment
  • FIG. 8 is a diagram for explaining a configuration of a semiconductor device 1# based on a second embodiment.
  • As shown in FIG. 8, the semiconductor device 1# mounts a plurality of memory chips MDA and MDB and a common logic chip PU in a common package.
  • Each of the memory chips MDA and MDB is configured to be able to be accessed from the logic chip PU.
  • The other components are the same as those of FIG. 1, so that the detailed description thereof will not be repeated.
  • The memory chip MDA includes a test circuit TCA and a serial bus interface circuit SIFA.
  • The memory chip MDB includes a test circuit TCB and a serial bus interface circuit SIFB.
  • The test circuits TCA and TCB are basically the same as the test circuit TC.
  • The serial bus interface circuits SIFA and SIFB are basically the same as the serial bus interface circuit SIF.
  • The external terminal SDAP and the external terminal SCLP are provided as common terminals of the serial bus interface circuits SIFA and SIFB.
  • In the present example, a case is shown where identification information is assigned to each of the memory chips MDA and MDB.
  • Specifically, identification information ID (0×0) is assigned to the memory chip MDA. As an example, a device ID (0×0) of a serial bus is set corresponding to the memory chip MDA. Further, identification information ID (0×1) is assigned to the memory chip MDB. As an example, a device ID (0×1) of a serial bus is set corresponding to the memory chip MDB.
  • The semiconductor device 1# based on the second embodiment mounts the serial bus interface circuits SIFA and SIFB on the memory chips MDA and MDB, respectively. The serial bus interface circuits SIFA and SIFB receive an input of test instruction inputted through an external serial bus according to identification information assigned to the memory chips MDA and MDB, respectively.
  • Each of test circuits TCA and TCB performs test according to the test instruction. The test circuits TCA and TCB can output an output result (a test result) through an external serial bus.
  • By this constitution, it is possible to directly test each memory chip included in the semiconductor device 1# from a system through a serial bus.
  • Further, in the present example, it is possible to access a plurality of memory chips by using the common external teLutinals SDAP and SCLP. Therefore, even when a plurality of memory chips are mounted in the semiconductor device, it is possible to reduce the number of serial bus terminals required as external teLminals of the semiconductor device to a minimum.
    • Third Embodiment
  • FIG. 9 is a diagram for explaining a configuration of a system board SD# based on a third embodiment.
  • As shown in FIG. 9, over a system board SD# (motherboard), an entire control unit MCU that controls the entire system board SD#, a plurality of semiconductor devices 1A to 1C, and a serial bus SB are mounted.
  • The semiconductor device 1A. mounts a plurality of memory chips MDA, MDB, MDC, and MDD, and a logic chip PU in a common package.
  • Each of the memory chips MDA, MDB, MDC, and MDD is configured to be able to be accessed from the logic chip PU. The other components are the same as those of FIG. 1, so that the detailed description thereof will not be repeated.
  • In the present example, a case is shown where identification info Nation is assigned to each of the memory chips MDA to MDD. Further, a case is shown where identification information is also assigned to each of the plurality of semiconductor devices 1A to 1C.
  • Specifically, a device ID of the serial bus is divided into upper bits and lower bits, and then the upper bits are assigned to a semiconductor device and the lower bits are assigned to the memory chip of the semiconductor device.
  • As an example, sets of upper bits ID1 of the device ID of the serial bus are assigned corresponding to the semiconductor devices 1A to 1C, respectively. Specifically, the device ID1 (0×0) is set corresponding to the semiconductor device 1A. The device ID1 (0×1) is set corresponding to the semiconductor device 1B. The device ID1 (0×2) is set corresponding to the semiconductor device 1C.
  • Further, sets of lower bits ID0 of the device ID of the serial bus are assigned corresponding to the memory chips in each semiconductor device 1A to 1C, respectively. Specifically, the device ID0 (0×0) of the serial bus is set corresponding to the memory chip MDA. The device ID0 (0×1) of the serial bus is set corresponding to the memory chip MDB. The device ID0 (0×2) of the serial bus is set corresponding to the memory chip MDC. The device ID0 (0×3) of the serial bus is set corresponding to the memory chip MDD.
  • Although no peripheral device is provided in the present example, the peripheral device 5 may be further mounted over the system board SD#. The peripheral device 5 is not limited to a sensor.
  • The entire control unit MCU and the semiconductor devices 1A to 1C are coupled through the serial bus SB, and the serial bus SB is pulled up by the power supply voltage VCC through the resistance elements R0 and R1. Although not shown in the drawings, the entire control unit MCU and the semiconductor devices 1A to 1C, each of which are a device, are provided with serial bus interfaces, respectively, and are able to communicate with each other. As an example, it is possible to use a communication method of I2C serial bus.
  • The entire control unit MCU can access each semiconductor device 1 through the serial bus SB by using the upper bits of the identification information. Further, the entire control unit MCU can access a corresponding memory chip in the semiconductor device through the serial bus SB by using the lower bits of the identification information.
  • When performing a test on the memory chip MD according to the embodiment over the system board SD, it is not necessary to introduce a special bus for the memory chip. It is possible to test the memory chip MD by using an existing standard serial bus. Further, the test circuit (BIST circuit) is controlled by using a standard serial bus, so that it is possible to reduce man-hour for developing a test program and debug software.
  • While the present disclosure has been specifically described based on the embodiments, it is needless to say that the present invention is not limited to the embodiments and may be variously modified without departing from the scope of the invention.

Claims (10)

What is claimed is:
1. A semiconductor device that mounts a plurality of chips in a common package, the semiconductor device comprising:
a logic chip having a predetermined function; and
a memory chip that is coupled with the logic chip and stores data,
wherein the memory chip includes
a memory chip testing circuit that performs an operation test of the memory chip, and
a serial bus interface circuit for transmitting and receiving data between the memory chip testing circuit and a serial bus provided outside the package.
2. The semiconductor device according to claim 1,
wherein the memory chip includes a plurality of stacked type memory dies which are electrically coupled together by a through electrode, and
wherein the memory chip testing circuit and the serial bus interface circuit are provided to at least one of the memory dies.
3. The semiconductor device according to claim 1,
wherein the memory chip includes
a base die provided at a lowest layer, and
a plurality of stacked type memory dies which are provided above the base die and electrically coupled together by a through electrode, and
wherein the memory chip testing circuit and the serial bus interface circuit are provided to the memory die.
4. The semiconductor device according to claim 3 , wherein the base die further includes a bump that is used for external coupling.
5. The semiconductor device according to claim 1, wherein the logic chip and the memory chip are coupled through a silicon interposer.
6. The semiconductor device according to claim 1,
wherein the serial bus interface circuit includes
a clock buffer for a clock signal, and
a data buffer for a data signal.
7. A semiconductor integrated system comprising:
a system board;
an entire control unit that is provided over the system board and controls the entire system board;
a plurality of semiconductor devices provided over the system board; and
a serial bus that couples the entire control unit and the semiconductor devices,
wherein each semiconductor device is a semiconductor device that mounts a plurality of chips in a common package, and includes
a logic chip having a predetermined function, and
a memory chip that is coupled with the logic chip and stores data, and
wherein the memory chip includes
a memory chip testing circuit that performs an operation test of the memory chip, and
a serial bus interface circuit for transmitting and receiving data between the memory chip testing circuit and the serial bus provided outside the package.
8. The semiconductor integrated system according to claim 7,
wherein identification information is assigned to each of the semiconductor devices, and
wherein the entire control unit accesses a memory chip of a corresponding semiconductor device according to identification information assigned through the serial bus and instructs the memory chip to perform the operation test.
9. The semiconductor integrated system according to claim 8,
wherein each semiconductor device is provided with a plurality of memory chips,
wherein the identification information includes upper bits and lower bits, and
wherein the entire control unit accesses a corresponding semiconductor device of the semiconductor devices based on at least either of the upper bits and the lower bits assigned through the serial bus, accesses a corresponding memory chip of the memory chips in the corresponding semiconductor device based on the other of the upper bits and the lower bits, and instructs the memory chip to perform the operation test.
10. The semiconductor integrated system according to claim 7,
wherein the memory chip includes a plurality of stacked type memory dies which are electrically coupled together by a through electrode, and
wherein the memory chip testing circuit and the serial bus interface circuit are provided to at least one of the memory dies.
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