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US20180138100A1 - Power module and inverter equipment - Google Patents

Power module and inverter equipment Download PDF

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Publication number
US20180138100A1
US20180138100A1 US15/863,537 US201815863537A US2018138100A1 US 20180138100 A1 US20180138100 A1 US 20180138100A1 US 201815863537 A US201815863537 A US 201815863537A US 2018138100 A1 US2018138100 A1 US 2018138100A1
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US
United States
Prior art keywords
power module
metallic pattern
module according
frame member
power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US15/863,537
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English (en)
Inventor
Seita Iwahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Assigned to ROHM CO., LTD. reassignment ROHM CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: IWAHASHI, SEITA
Publication of US20180138100A1 publication Critical patent/US20180138100A1/en
Priority to US16/390,945 priority Critical patent/US10748826B2/en
Abandoned legal-status Critical Current

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Classifications

    • H10W74/111—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group subclass H10D
    • H01L25/072—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group subclass H10D the devices being arranged next to each other
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
    • H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
    • H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H10W40/10—
    • H10W40/22—
    • H10W70/60—
    • H10W70/65—
    • H10W74/40—
    • H10W76/42—
    • H10W90/00—
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P27/00—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage
    • H02P27/04—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage
    • H02P27/06—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using DC to AC converters or inverters
    • H10W72/01515—
    • H10W72/075—
    • H10W72/884—
    • H10W90/734—

Definitions

  • Embodiments described herein relate to a power module, and inverter equipment on which such a power module is mounted.
  • SiC power devices have low on resistance as compared with Si power devices, and also include high switching speed and high temperature operation characteristics.
  • DBC Direct Bonding Copper
  • DBA Direct Brazed Aluminum
  • AMB Active Metal Brazed, Active Metal Bond
  • the embodiments provide: a power module easy to be fabricated, capable of suppressing such a degradation of the bonded portion and improving reliability; and the inverter equipment on which such a power module is mounted.
  • a power module comprising: a first metallic pattern; a plurality of power devices configured to be bonded on the first metallic pattern, each of the plurality of the power devices has a thickness thinner than a thickness of the metallic pattern; a frame member disposed so as to collectively enclose a predetermined number of the plurality of the power devices on the first metallic pattern; a second metallic pattern disposed outside the frame member; and a resin layer configured to seal the plurality of the power devices, the first metallic pattern, and the second metallic pattern so as to include the frame member, wherein the frame member suppresses a stress according to a difference between a coefficient of thermal expansion of the metallic pattern and a coefficient of thermal expansion of the power devices.
  • inverter equipment comprising a circuit in which a plurality of switching elements are connected in series between power terminals and a connection unit of the plurality of the switching elements is used as an output, wherein the inverter equipment is configured to mount at least one power module which is mentioned above as the switching elements.
  • the power module easy to be fabricated, capable of suppressing the degradation of the bonded portion and improving reliability; and the inverter equipment on which such a power module is mounted.
  • FIG. 1 is a bird's-eye view configuration diagram (perspective diagram) showing a principal portion of a power module according to the embodiments.
  • FIG. 2 is a schematic cross-sectional structure diagram taken in the line II-II of FIG. 1 .
  • FIG. 3A is a planar pattern configuration diagram showing a ceramic frame disposed on a metallic pattern, in the power module according to the embodiments.
  • FIG. 3B is a schematic cross-sectional structure diagram taken in the line IIIb-IIIb of FIG. 3A .
  • FIG. 4A is a schematic cross-sectional structure diagram showing a power module with a ceramic frame, in an example of a case where no resin layer is formed thereon.
  • FIG. 4B is a schematic cross-sectional structure diagram showing a power module without a ceramic frame, in an example of a case where no resin layer is formed thereon.
  • FIG. 4C shows a simulation result showing a stress applied to the bonded portion being compared for each component.
  • FIG. 5A is a conceptual diagram showing the component in each direction of the stress.
  • FIG. 5B is a schematic cross-sectional diagram for explaining each component of the stress applied to the bonded portion.
  • FIG. 6A is a schematic cross-sectional structure diagram showing a power module with a ceramic frame, in an example of a case where a resin layer is formed thereon.
  • FIG. 6B is a schematic cross-sectional structure diagram showing a power module without a ceramic frame, in an example of a case where a resin layer is formed thereon.
  • FIG. 6C shows a simulation result showing a stress applied to the bonded portion being compared for each component.
  • FIG. 7A is a schematic cross-sectional structure diagram axisymmetrically showing a power module with a ceramic frame, in an example of a case where no resin layer is formed thereon.
  • FIG. 7B is a schematic cross-sectional structure diagram axisymmetrically showing a power module without a ceramic frame, in an example of a case where no resin layer is formed thereon.
  • FIG. 8A shows a simulation result showing a relationship between a shear stress and a distance from an axis of the power module with a ceramic frame, in an example of a case where no resin layer is formed thereon.
  • FIG. 8B shows a simulation result showing a relationship between a shear stress and a distance from an axis of the power module without a ceramic frame, in an example of a case where no resin layer is formed thereon.
  • FIG. 9A is a schematic cross-sectional structure diagram axisymmetrically showing a power module with a ceramic frame, in an example of a case where a resin layer is formed thereon.
  • FIG. 9B is a schematic cross-sectional structure diagram axisymmetrically showing a power module without a ceramic frame, in an example of a case where a resin layer is formed thereon.
  • FIG. 10A shows a simulation result showing a relationship between a shear stress and a distance from an axis of the power module with a ceramic frame, in an example of a case where a resin layer is formed thereon.
  • FIG. 10B shows a simulation result showing a relationship between a shear stress and a distance from an axis of the power module without a ceramic frame, in an example of a case where a resin layer is formed thereon.
  • FIG. 11A is a schematic cross-sectional structure diagram showing one process of a fabrication method of the power module according to the embodiments (Phase 1).
  • FIG. 11B is a schematic cross-sectional structure diagram showing one process of the fabrication method of the power module according to the embodiments (Phase 2).
  • FIG. 12A is a schematic cross-sectional structure diagram showing one process of the fabrication method of the power module according to the embodiments (Phase 3).
  • FIG. 12B is a schematic cross-sectional structure diagram showing one process of the fabrication method of the power module according to the embodiments (Phase 4).
  • FIG. 13A is a schematic cross-sectional structure diagram showing one process of the fabrication method of the power module according to the embodiments (Phase 5).
  • FIG. 13B is a schematic cross-sectional structure diagram showing one process of the fabrication method of the power module according to the embodiments (Phase 6).
  • FIG. 14 is a schematic cross-sectional structure diagram showing one process of the fabrication method of the power module according to the embodiments (Phase 7), in an example of a case where a heat sink is formed thereto.
  • FIG. 15A is a planar pattern configuration diagram showing a ceramic frame, in a power module according to a modified example 1 of the embodiments.
  • FIG. 15B is a schematic cross-sectional structure diagram taken in the line XVII-XVII of FIG. 15A .
  • FIG. 15C is a schematic cross-sectional structure diagram showing a ceramic frame, in a power module according to a modified example 2 of the embodiments.
  • FIG. 15D is a schematic cross-sectional structure diagram showing a ceramic frame, in a power module according to a modified example 3 of the embodiments.
  • FIG. 16A is a schematic cross-sectional structure diagram showing a ceramic frame, in a power module according to a modified example 4 of the embodiments.
  • FIG. 16B is a schematic cross-sectional structure diagram showing a ceramic frame, in a power module according to a modified example 5 of the embodiments.
  • FIG. 16C is a schematic cross-sectional structure diagram showing a ceramic frame, in a power module according to a modified example 6 of the embodiments.
  • FIG. 16D is a schematic cross-sectional structure diagram showing a ceramic frame, in a power module according to a modified example 7 of the embodiments.
  • FIG. 17A is a planar pattern configuration diagram showing a ceramic frame in an example of a case where one semiconductor device is mounted therein (Phase 1-1), in a power module according to a modified example 8 of the embodiments.
  • FIG. 17B is a planar pattern configuration diagram showing a ceramic frame in an example of a case where two semiconductor devices are mounted therein (Phase 1-2), in the power module according to the modified example 8 of the embodiments.
  • FIG. 17C is a planar pattern configuration diagram showing a ceramic frame in an example of a case where one semiconductor device is mounted therein (Phase 2), in the power module according to the modified example 8 of the embodiments.
  • FIG. 17D is a planar pattern configuration diagram showing a ceramic frame in an example of a case where two semiconductor devices are mounted therein (Phase 3), in the power module according to the modified example 8 of the embodiments.
  • FIG. 18 is a schematic cross-sectional structure diagram showing a power module according to an additional embodiment 1.
  • FIG. 19 is a schematic cross-sectional structure diagram showing a power module according to an additional embodiment 2.
  • FIG. 20 is a bird's-eye view (perspective diagram) showing the power module according to the additional embodiment 2 such that a resin layer is in a transmitted state.
  • FIG. 21 is a bird's-eye view configuration diagram (perspective diagram) showing a module with the built-in half-bridge, in a power module according to an additional embodiment 3.
  • FIG. 22 is a planar pattern configuration diagram showing the power module according to the additional embodiment 3 such that a resin layer is in a transmitted state, in a 2-in-1 module (module with the built-in half-bridge).
  • FIG. 23 is a circuit configuration diagram showing the 2-in-1 module (module with the built-in half-bridge) in which an SiC Metal Oxide Semiconductor Field Effect Transistor (MISFET) is applied as a semiconductor device, in the power module according to the additional embodiment 3.
  • MISFET SiC Metal Oxide Semiconductor Field Effect Transistor
  • FIG. 24 is a bird's-eye view configuration diagram (perspective diagram) showing an aspect before forming the resin layer in the module with the built-in half-bridge, in the power module according to the additional embodiment 3.
  • FIG. 25A is a circuit representative diagram of the SiC MISFET of a 1-in-1 module, which is the power module according to the embodiments.
  • FIG. 253 is a circuit representative diagram of an Insulated Gate Bipolar Transistor (IGBT) of a 1-in-1 module, in the power module according to the embodiments.
  • IGBT Insulated Gate Bipolar Transistor
  • FIG. 26 is a detail circuit representative diagram of the SiC MISFET of the 1-in-1 module, which is the power module according to the embodiments.
  • FIG. 27A is a circuit representative diagram of an SiC MISFET of a 2-in-1 module, which is the power module according to the embodiments.
  • FIG. 27B is a circuit representative diagram of an IGBT of a 2-in-1 module, which is the power module according to the embodiments.
  • FIG. 28A is a schematic cross-sectional structure diagram of an SiC MISFET, which is an example of a semiconductor device to be applied to the power module according to the embodiments.
  • FIG. 28B is a schematic cross-sectional structure diagram of an IGBT, which is an example of the semiconductor device to be applied to the power module according to the embodiments.
  • FIG. 29 is a schematic cross-sectional structure diagram showing an SiC MISFET including a source pad electrode SP and a gate pad electrode GP, which is an example of the semiconductor device to be applied to the power module according to the embodiments.
  • FIG. 30 is a schematic cross-sectional structure diagram of the IGBT including an emitter pad electrode EP and a gate pad electrode GP, which is an example of the semiconductor device to be applied to the power module according to the embodiments.
  • FIG. 31 is a schematic cross-sectional structure diagram of an SiC Double Implanted MISFET (SiC DIMISFET), which is an example of a semiconductor device which can be applied to the power module according to the embodiments.
  • SiC DIMISFET SiC Double Implanted MISFET
  • FIG. 32 is a schematic cross-sectional structure diagram of an SiC Trench MISFET (SiC TMISFET), which is an example of a semiconductor device which can be applied to the power module according to the embodiments.
  • SiC Trench MISFET SiC TMISFET
  • FIG. 33A shows an example of a circuit configuration in which the SiC MISFET is applied as a semiconductor device, and a snubber capacitor is connected between a power terminal PL and an earth terminal (ground terminal) NL, in a circuit configuration of a three-phase alternating current (AC) inverter composed using the power module according to the embodiments.
  • AC alternating current
  • FIG. 33B shows an example of a circuit configuration in which the IGBT is applied as a semiconductor device, and the snubber capacitor is connected between the power terminal PL and the earth terminal (ground terminal) NL, in the circuit configuration of a three-phase AC inverter composed using the power module according to the embodiments.
  • FIG. 34 is a circuit configuration diagram of a three-phase AC inverter composed using the power module according to the embodiments to which the SiC MISFET is applied as the semiconductor device.
  • FIG. 35 is a circuit configuration diagram of a three-phase AC inverter composed using the power module according to the embodiments to which the IGBT is applied as the semiconductor device.
  • FIG. 1 shows a bird's-eye view configuration of a power module 20 according to the embodiments.
  • FIG. 2 shows a schematic cross-sectional structure of a principal portion taken in line II-II of FIG. 1 in which a ceramic frame (frame member) 10 is disposed at a peripheral portion of a metallic pattern (metallic substrate) 3 formed on a ceramics substrate (mounting substrate) 8 , in the power module 20 according to the embodiments.
  • FIG. 3A shows a planar pattern configuration of the ceramic frame 10 disposed at a peripheral portion of the metallic pattern 3 on the ceramics substrate 8
  • FIG. 3B shows a schematic cross-sectional structure taken in the line IIIb-IIIb of FIG. 3A .
  • the principal portion of the power module 20 includes: a ceramics substrate 8 ; a semiconductor device (semiconductor chip) 1 as a power device configured to be bonded near a center portion of the metallic pattern 3 on the ceramics substrate 8 ; a ceramic frame 10 disposed along an edge of the metallic pattern 3 on the ceramics substrate 8 , a cross-sectional structure of the ceramic frame 10 configured to enclose the semiconductor device 1 being an I-shaped structure; and a resin layer 14 configured to seal the semiconductor device 1 and the ceramics substrate 8 so as to include the ceramic frame 10 .
  • the semiconductor device 1 is illustrated as one element, it may be composed of a plurality of elements (e.g., modules).
  • the semiconductor device 1 is bonded with solder on an upper surface of the metallic pattern 3 via a bonding layer under chip (bonded portion) 2
  • the ceramic frame 10 is bonded with solder on the upper surface of the metallic pattern 3 via a bonding layer under frame 11 capable of solder bonding by being subjected to metal sputtering etc.
  • the resin layer 14 configured to cover side surface portions of the ceramics substrate 8 is formed using a resin, etc., capable of transfer molding.
  • DBC Direct Bonding Copper
  • DBA Direct Brazed Aluminum
  • AMB Active Metal Brazed, Active Metal Bond
  • FIGS. 4A-4C respectively show stresses applied to the bonded portion between the semiconductor device 1 and the metallic pattern 3 , comparing between a case of being provided with the ceramic frame 10 (WCF: With Ceramic Frame) and a case of being provided without the ceramic frame 10 (WOCF: Without Ceramic Frame), when no resin layer 14 is formed thereon.
  • FIG. 4A shows a schematic cross-sectional structure of a power module 20 - 1 a in the case of being provided with the ceramic frame 10
  • FIG. 4B shows a schematic cross-sectional structure of a power module 20 - 1 b in the case of being provided without the ceramic frame 10
  • FIG. 4C graphically shows each component ( ⁇ xx, ⁇ zz, ⁇ zx) of a simulation result of each stress.
  • a size (width ⁇ thickness) of a cross section of the metallic pattern 3 is set as 10 ⁇ 1
  • a size (width ⁇ thickness) in a cross-sectional direction of the semiconductor device 1 is set as 5 ⁇ 0.25.
  • a component in the direction z of a stress applied to the bonded portion CP is referred to as the vertical stress ⁇ zz
  • a component in the direction x of the stress applied to the bonded portion CP is referred to as the horizontal stress ⁇ xx
  • a component in the direction zx of the stress applied to the bonded portion CP is referred to as the shear stress ⁇ zx, as shown in FIGS. 5A and 5B .
  • the shear stress ⁇ zx can be reduced more remarkably than other stresses ⁇ xx and ⁇ zz.
  • FIGS. 6A-6C respectively show stresses applied to the bonded portion between the semiconductor device 1 and the metallic pattern 3 , comparing between a case of being provided with the ceramic frame 10 (WCF) and a case of being provided without the ceramic frame 10 (WOCF), when the resin layer 14 is formed thereon.
  • FIG. 6A shows a schematic cross-sectional structure of a power module 20 - 2 a in the case of being provided with the ceramic frame 10
  • FIG. 6B shows a schematic cross-sectional structure of a power module 20 - 2 b in the case of being provided without the ceramic frame 10
  • FIG. 6C graphically shows each component ( ⁇ xx, ⁇ zz, ⁇ zx) of a simulation result of each stress.
  • the shear stress ⁇ zx can be reduced more remarkably than other stresses ⁇ xx and ⁇ zz.
  • FIGS. 7-10 show the operation/working-effect produced by being providing the ceramic frame 10 in order to be further explained in detail, in the power module 20 according to the embodiments.
  • FIGS. 7 and 8 respectively show stresses applied to the bonded portion between the semiconductor device (SiC) 1 and the metallic pattern (Cu substrate) 3 , comparing between a case of being provided with the ceramic frame (SiN) 10 and a case of being provided without the ceramic frame (SiN) 10 , when the resin layer (Resin) 14 is not formed thereon.
  • FIG. 7A shows a schematic cross-sectional structure of the power module 20 - 1 a in the case of being provided with the ceramic frame 10 axisymmetrically taken in the line Yc-Yc
  • FIG. 7B shows a schematic cross-sectional structure of the power module 20 - 1 b in the case of being provided without the ceramic frame 10 axisymmetrically taken in the line Yc-Yc.
  • FIG. 8A shows a stress simulation result showing a relationship between a distance from the axis of the power module 20 - 1 a and a shear stress ⁇ zx
  • FIG. 8B shows a stress simulation result showing a relationship between a distance from the axis of the power module 20 - 1 b and a shear stress ⁇ zx.
  • the thickness of the cross section of the ceramic frame 10 is thicker than the thickness of the semiconductor device 1 , and the size (width ⁇ thickness) of the cross section of the ceramic frame 10 is set to 2 ⁇ 1 (the approximately same thickness as the metallic pattern 3 ), for example.
  • FIGS. 9 and 10 respectively show stresses applied to the bonded portion between the semiconductor device (SiC) 1 and the metallic pattern (Cu substrate) 3 , comparing between a case of being provided with the ceramic frame (SiN) 10 and a case of being provided without the ceramic frame (SiN) 10 , when the resin layer (Resin) 14 is formed thereon.
  • FIG. 9A shows a schematic cross-sectional structure of the power module 20 - 2 a in the case of being provided with the ceramic frame 10 axisymmetrically taken in the line Yc-Yc
  • FIG. 9B shows a schematic cross-sectional structure of the power module 20 - 2 b in the case of being provided without the ceramic frame 10 axisymmetrically taken in the line Yc-Yc.
  • FIG. 10A shows a stress simulation result showing a relationship between a distance from the axis of the power module 20 - 2 a and a shear stress ⁇ zx
  • FIG. 10B shows a stress simulation result showing a relationship between a distance from the axis of the power module 20 - 2 b and a shear stress ⁇ zx.
  • the size (width ⁇ thickness) of the cross section of the resin layer 14 is set to 15 ⁇ 7.5.
  • the ceramic frame 10 has a function of suppressing the shear stress ⁇ zx according to the difference between the CTE value of the metallic pattern 3 and the CTE value of the semiconductor device 1 . More specifically, the ceramic frame 10 has an effect of reducing the CTE value of Cu so that the metallic pattern 3 is not shrunk.
  • the shear stress ⁇ zx applied to the bonded portion CP at the time of the heat cycle test, etc. can be remarkably reduced by providing the ceramic frame 10 having the CTE value smaller than the CTE value of Cu of the metallic pattern 3 but larger than the CTE value of the semiconductor device 1 , as described above.
  • the ceramic frame (SiN) 10 having the CTE value of approximately 2-10 ppm/K may be provided, in the power module 20 according to the embodiments.
  • the CTE value of the resin layer 14 is set as approximately 12-14 ppm/K, in the power module 20 according to the embodiments.
  • a fabrication method of the power module 20 mainly includes: forming a ceramic frame 10 on a peripheral portion of a metallic pattern 3 on a ceramics substrate 8 ; disposing a semiconductor device 1 on the metallic pattern 3 inside the ceramic frame 10 ; and forming a resin layer 14 configured to seal the semiconductor device 1 and the ceramics substrate 8 so as to include the ceramic frame 10 .
  • a DBC substrate formed by forming respectively Cu frames on a front side surface and a back side surface of a ceramics substrate 8 is prepared for as a mounting substrate.
  • a metallic pattern 3 having a CTE value of approximately 16 ppm/K, and patterned metallic patterns (copper foils) 5 and 7 are formed on the front side surface of the ceramics substrate 8 .
  • a metallic pattern (metallic frame) 9 is formed on the back side surface of the ceramics substrate 8 .
  • a ceramic frame 10 having a CTE value of approximately 2-10 ppm/K is formed via a bonding layer under frame 11 on the metallic pattern 3 on the front side surface of the ceramics substrate 8 .
  • a soldering layer or an adhesive layer are applicable to the bonding layer under frame 11 , for example.
  • an SiC based semiconductor device 1 having a CTE value of approximately 3 ppm is bonded with die bonding via a bonding layer 2 under chip on the metallic pattern 3 on the front side surface of the ceramics substrate 8 inside the ceramic frame 10 .
  • a soldering layer or an Ag sintered layer are applicable for the bonding layer 2 under chip.
  • an Ag nanoparticle layer etc. which are previously formed on a back side surface of the semiconductor device 1 may be used for the bonding layer 2 under chip.
  • the processing order of (b) forming a ceramic frame 10 on the metallic pattern 3 and (c) bonding the semiconductor device 1 on the metallic pattern 3 may also be reversed. Accordingly, the ceramic frame 10 may be formed, after bonding of the semiconductor device 1 .
  • the bonding wires 4 and 6 are respectively bonded to a gate electrode and a source electrode of the semiconductor device 1 .
  • the bonding wires 4 and 6 may respectively be bonding-connected on the patterned metallic patterns 5 and 7 .
  • the bonding wires 4 and 6 can be formed by including Al, AlCu, or the like, for example.
  • block terminal electrodes 12 and 13 are respectively connected via soldering layers (not shown) on the metallic patterns 5 and 7 patterned on the front side surface of the ceramics substrate 8 .
  • FIG. 12A block terminal electrodes 12 and 13 are respectively connected via soldering layers (not shown) on the metallic patterns 5 and 7 patterned on the front side surface of the ceramics substrate 8 .
  • a resin layer 14 configured to seal the semiconductor device 1 and the ceramics substrate 8 so as to include the inside of the ceramic frame 10 is formed to seal the whole of the power module.
  • a transfer molding process is applicable to the formation of the resin layer 14 .
  • the power module 20 includes a heat sink 100 as shown in FIG. 14 , for example, and the ceramics substrate 8 may be disposed on the heat sink 100 .
  • the heat sink 100 is formed by including a Cu base for heat radiation, for example.
  • the metallic pattern 9 formed on the back side surface of the ceramics substrate 8 is connected to the heat sink 100 via a soldering layer 16 under substrate.
  • a simplification of the module fabrication process and a miniaturization of the module can be realized since the module fabrication can be realized without attachment of a case.
  • a height of the ceramic frame 10 is approximately 5 mm to approximately 0.2 mm, for example. Moreover, the ceramic frame 10 is formed in an approximately square shape. The height and width of the frame are preferable to be made as small as possible so that the chip size is suitable for the purpose of a miniaturization and a cost reduction, in the light of a sufficiently effective design calculated from the simulation result etc.
  • the ceramics may be formed by including: Al 2 O 3 , AlN, SiN, AlSiC; or SiC of which at least the front side surface has insulating property, for example.
  • a front side surface of Al 2 O 3 may be subjected to plating processing of W, Ni, the Au, or the like.
  • the frame member may be formed by milling etc.
  • a thickness of the resin layer 14 is approximately 4.0 mm to approximately 10 mm, for example.
  • the block terminal electrodes 12 and 13 may be formed by including Cu, CuMo, or the like.
  • the ceramic substrate 8 may be formed by including: Al 2 O 3 , AlN, SiN, AlSiC; or SiC of which at least the front side surface has insulating property, for example.
  • FIG. 15A shows a planar pattern configuration of a ceramic frame 10 , in the power module according to a modified example 1 of the embodiments
  • FIG. 15B shows a schematic cross-sectional structure taken in the line XVII-XVII of FIG. 15A .
  • a cross-sectional structure of the ceramic frame 10 may have a T-shaped structure by being provided with a ceramic frame 10 including a cap portion 10 A of a protruding structure, as shown in FIG. 15B .
  • An engaging degree of the resin layer 14 can be improved and thereby adhesibility thereof can be improved, by being provided with the ceramic frame 10 including the cap portion 10 A of the protruding structure.
  • FIG. 15C shows a schematic cross-sectional structure of a ceramic frame 10 , in a power module according to a modified example 2 of the embodiments.
  • a cross-sectional structure of the ceramic frame 10 may have an inverted-L-shaped structure or ⁇ (gamma)-shaped structure by being provided with a cap portion 10 B, as shown in FIG. 15C .
  • An engaging degree of the resin layer 14 can be improved and thereby adhesibility thereof can be improved, by being provided with the ceramic frame 10 including the cap portion 10 B of the protruding structure.
  • FIG. 15D shows a schematic cross-sectional structure of a ceramic frame 10 , in a power module according to a modified example 3 of the embodiments.
  • a cross-sectional structure of the ceramic frame 10 may have an inverted-L-shaped structure or ⁇ -shaped structure by being provided with a cap portion 10 C, as shown in FIG. 15D .
  • An engaging degree of the resin layer 14 can be improved and thereby adhesibility thereof can be improved, by being provided with the ceramic frame 10 including the cap portion 100 of the protruding structure.
  • FIG. 16A shows a schematic cross-sectional structure of a ceramic frame 10 , in a power module according to a modified example 4 of the embodiments.
  • a surface roughening process may be applied to a surface 10 S of a ceramic frame 10 having an I-shaped structure.
  • the surface roughening process to be applied to the ceramic frame 10 can be realized by a sandblast processing etc.
  • an engaging degree of the resin layer 14 can be further improved and thereby adhesibility thereof can be improved, by applying the surface roughening process to the surface 10 S of the ceramic frame 10 .
  • FIG. 16B shows a schematic cross-sectional structure of a ceramic frame 10 , in a power module according to a modified example 5 of the embodiments.
  • a surface roughening process may be applied to a surface 10 S of a ceramic frame 10 having a T-shaped structure, by being provided with the cap portion 10 A.
  • an engaging degree of the resin layer 14 can be further improved and thereby adhesibility thereof can be improved, by applying the surface roughening process to the surface 10 S of the ceramic frame 10 .
  • FIG. 16C shows a schematic cross-sectional structure of a ceramic frame 10 , in a power module according to a modified example 6 of the embodiments.
  • a surface roughening process may be applied to a surface 10 S of a ceramic frame 10 having an inverted-L-shaped structure or ⁇ -shaped structure, by being provided with the cap portion 10 B.
  • an engaging degree of the resin layer 14 can be further improved and thereby adhesibility thereof can be improved, by applying the surface roughening process to the surface 10 S of the ceramic frame 10 .
  • FIG. 16D shows a schematic cross-sectional structure of a ceramic frame 10 , in a power module according to a modified example 7 of the embodiments.
  • a surface roughening process may be applied to a surface 10 S of a ceramic frame 10 having an inverted-L-shaped structure or T-shaped structure, by being provided with the cap portion 10 C.
  • an engaging degree of the resin layer 14 can be further improved and thereby adhesibility thereof can be improved, by applying the surface roughening process to the surface 10 S of the ceramic frame 10 .
  • FIGS. 17A-17D show planar pattern configurations of ceramic frames 10 , in a power module according to a modified example 8 of the embodiments.
  • a ceramic frame 10 a of rectangular shape, e.g. rectangle, may be adopted, as shown in FIG. 17A .
  • the ceramic frame is not limited to the ceramic frame 10 a enclosing the periphery of one semiconductor device 1 , but a ceramic frame 10 b enclosing the periphery of a plurality of semiconductor devices 1 A and 1 B as shown in FIG. 17B may be adopted.
  • a circle-shaped (e.g. circular or elliptical) ceramic frame 10 c may be adopted, as shown in FIG. 17C .
  • a line-shaped (e.g. straight line-shaped) ceramic frame 10 d disposed along a long side of the metallic pattern 3 near the semiconductor devices 1 A and 1 B, without enclosing the periphery of semiconductor devices 1 A and 1 B, may be adopted, as shown in FIG. 17D .
  • the ceramic frame 10 is not limited to a structure of being arranged along an edge of the metallic pattern 3 , but the ceramic frame 10 may be arranged at an inner side than the edge of the metallic pattern 3 as shown in FIGS. 17A-17D .
  • each of the ceramic frames 10 a - 10 d respectively shown in FIGS. 17A-17D may not always be integral-type frame, but may be divided to be fragmentarily arranged.
  • the power module according to the embodiments and its modified examples can be applied, in particular to various transfer-mold type power modules, e.g. IGBT modules in which IGBT chips are mounted on metallic (e.g. Cu) substrates, diode modules, MIS (Si, SiC, GaN) modules.
  • IGBT modules in which IGBT chips are mounted on metallic (e.g. Cu) substrates, diode modules, MIS (Si, SiC, GaN) modules.
  • the low-cost power module having a simplified structure, easy to be fabricated through a simplified and easy process, and capable of improving mass productivity and realizing miniaturization thereof.
  • the power module can be easily fabricated and excellent also in mass productivity.
  • a block terminal electrode 17 may be provided therein, instead of the bonding wires 4 and 6 .
  • the block terminal electrode 17 can be disposed on a gate electrode or source electrode on the front side surface of the semiconductor device 1 .
  • a plurality of the block terminal electrodes 17 may be disposed for the gate and source electrodes.
  • the block terminal electrode 17 may be formed by including Cu, CuMo, or the like.
  • the power module 20 may include: a relaying substrate 18 configured to select a bonding wire 19 and a block terminal electrode 23 , relaying substrate 18 disposed on the metallic pattern 3 inside the ceramic frame 10 ; and a block terminal electrode 21 configured to connect between a source electrode on the semiconductor device 1 and a metallic pattern 7 on the ceramics substrate 8 .
  • FIG. 19 shows a schematic cross-sectional structure of the power module 20
  • FIG. 20 shows a bird's-eye view configuration of the power module 20 such that the resin layer 14 is in a transmitted state.
  • the relaying substrate 18 includes a ceramics substrate, and copper foils (Cu frames) formed respectively on front side and back side surfaces of the ceramics substrate. More specifically, the relaying substrate 18 has a DBC substrate structure. Moreover, a DBA substrate or AMB substrate may be used as the relaying substrate 18 .
  • the bonding wire 19 bonding-connects between the gate electrode on the semiconductor device 1 and the copper foil on the relaying substrate 18 .
  • the bonding wire 19 can be formed by including Al, AlCu, or the like, for example.
  • the block terminal electrode 23 is configured to connect between the copper foil on the relaying substrate 18 and the metallic pattern 5 on the ceramics substrate 8 respectively via soldering layers (not shown).
  • the block terminal electrodes 21 and 23 may be formed by including Cu, CuMo, or the like.
  • FIG. 21 shows a bird's-eye view configuration of so-called 2-in-1 module (module with the built-in half-bridge) in which two semiconductor devices are contained in one module, in a power module 200 according to an additional embodiment 3.
  • FIG. 22 shows a planar pattern configuration of the power module 200 before forming the resin layer 14
  • FIG. 23 shows a circuit configuration of the 2-in-1 module to which SiC MISFETs Q 1 and Q 4 are applied as semiconductor devices.
  • the power module 200 includes a configuration of a module with so-called built-in half-bridge in which two MISFETs Q 1 and Q 4 are built in one module.
  • FIG. 22 shows an example of 4-chip of the MISFETs Q 1 and 4-chip of the MISFETs Q 4 respectively disposed in parallel.
  • one MISFET can mount five transistors (chip) at the maximum. Note that it is also possible to mount a part of five pieces of the chips for the diode DI thereon.
  • the module can be understood as one large transistor, one piece or a plurality of transistors (chips) may be contained therein. More specifically, although the modules include 1-in-1 module, 2-in-1 module, 4-in-1 module, 6-in-1 module, etc., for example, a module configured to vertically connect two transistors to be contained on the module is called 2-in-1 module, a module configured to wire 2 sets of 2-in-1 module to be contained on the module is called 4-in-1 module, and a module configured to wire all to be contained on the module is called 6-in-1 module.
  • the power module 200 includes: a positive-side power terminal P (D 1 ) and a negative-side power terminal N (S 4 ) disposed at a first side of the ceramic substrate 8 covered with the resin layer 14 ; a gate terminal GT 1 and a source sense terminal SST 1 disposed at a second side adjacent to the first side; output terminals O (S 1 ) and O (D 1 ) disposed at a third side opposite to the first side; and a gate terminal GT 4 and a source sense terminal SST 4 disposed at a fourth side opposite to the second side.
  • the gate terminal GT 1 and the source sense terminal SST 1 are connected to the signal wiring pattern GL 1 for gate and the signal wiring pattern SL 1 for source in the MISFET Q 1 ; and the gate terminal GT 4 and the source sense terminal SST 4 are connected to the signal wiring pattern GL 4 for gate and the signal wiring pattern SL 4 for source in the MISFET Q 4 .
  • wires for gate GW 1 and GW 4 and wires for source sense SSW 1 and SSW 4 are respectively connected from the MISFETs Q 1 and Q 4 toward the gate signal wiring patterns GL 1 and GL 4 and the source sense signal wiring patterns SL 1 and SL 4 which are respectively disposed on the signal substrates 24 1 and 24 4 .
  • gate terminals GT 1 and GT 4 and source sense terminals SST 1 and SST 4 for external extraction are respectively connected to the signal wiring patterns GL 1 and GL 4 for gate and the signal wiring patterns SL 1 and SL 4 for source sense by soldering etc.
  • the signal substrates 24 1 and 24 4 are connected by soldering etc. on the ceramics substrate 8 .
  • FIG. 24 shows a bird's-eye view configuration before forming the resin layer 14 after forming upper surface plate electrodes 22 1 and 22 4 , in the module with the built-in half-bridge, in the power module 200 according to the additional embodiment 3. Note that the wires GW 1 and GW 4 for gate and the wires SSW 1 and SSW 4 for source sense are not shown in FIG. 24 .
  • the sources S 1 and S 4 of 4 chips of the MISFETs Q 1 and Q 4 respectively disposed in parallel are commonly connected with the upper surface plate electrodes 22 1 and 22 4 .
  • diodes may be respectively connected reversely in parallel between a drain D 1 and a source S 1 and between a drain D 4 and a source S 4 of the MISFETs Q 1 and Q 4 .
  • the sources S 1 and S 4 of 4 chips of the MISFETs Q 1 and Q 4 disposed in parallel are commonly connected with the upper surface plate electrodes 22 1 and 22 4 in an example shown in FIGS. 21-24 , the sources may be conducted to one another with the wire instead of the upper surface plate electrodes 22 1 and 22 4 .
  • the positive-side power terminal P and the negative-side power terminal N, and the gate terminals GT 1 and GT 4 and the source sense terminals SST 1 and SST 4 for external extraction can be formed of Cu, for example.
  • the signal substrates 241 and 244 can be formed by including a ceramics substrate.
  • the ceramic substrate may be formed by including Al 2 O 3 , AlN, SiN, AlSiC, or SiC of which at least the surface is insulation, for example.
  • Main wiring conductors (metallic substrates) 32 1 , 32 4 , and 32 n (EP) used for electrode patterns can be formed by including Cu, Al, or the like, for example.
  • Portions of pillar electrodes 25 1 and 25 4 and upper surface plate electrodes 22 1 and 22 4 configured to respectively connect between the sources S 1 and S 4 of the MISFETs Q 1 and Q 4 and the upper surface plate electrodes 22 1 and 22 4 may be formed by including CuMo, Cu, or the like, for example.
  • the wires GW 1 and GW 4 for gate and the wires SSW 1 and SSW 4 for source sense can be formed by including Al, AlCu, or the like, for example.
  • Wide-bandgap type elements such as SiC based power devices (e.g. SiC DIMISFET and SiC TMISFET), or GaN based power devices (e.g. GaN based FET, High Electron Mobility Transistor (HEMT)), can be applied as the MISFETs Q 1 and Q 4 .
  • power devices e.g. Si based MISFETs and IGBT, are also applicable thereto.
  • 4 chips of the MISFETs Q 1 are bonded via a bonding layer 2 under chip on the main wiring conductor 32 1 in the ceramic frame 10 1 disposed via a soldering layer etc. on the main wiring conductor 32 1 .
  • 4 chips of the MISFETs Q 4 are bonded via a bonding layer 2 under chip on the main wiring conductor 32 4 in the ceramic frame 10 4 disposed via a soldering layer etc. on the main wiring conductor 32 4 .
  • each of the ceramic frames 10 1 and 10 4 is filled up with a resin, and each of the 4 chips of the MISFETs Q 1 and Q 4 is sealed with the resin. Moreover, the whole module is packaged by the resin layer 14 so as to include the upper surface plate electrodes 22 1 and 22 4 , etc. The whole of the resin layer 14 is formed of a homogeneous material.
  • respective ceramic frames 10 1 and 10 4 are configured to collectively contain the respective MISFETs Q 1 and Q 4 , in the example shown in FIGS. 22 and 24 , but the respective ceramic frames 10 1 and 10 4 may be configured to individually contain the respective MISFETs Q 1 and Q 4 .
  • the principal portion of the power module 200 according to the additional embodiment 3 includes: a ceramics substrate 8 ; MISFETs Q 1 and Q 4 respectively bonded to main wiring conductors 32 1 and 32 4 on the ceramics substrate 8 ; ceramic frames 10 1 and 10 4 respectively disposed on the main wiring conductor 32 1 and 32 4 , the ceramic frames 10 1 and 10 4 configured to enclose the MISFETs Q 1 and Q 4 ; and resin layers 14 configured to respectively seal the MISFETs Q 1 and Q 4 inside the ceramic frames 10 1 and 10 4 , and to respectively seal the main wiring conductors 32 1 and 32 4 and the ceramics substrate 8 inside the ceramic frames 10 1 and 10 4 .
  • the same resin material as that of the embodiments and its modified examples 1-8 can be applied to the resin layer 14 , and the same configuration of the ceramic frame 10 as that of the embodiments and its modified examples 1-8 can be adopted into the ceramic frames 10 1 and 10 4 .
  • the block terminal electrodes 12 and 13 , the relaying substrate 18 , etc. may be applied instead of the wires GW 1 and GW 4 for gate and the wires SSW 1 and SSW 4 for source sense, in order to prevent wire breaking due to a thermal stress etc. and to obtain an improvement in reliability.
  • a simplification of the module fabrication process and a miniaturization of the module can be realized since the same fabrication method as that of the embodiments or other additional embodiments can be applied and therefore the module fabrication can be realized without attachment of a case. Also in the power module 200 according to the additional embodiment 3, since structural members, e.g. a case, are unnecessary, the number of parts is reduced, and thereby realizing cost reduction.
  • the low-cost power module having a simplified structure, easy to be fabricated through a simplified and easy process, and capable of improving mass productivity and realizing miniaturization thereof.
  • the power module can be easily fabricated and excellent also in mass productivity.
  • the power module 20 according to the embodiments.
  • the configuration in which the ceramic frame 10 is formed in the periphery of the semiconductor device 1 on the metallic pattern 3 is adopted, in order to reduce the difference between the CTE value of the metallic pattern 3 and the CTE value of the semiconductor device 1 also in the power module 20 explained hereinafter.
  • FIG. 25A shows a schematic circuit representative of an SiC MISFET of the 1-in-1 module, which is the power module 20 according to the embodiments.
  • FIG. 25B shows a schematic circuit representation of the IGBT of the 1-in-1 module.
  • a diode DI connected in reversely parallel to the MISFET Q is shown in FIG. 25A .
  • a main electrode of the MISFET Q is expressed with a drain terminal DT and a source terminal ST.
  • FIG. 25B a diode DI connected in reversely parallel to the IGBT Q is shown in FIG. 25B .
  • a main electrode of the IGBT Q is expressed with a collector terminal CT and an emitter terminal ET.
  • FIG. 26 shows a detailed circuit representative of the SiC MISFET of the 1-in-1 module, which is the power module 20 according to the embodiments.
  • the power module 20 includes a configuration of 1-in-1 module, for example. More specifically, one MISFET is contained in one module, and a maximum of 5 chips (five transistors) connected in parallel to one another can be mounted in one MISFET, as an example. Note that it is also possible to mount a part of five pieces of the chips for the diode DI thereon.
  • a sense MISFET Qs is connected to the MISFETQ in parallel.
  • the sense MISFET Qs is formed as a miniaturized transistor in the same chip as the MISFET Q.
  • reference numeral SS denotes a source sense terminal
  • reference numeral CS denotes a current sense terminal
  • reference numeral G denotes a gate signal terminal.
  • the sense MISFET Qs is formed as a miniaturized transistor in the same chip.
  • FIG. 27A shows a circuit representative of the SiC MISFET of the 1-in-1 module, which is the power module 20 T according to the embodiments.
  • FIG. 27A two MISFETs Q 1 and Q 4 , and diodes D 1 and D 4 connected in reversely parallel to the MISFETs Q 1 and Q 4 are built in one module.
  • reference numeral G 1 denotes a gate signal terminal of the MISFET Q 1
  • reference numeral S 1 denotes a source terminal of the MISFET Q 1
  • Reference numeral G 4 denotes a gate signal terminal of the MISFET Q 4
  • reference numeral S 4 denotes a source terminal of the MISFET Q 4
  • Reference numeral P denotes a positive side power input terminal
  • reference numeral N denotes a negative side power input terminal
  • reference numeral O denotes an output terminal.
  • FIG. 27B shows a circuit representative of the 2-in-1 module, which is the power module 20 T according to the embodiments.
  • reference numeral G 1 denotes a gate signal terminal of the IGBT Q 1
  • reference numeral E 1 denotes an emitter terminal of the IGBT Q 1
  • reference numeral G 4 denotes a gate signal terminal of the IGBT Q 4
  • reference numeral E 4 denotes an emitter terminal of the IGBT Q 4
  • Reference numeral P denotes a positive side power input terminal
  • reference numeral N denotes a negative side power input terminal
  • reference numeral O denotes an output terminal.
  • FIG. 28A shows a schematic cross-sectional structure of an SiC MISFET 110 , which is an example of a semiconductor device which can be applied to the power modules 20 and 20 T according to the embodiments
  • FIG. 28B shows a schematic cross-sectional structure of the IGBT 110 A.
  • the schematic cross-sectional structure of the SiC MISFET 110 includes: a semiconductor substrate 126 composed by including an n ⁇ type high resistivity layer; a p body region 128 formed on a front surface side of the semiconductor substrate 126 ; a source region 130 formed on a front side surface of the p body region 128 ; a gate insulating film 132 disposed on a front side surface of the semiconductor substrate 126 between the p body regions 128 ; a gate electrode 138 disposed on the gate insulating film 132 ; a source electrode 134 connected to the source region 130 and the p body region 128 ; an n + drain region 124 disposed on a back side surface opposite to the surface of the semiconductor substrate 126 ; and a drain electrode 136 connected to the n + type drain area 124 .
  • the semiconductor device may be composed by including a trench-gate-type n channel vertical SiC-TMISFET, etc., shown in FIG. 32 mentioned below.
  • a GaN based FET etc. can also be adopted thereinto, instead of the SiC MISFET. It is especially effective to adopt any one of an SiC-based or GaN-based power device, as the power modules 20 and 20 T according to the embodiments.
  • a wide-bandgap type semiconductor of which the bandgap energy is from 1.1 eV to 8 eV, for example, can be used for the semiconductor device applicable to the power modules 20 and 20 T according to the embodiments.
  • IGBT 110 A as an example of the semiconductor device applicable to the power modules 20 and 20 T according to the embodiments includes: a semiconductor substrate 126 composed by including an n ⁇ type high resistivity layer; a p body region 128 formed on a front surface side of the semiconductor substrate 126 ; an emitter region 130 E formed on a front side surface of the p body region 128 ; a gate insulating film 132 disposed on a front side surface of the semiconductor substrate 126 between the p body regions 128 ; a gate electrode 138 disposed on the gate insulating film 132 ; an emitter electrode 134 E connected to the emitter region 130 E and the p body region 128 ; a p + collector region 124 P disposed on a back side surface opposite to the surface of the semiconductor substrate 126 ; and a collector electrode 136 connected to the p + collector region 124 P.
  • the semiconductor device 110 composed by including the planar-gate-type n channel vertical IGBT is disclosed, the semiconductor device may be composed by including a trench-gate-type n channel vertical IGBT, etc.
  • FIG. 29 shows a schematic cross-sectional structure of an SiC MISFET 110 including a source pad electrode SP and a gate pad electrode GP, which is an example of the semiconductor device applicable to the power modules 20 and 20 T according to the embodiments.
  • the gate pad electrode GP is connected to the gate electrode 138 disposed on the gate insulating film 132
  • the source pad electrode SP is connected to the source electrode 134 connected to the source region 130 and the p body region 128 .
  • the gate pad electrode GP and the source pad electrode SP are disposed on an interlayer insulating film 144 for passivation which covers the surface thereof.
  • microstructural transistor structure may be formed in the semiconductor substrate 126 below the gate pad electrode GP and the source pad electrode SP in the same manner as the center portion shown in FIG. 28A or 29 .
  • the source pad electrode SP may be disposed to be extended onto the interlayer insulating film 144 for passivation, also in the transistor structure of the center portion.
  • FIG. 30 shows a schematic cross-sectional structure of an IGBT 110 A including a source pad electrode SP and a gate pad electrode GP, which is an example of the semiconductor device applied to the power modules 20 and 20 T according to the embodiments.
  • the gate pad electrode GP is connected to the gate electrode 138 disposed on the gate insulating film 132
  • the emitter pad electrode EP is connected to the emitter electrode 134 E connected to the emitter region 130 E and the p body region 128 .
  • the gate pad electrode GP and the emitter pad electrode EP are disposed on an interlayer insulating film 144 for passivation which covers the surface thereof.
  • microstructural IGBT structure may be formed in the semiconductor substrate 126 below the gate pad electrode GP and the emitter pad electrode EP in the same manner as the center portion shown in FIG. 28B or 30 .
  • the emitter pad electrode EP may be disposed to be extended onto the interlayer insulating film 144 for passivation, also in the IGBT structure of the center portion.
  • FIG. 31 shows a schematic cross-sectional structure of an SiC DIMISFET 110 , which is an example of a semiconductor device which can be applied to the power module 20 T according to the embodiments.
  • the SiC DIMISFET applicable to the power module 20 T includes: a semiconductor substrate 126 composed by including an n ⁇ type high resistivity layer; a p body region 128 formed on a front surface side of the semiconductor substrate 126 ; an n + source region 130 formed on a front side surface of the p body region 128 ; a gate insulating film 132 disposed on a front side surface of the semiconductor substrate 126 between the p body regions 128 ; a gate electrode 138 disposed on the gate insulating film 132 ; a source electrode 134 connected to the source region 130 and the p body region 128 ; an n + drain region 124 disposed on a back side surface opposite to the surface of the semiconductor substrate 126 ; and a drain electrode 136 connected to the n + type drain area 124 .
  • the p body region 128 and the n + source region 130 formed on the front side surface of the p body region 128 are formed with double ion implantation (DI), and the source pad electrode SP is connected to the source region 130 and the source electrode 134 connected to the p body region 128 .
  • a gate pad electrode GP (not shown) is connected to the gate electrode 138 disposed on the gate insulating film 132 .
  • the source pad electrode SP and the gate pad electrode GP are disposed on an interlayer insulating film 144 for passivation configured to cover the front side surface thereof.
  • FIG. 32 shows a schematic cross-sectional structure of an SiC TMISFET 110 , which is an example of a semiconductor device which can be applied to the power module 20 T according to the embodiments.
  • the SiC TMISFET applicable to the power circuit 20 T includes: a semiconductor substrate 126 N composed by including an n layer; a p body region 128 formed on a front surface side of the semiconductor substrate 126 N; an n + source region 130 formed on a front side surface of the p body region 128 ; a trench gate electrode 138 TG passing through the p body region 128 , the trench gate electrode 138 TG formed in the trench formed up to the semiconductor substrate 126 N via the gate insulating layer 132 and the interlayer insulating films 144 U and 144 B; a source electrode 134 connected to the source region 130 and the p body region 128 ; an n + type drain area 124 disposed on a back side surface of the semiconductor substrate 126 N opposite to the front side surface thereof; and a drain electrode 136 connected to the n + type drain area 124 .
  • a trench gate electrode 138 TG passing through the p body region 128 is formed in the trench formed up to the semiconductor substrate 126 N via the gate insulating layer 132 and the interlayer insulating films 144 U and 144 B; and the source pad electrode SP is connected to the source region 130 and the source electrode 134 connected to the p body region 128 .
  • a gate pad electrode GP (not shown) is connected to the gate electrode 138 disposed on the gate insulating film 132 .
  • the source pad electrode SP and the gate pad electrode GP are disposed on an interlayer insulating film 144 U for passivation configured to cover the front side surface thereof.
  • channel resistance RJ FET accompanying the junction type FET (JFET) effect as the SiC DIMISFET is not formed.
  • body diodes BD are respectively formed between the p body regions 128 and the semiconductor substrates 126 N, in the same manner as FIG. 31 .
  • FIG. 33A shows an example of a circuit configuration in which the SiC MISFET is applied as a semiconductor device, and a snubber capacitor C is connected between the power terminal PL and the earth terminal (ground terminal) NL, in a circuit configuration of a three-phase AC inverter 140 composed using the power module 20 T according to the embodiments.
  • FIG. 33B shows an example of a circuit configuration in which the IGBT is applied as a semiconductor device, and a snubber capacitor C is connected between the power terminal PL and the earth terminal (ground terminal) NL, in a circuit configuration of a three-phase AC inverter 140 A composed using the power module 20 T according to the embodiments.
  • Ldi/dt When connecting the power module 20 T according to the embodiments to the power source E, large surge voltage Ldi/dt is produced by an inductance L included in a connection line due to a high switching speed of the SiC MISFET and IGBT.
  • the surge voltage Ldi/dt changes dependent on a value of the inductance L
  • the surge voltage Ldi/dt is superimposed on the power source E.
  • Such a surge voltage Ldi/dt can be absorbed by the snubber capacitor C connected between the power terminal PL and the earth terminal (ground terminal) NL.
  • the three-phase AC inverter 140 includes a gate drive unit 150 , a power module unit 152 connected to the gate drive unit 150 , and a three-phase AC motor unit 154 .
  • U-phase, V-phase, and W-phase inverters are respectively connected to the three-phase AC motor unit 54 so as to correspond to U phase, V phase, and W phase of the three-phase AC motor unit 154 , in the power module unit 152 .
  • the gate drive unit 150 is connected to the SiC MISFETs Q 1 and Q 4 , SiC MISFETs Q 2 and Q 5 , and the SiC MISFETs Q 3 and Q 6 .
  • the power module unit 152 includes the SiC MISFETs (Q 1 and Q 4 ), (Q 2 and Q 5 ), and (Q 3 and Q 6 ) having inverter configurations connected between a positive terminal (+) and a negative terminal ( ⁇ ) to which the converter 148 in a power supply or a storage battery (E) 146 is connected. Moreover, flywheel diodes D 1 -D 6 are respectively connected reversely in parallel between the source and the drain of the SiC MISFETs Q 1 -Q 6 .
  • the three-phase AC inverter 140 A includes a gate drive unit 150 A, a power module unit 152 A connected to the gate drive unit 150 A, and a three-phase AC motor unit 154 A.
  • U-phase, V-phase, and W-phase inverters are respectively connected to the three-phase AC motor unit 152 A so as to correspond to U phase, V phase, and W phase of the three-phase AC motor unit 154 A, in the power module unit 152 A.
  • the gate drive unit 150 A is connected to the IGBTs Q 1 and Q 4 , IGBTs Q 2 and Q 5 , and the IGBTs Q 3 and Q 6 .
  • the power module unit 152 A includes the IGBTs (Q 1 and Q 4 ), (Q 2 and Q 5 ), and (Q 3 and Q 6 ) having inverter configurations connected between a positive terminal (+) and a negative terminal ( ⁇ ) to which the converter 148 A in a storage battery (E) 146 A is connected. Moreover, flywheel diodes D 1 -D 6 are respectively connected reversely in parallel between the emitter and the collector of the IGBTs Q 1 -Q 6 .
  • the power module 20 T can be formed as any one selected from the group consist of 1-in-1 module, 2-in-1 module, 4-in-1 module, 6-in-1 module, and 7-in-1 module.
  • the power module easy to be fabricated, capable of suppressing the degradation of the bonded portion and improving reliability; and the inverter equipment on which such a power module is mounted, also when adopting the transfer-mold type power module.
  • the embodiments cover a variety of embodiments and the like, whether described or not.
  • the power module according to the embodiments can be used for manufacturing techniques for power modules, e.g. IGBT modules, diode modules, MIS modules (Si, SiC, GaN), and the like, and can be applied to wide applicable fields, e.g. inverters for HEV/EV, inverter and converters for industrial applications, etc.

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US15/863,537 2015-07-06 2018-01-05 Power module and inverter equipment Abandoned US20180138100A1 (en)

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US10748826B2 (en) 2020-08-18
WO2017006771A1 (fr) 2017-01-12
US20190252279A1 (en) 2019-08-15

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