US20180083053A1

US20180083053A1 - Solid-state image sensor and camera

Info

Publication number: US20180083053A1
Application number: US15/827,333
Authority: US
Inventors: Takehiko Soda
Original assignee: Canon Inc
Current assignee: Canon Inc
Priority date: 2013-04-15
Filing date: 2017-11-30
Publication date: 2018-03-22
Also published as: US9881950B2; US20140307151A1; JP6162999B2; JP2014207390A

Abstract

The solid-state image sensor includes image sensing pixels, first and second focus detection pixels configured to respectively detect lights passing through different regions of a pupil of an image sensing lens. The sensor includes a semiconductor substrate including photoelectric converters of the image sensing pixels, a photoelectric converter and a first well contact region of the first focus detection pixel, and a photoelectric converter and a second well contact region of the second focus detection pixel, a first contact plug electrically connected to the first well contact region, and a second contact plug electrically connected to the second well contact region. The relative position of the first well contact region in the first focus detection pixel differs from a relative position of the second well contact region in the second focus detection pixel.

Description

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to a solid-state image sensor and a camera.

Description of the Related Art

There is known a technique of implementing focus detection without using any dedicated automatic focus detection (AF) sensor by making a solid-state image sensor used in a digital video camera, digital still camera, or the like have a phase-difference detection function. For example, the solid-state image sensor disclosed in Japanese Patent Laid-Open No. 2011-60815 has openings formed in the light shielding layers of some pixels so as to have eccentric centers relative to the optical axes of microlenses, thereby dividing the pupil of an image sensing lens.
A solid-state image sensor is provided with a well contact region for fixing the potential of a well in which circuit elements such as a photoelectric converter and a transistor are formed. A reference potential line is electrically connected to the well contact region via a contact plug. Japanese Patent Laid-Open No. 2011-60815 has no description or suggestion about how to arrange well contact regions.

SUMMARY OF THE INVENTION

The present invention provides the advantageous placement of well contact regions in a solid-state image sensor having a focus detection function.
One of aspects of the present invention provides a solid-state image sensor including a plurality of image sensing pixels configured to sense an image of an object, a first focus detection pixel configured to detect light passing through a first region of a pupil of an image sensing lens, and a second focus detection element configured to detect light passing through a second region different from the first region of the pupil, the sensor comprising: a semiconductor substrate including photoelectric converters of the plurality of image sensing pixels, a photoelectric converter and a first well contact region of the first focus detection pixel, and a photoelectric converter and a second well contact region of the second focus detection pixel; a first light shielding portion configured to define the first region and shield the first well contact region from light; a second light shielding portion configured to define the second region and shield the second well contact region from light; a first contact plug electrically connected to the first well contact region; and a second contact plug electrically connected to the second well contact region, wherein a relative position of the first well contact region in the first focus detection pixel with respect to an element included in the first focus detection pixel differs from a relative position of the second well contact region in the second focus detection pixel with respect to an element corresponding to the element included in the first focus detection pixel.
Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram exemplarily showing the circuit arrangement of one pixel of a solid-state image sensor according to one embodiment of the present invention;

FIGS. 2A and 2B are views showing part of the pixel array of a solid-state image sensor according to the first embodiment of the present invention;

FIGS. 3A and 3B are views showing part of the pixel array of a solid-state image sensor according to the second embodiment of the present invention;

FIGS. 4A and 4B are views showing part of the pixel array of a solid-state image sensor according to the third embodiment of the present invention; and

FIGS. 5A and 5B are views showing a comparative example.

DESCRIPTION OF THE EMBODIMENTS

A solid-state image sensor according to the present invention includes a plurality of image sensing pixels for sensing an image of an object, a plurality of first focus detection pixels which detect light passing through the first region of the pupil of an image sensing lens, and a plurality of second focus detection pixels which detect light passing through the second region different from the first region of the pupil. It is possible to detect a focus by a phase-difference detection method based on outputs from the plurality of first focus detection pixels and outputs from the plurality of second focus detection pixels. The solid-state image sensor of the present invention can be formed as a MOS solid-state image sensor or CCD solid-state image sensor.
A case in which the present invention is applied to a MOS solid-state image sensor as an embodiment of the present invention will be described below. FIG. 1 exemplarily shows the circuit arrangement of one pixel PIX of a solid-state image sensor according to one embodiment of the present invention. Image sensing pixels, the first focus detection pixels, and the second focus detection pixels can have a circuit arrangement like that shown in FIG. 1. The pixel PIX includes a photoelectric converter 101. The photoelectric converter 101 can be, for example, a photodiode. The photoelectric converter has a charge accumulation region for accumulating charges generated by photoelectric conversion. In the case shown in FIG. 1, the pixel PIX accumulates electrons, of the electrons and holes which are generated by photoelectric conversion, and outputs a signal corresponding to the amount of electrons as a pixel signal. However, the pixel PIX may be configured to accumulate holes and output a signal corresponding to the amount of holes as a pixel signal.
The pixel PIX can include a transfer transistor 102 which transfers the charges accumulated in the photoelectric converter 101 to a floating diffusion FD. The pixel PIX can also include an amplification transistor 105 which outputs a signal corresponding to the amount of charges transferred to the pixel PIX or the floating diffusion FD to a column signal line 110. In this case, one end of a current source 111 is connected to the column signal line 110. The amplification transistor 105 and the current source 111 can constitute a source follower circuit. A potential V2 can be applied to the other end of the current source 111. The pixel PIX can include a reset transistor 104 which resets the potential of the floating diffusion FD. The pixel PIX may include a selection transistor 106. A vertical scanning circuit (not shown) activates the selection transistor 106 to set the pixel PIX in a selected state. In the scheme of setting the pixel PIX in a selected or unselected state depending on the potential set for the floating diffusion FD, the selection transistor 106 is not required. The selection transistor 106 can be arranged between, for example, the amplification transistor 105 and the column signal line 110. A potential V1 can be applied to the drains of the reset transistor 104 and amplification transistor 105.
A reference potential such as a ground potential is applied to the photoelectric converter 101, the transfer transistor 102, the amplification transistor 105, the reset transistor 104, and the selection transistor 106 via well contact regions of the semiconductor substrate and the contact plugs connected to them. If the photoelectric converter 101 is formed from a photodiode and accumulates electrons in the cathode, a ground potential 112 is applied to the anode via a well contact region formed in a well and the contact plug connected to the region. If the transistors 102, 104, 105, and 106 are formed from NMOS transistors, the ground potential 112 is applied to them as a substrate bias via well contact regions formed in wells of the semiconductor substrate and the contact plugs connected to the regions.
FIG. 2A shows the layout (plan view) of part (four pixels) of the pixel array of the solid-state image sensor according to the first embodiment of the present invention. More specifically, FIG. 2A shows two image sensing pixels 202A and 202B, a first focus detection pixel 201A, and a second focus detection pixel 201B. The first focus detection pixel 201A detects light passing through a first region of the pupil of the image sensing lens. The second focus detection pixel 201B detects light passing through a second region different from the first region of the pupil. FIG. 2B is a sectional view taken along a line A-A in FIG. 2A.
The first focus detection pixel 201A includes a photoelectric converter 206A, a transfer transistor, a selection transistor, an amplification transistor, and a reset transistor. The second focus detection pixel 201B includes a photoelectric converter 206B, a transfer transistor, a selection transistor, an amplification transistor, and a reset transistor. Each of the image sensing pixels 202A and 202B includes a photoelectric converter 206C, a transfer transistor, a selection transistor, an amplification transistor, and a reset transistor. The transfer transistors, the selection transistors, the amplification transistors, and the reset transistors respectively include gate electrodes 213, 203, 204, and 205.
The photoelectric converter 206A of the first focus detection pixel 201A can be constituted by, for example, a p-type surface region 219A, an n-type charge accumulation region 220A, and a p-type well 230. Like the photoelectric converter 206A of the first focus detection pixel 201A, the photoelectric converter 206B of the second focus detection pixel 201B can be constituted by a p-type surface region, an n-type charge accumulation region, and a p-type well 230. The photoelectric converters 206C of the image sensing pixels 202A and 202B each can be constituted by a p-type surface region 219C, an n-type charge accumulation region 220C, and a p-type well 230.
The solid-state image sensor includes a semiconductor substrate SB having the p-type well 230. The semiconductor substrate SB includes an element isolation 209. The element isolation 209 defines an active region 208. The element isolation 209 can have an isolation structure including an insulator such as an STI (Shallow Trench Isolation) or LOCOS (Local Oxidation of Silicon). The active region 208 includes, for example, the surface regions of the photoelectric converters 206A, 206B, and 206C, a floating diffusion 207, and the source, drain, and channel regions of each transistor. In addition, the active region 208 includes a first well contact region 215A of the first focus detection pixel 201A, a second well contact region 215B of the second focus detection pixel 201B, and third well contact regions 215C of the image sensing pixels 202A and 202B. In this embodiment, well contact regions are arranged in only some image sensing pixels. However, well contact regions may be arranged in all the image sensing pixels.
In the case shown in FIGS. 2A and 2B, the selection transistor, amplification transistor, and reset transistor of each pixel are formed by arranging gate electrodes 203, 204, and 205 on one active region 208 at predetermined intervals, with the respective transistors commonly having source and drain regions. Part or all of the element isolation 209 may be formed by p-n junction isolation. In this case, a plurality of pixels or all pixel elements can be arranged in one continuous active region 208.
A first contact plug 210A is electrically connected to the first well contact region 215A to supply a ground potential to the active region 208 of the first focus detection pixel 201A. A ground line (metal wiring pattern) 212A is electrically connected to the first contact plug 210A. Likewise, a second contact plug 210B is electrically connected to the second well contact region 215B to supply a ground potential to the active region 208 of the second focus detection pixel 201B. A ground line (metal wiring pattern) 212B is electrically connected to the second contact plug 210B. The ground line 212A includes the first light shielding portion which shields the first well contact region 215A from light, while defining the first region described above in the pupil of the image sensing lens. The ground line 212B includes the second light shielding portion which shields the second well contact region 215B from light, while defining the second region described above in the pupil of the image sensing lens. Phase difference detection by pupil division is implemented by detecting light passing through the first region of the image sensing lens using the first focus detection pixel 201A, and detecting light passing through the second region of the image sensing lens using the second focus detection pixel 201B, in the above manner.
The ground lines 212A and 212B can be formed as part of a wiring structure 240 including wiring patterns, contact plugs, and via plugs. Color filters 221 and/or microlenses 204 can be arranged on the wiring structure 240.
The first focus detection pixel 201A and the second focus detection pixel 201B constitute a pair of pixels for phase difference detection. In the first focus detection pixel 201A and the second focus detection pixel 201B constituting a pair for phase difference detection, the photoelectric converters are arranged at different relative positions. Accordingly, the relative position of the first well contact region 215A in the first focus detection pixel 201A with respect to a given element differs from the relative position of the second well contact region 215B in the second focus detection pixel 201B with respect to the corresponding pixel. That is, consider that the layout of the first focus detection pixel 201A is translated and is further rotated and reversed, as needed, so as to overlap a given element in the first focus detection pixel 201A with the corresponding element in the second focus detection pixel 201B. In this case, the first well contact region 215A is moved to a position different from that of the second well contact region 215B of the second focus detection pixel 201B. In addition, the relative position of the first contact plug 210A in the first focus detection pixel 201A differs from the relative position of the second contact plug 210B in the second focus detection pixel 201B. Differentiating the relative positions of the well contact regions (or the contact plugs) in the first focus detection pixel 201A and the second focus detection pixel 201B, which constitute a pair for phase difference detection, is advantageous in improving the degree of freedom in layout.
The ground lines 212A and 212B can be formed as part of the wiring structure 240 including wiring patterns, contact plugs, and via plugs. The color filters 221 and/or the microlenses 204 can be arranged on the wiring structure 240.
A third contact plug 211A is electrically connected to the third well contact region 215C of the image sensing pixel 202A to supply a ground potential to the active region 208 of the image sensing pixel 202A. The ground line (metal wiring pattern) 212A is electrically connected to the third contact plug 211A. Likewise, a third contact plug 211B is electrically connected to the third well contact region 215C of the image sensing pixel 202B to supply a ground potential to the active region 208 of the image sensing pixel 202B. The ground line (metal wiring pattern) 212B is electrically connected to the third contact plug 211A.
The image sensing pixel 202A and the image sensing pixel 202B can have symmetrical structures. For example, such structures include structures having translational symmetry, rotational symmetry, and mirror symmetry and a structure having a combination thereof. In this embodiment, the two image sensing pixels 202A and 202B have a translational symmetrical structure. In this case, the relative position of the third well contact region 215C in the image sensing pixel 202A coincides with the relative position of the third well contact region 215C in the image sensing pixel 202B. Alternatively, the image sensing pixel 202A and the image sensing pixel 202B may have structures having no symmetry to each other. If, for example, the image sensing pixel 202A and the image sensing pixel 202B share an amplification transistor, the image sensing pixel 202A and the image sensing pixel 202B can have structures having no symmetry to each other.
In this embodiment, the relative position of the third well contact region 215C in the image sensing pixel 202A (202B) with respect to a given element differs from the relative position of the first well contact region 215A in the first focus detection pixel 201A with respect to the corresponding element. That is, consider a case in which the layout of the first focus detection pixel 201A is translated and is further rotated and reversed, as needed, to overlap a given element in the first focus detection pixel 201A with the corresponding element in the image sensing pixel 202A (202B). In this case, the first well contact region 215A is moved to a position different from that of the third well contact region 215C in the image sensing pixel 202A. The elements corresponding to each other are elements or portions such as a reset transistor in the first focus detection pixel and a reset transistor in an image sensing element, which have similar functions in the two different pixels. In addition, the relative position of the third well contact region 215C in the image sensing pixel 202A (202B) differs from the relative position of the second well contact region 215B in the second focus detection pixel 201B.
The impurity concentration of the well contact regions 215A, 215B, and 215C is higher than that of the well 230. Providing the well contact regions 215A, 215B, and 215C can decrease the contact resistance with the contact plugs 210A, 210B, and 211A (211B). In the case shown in FIGS. 2A and 2B, a well contact region and the surface region of a photoelectric converter are arranged in different active regions, respectively. In other words, the well contact region is electrically isolated from the surface region of the photoelectric converter by the element isolation 209 including an insulator. However, this is a merely an example, and the well contact region and the surface region of the photoelectric converter may be arranged in the same active region.
The well 230 may be shared by a plurality of pixels or all pixels or may be provided for each pixel. According to the above description, a ground potential is supplied to the well 230 via the well contact regions 215A, 215B, and 215C, but an arbitrary potential other than a ground potential can be supplied to the p-type well.
Since the above case has exemplified the solid-state image sensor which accumulates electrons in the photoelectric converters, the well 230 is of the p type. However, in a solid-state image sensor designed to accumulate holes in photoelectric converters, the p type and n type in the above case are interchanged.
The potential of a well in which an amplification transistor and a reset transistor are arranged is an important factor when determining the operation characteristics of the respective transistors. The existence of an uneven potential distribution in a region in which a pixel array is arranged can generate shading in a sensed image. It is therefore preferable to make the well, in which a pixel array is arranged, have an equipotential distribution by arranging many contact plugs in the well. On the other hand, arranging many contact plugs may cause dark currents to flow into photoelectric converters via the contact plugs and the well contact regions. The generation of dark currents in the photoelectric converters of image sensing pixels adversely affects an image in a dark period, in particular. Since a signal from a focus detection pixel is not used as a signal for directly forming an image, it is therefore more important to suppress a dark current generated in an image sensing pixel than to suppress a dark current generated in a focus detection pixel. Therefore, it is necessary to make the suppression of shading and the suppression of a dark current generated in an image sensing pixel compatible.
FIG. 5A shows the layout (plan view) of part (four pixels) of the pixel array of a solid-state image sensor according to a comparative example. FIG. 5B is a sectional view taken along a line A-A in FIG. 5A. In the comparative example, the relative positions of well contact regions 215A and 215B in focus detection pixels 201A and 201B coincide with the relative positions of well contact regions 215C in image sensing pixels 202A and 202B. This arrangement is advantageous in suppressing shading by making a well 230 have a uniform potential. However, the arrangement is disadvantageous in suppressing dark currents 217 flowing from contact plugs 210A and 210B for the focus detection pixel 201A and 201B and the well contact regions 215A and 215B into a photoelectric converter 206C. For example, the dark currents 217 flowing from the contact plug 210A for the focus detection pixel 201A and the well contact region 215A into the photoelectric converter 206C in the adjacent image sensing pixel 202A can adversely affect an image in a dark period.
Individually determining the relative positions of well contact regions in a focus detection pixel and an image sensing pixel as in the first embodiment is advantageous in making the suppression of shading and the suppression of a dark current in the image sensing pixel compatible. As compared with the case shown in FIGS. 5A and 5B, the first embodiment enables large distances to be set from the contact plug 210A for the focus detection pixel 201A and the well contact region 215A to the photoelectric converter 206C in the adjacent image sensing pixel 202A. The larger the distance between the well contact region 215A and the photoelectric converter 206C, the smaller a dark current flowing from the well contact region 215A to the photoelectric converter 206C. It is therefore possible to suppress a dark current to the photoelectric converter 206C. In addition to this method, there is available a method of suppressing a dark current by placing a barrier for preventing the entrance of charges between the well contact region 215A and the photoelectric converter 206C of the adjacent image sensing pixel 202A. The placement of such a barrier can be performed without any layout constraints, and hence is advantageous in suppressing a dark current.
In addition, arranging the well contact regions 215A and 215B in the regions light-shielded by the ground lines 212A and 212B in the focus detection pixels is advantageous in suppressing dark currents in the adjacent image sensing pixels.
The second embodiment of the present invention will be described with reference to FIGS. 3A and 3B. FIG. 3A shows the layout (plan view) of part (four pixels) of the pixel array of a solid-state image sensor according to the second embodiment of the present invention. More specifically, FIG. 3A shows two image sensing pixels 202A and 202B, a first focus detection pixel 201A, and a second focus detection pixel 201B. The first focus detection pixel 201A detects light passing through the first region of the pupil of an image sensing lens. The second focus detection pixel 201B detects light passing through the second region different from the first region of the pupil. FIG. 3B is a sectional view taken along a line A-A in FIG. 3A. Note that particulars that are not described in the second embodiment can comply with the first embodiment
In the second embodiment, the focus detect pixels 201A and 201B are provided with well contact regions and contact plugs for supplying a ground potential to a well 230. However, the second embodiment differs from the first embodiment in that some image sensing pixels 202A and 202B are not provided with well contact region contact plugs.
Providing no well contact regions and contact plugs for the image sensing pixels 202A and 202B can suppress generation of dark currents in the image sensing pixels 202A and 202B due to well contact regions and contact plugs. If the degree of shading caused by the potential distribution of the well 230 falls within an allowable range, there is no need to arrange well contact regions and contact plugs in all the focus detection pixels including the focus detection pixels 201A and 201B. That is, if the degree of shading falls within the allowable range, well contact regions and contact plugs may be arranged in only some of the plurality of focus detection pixels. Consider a case in which the layout of the focus detection pixel 201A is translated and is further rotated and reversed, as needed, so as to overlap some element of the first focus detection pixel 201A with the corresponding element of the image sensing pixel 202A (202B) having no well contact region. In this case, a first well contact region 215A is moved to a position different from that of a well contact region. Therefore, the relative position of the first well contact region 215A in the first focus detection pixel 201A with respect to a given element differs from the image sensing pixel 202A (202B).
If the gate area of an amplification transistor is small, the generation of 1/f noise may adversely affect pixel characteristics. In the second embodiment, since no contact plug for supplying a ground potential to an image sensing pixel is arranged, it is possible to increase the gate area of an amplification transistor of an image sensing pixel accordingly as compared with the case in which a contact plug is arranged in the image sensing pixel. This can suppress the generation of 1/f noise. In addition, since the area of the photoelectric converter of an image sensing pixel can be increased as compared with the case in which a contact plug is arranged in an image sensing pixel, it is possible to improve the sensitivity of the image sensing pixel.
The third embodiment of the present invention will be described with reference to FIGS. 4A and 4B. FIG. 4A shows the layout (plan view) of part (four pixels) of the pixel array of a solid-state image sensor according to third embodiment of the present invention. More specifically, FIG. 4A shows two image sensing pixels 202A and 202B, a first focus detection pixel 201A, and a second focus detection pixel 201B. The first focus detection pixel 201A detects light passing through the first region of the pupil of an image sensing lens. The second focus detection pixel 201B detects light passing through the second region different from the first region of the pupil. FIG. 4B is a sectional view taken along a line A-A in FIG. 4A. Note that particulars that are not described in the third embodiment can comply with the first embodiment.
The third embodiment differs from the first embodiment in that contact plugs 210A and 210B for the focus detection pixels 201A and 201B are connected to surface regions 219A of photoelectric converters 206A and 206B (the surface region of the photoelectric converter 206B is not shown) of the focus detection pixels 201A and 201B. In the third embodiment, since well contact regions 215A and 215B are not isolated from the photoelectric converters 206A and 206B by element isolation 209, it is possible to increase the regions of the photoelectric converters 206A and 206B. This contributes to an increase in the dynamic ranges of the first focus detection pixels 201A and 201B.
The camera incorporated in a solid-state image sensor according to each embodiment described above will be exemplarily described as an application example of the solid-state image sensor. The concept of the camera includes not only an apparatus mainly designed to perform imaging but also an apparatus including an imaging function as an auxiliary function (for example, a personal computer or a portable terminal). The camera includes a solid-state image sensor according to the present invention exemplified as the above embodiment and a processor which processes the signal output from the solid-state image sensor. The processor can include, for example, an A/D converter and a processor which processes the digital data output from the A/D converter.
While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.
This application claims the benefit of Japanese Patent Application No. 2013-085268, filed Apr. 15, 2013, which is hereby incorporated by reference herein in its entirety.

Claims

1.-13. (canceled)

14. A solid-state image sensor comprising an image sensing pixel configured to sense an image of an object, a first pixel configured to detect light passing through a first region of a pupil of an image sensing lens, and a second pixel configured to detect light passing through a second region of the pupil, which is different from the first region, wherein

the image sensing pixel includes a photoelectric converter, and

the first pixel includes a photoelectric converter, a first semiconductor region through which a well potential is supplied, and a transistor,

wherein the photoelectric converter of the first pixel and the first semiconductor region of the first pixel are arranged in a region in the first pixel, the region of the first pixel corresponding to a region in the image sensing pixel, and the photoelectric converter of the image sensing pixel being arranged in the region in the image sensing pixel, and

wherein the transistor of the first pixel is arranged in a region between the photoelectric convertor of the image sensing pixel and the first semiconductor region of the first pixel.

15. The sensor according to claim 14, wherein the first pixel includes a first light shielding portion configured to shield the first semiconductor region from light.

16. The sensor according to claim 15, wherein the first pixel further includes a first contact plug electrically connected to the first semiconductor region, the first contact plug being electrically connected to the first light shielding portion.

17. The sensor according to claim 14, wherein the first semiconductor region is arranged in an active region in which the photoelectric convertor of the first pixel is arranged.

18. The sensor according to claim 14, wherein the first pixel and the second pixel constitute a pair for phase difference detection.

19. The sensor according to claim 14, wherein the transistor is one of a reset transistor, an amplification transistor, a transfer transistor, and a selection transistor.

20. The sensor according to claim 14, wherein the second pixel includes a photoelectric converter, a second semiconductor region through which a well potential is supplied,

wherein the photoelectric converter of the second pixel and the second semiconductor region of the second pixel are arranged in a region in the second pixel, the region in the second pixel corresponding to a region in the image sensing pixel, and the photoelectric converter of the image sensing pixel being arranged in the region in the image sensing pixel.

21. The sensor according to claim 20, wherein a position of the first semiconductor region within the first pixel relative to an amplification transistor of the first pixel is different from a position of the second semiconductor region within the second pixel relative to an amplification transistor of the second pixel.

22. The sensor according to claim 20, wherein the second pixel further includes a second light shielding portion configured to shield the second semiconductor region from light, and a second contact plug electrically connected to the second semiconductor region.

23. The sensor according to claim 22, wherein the second contact plug is electrically connected to the first light shielding portion.

24. A camera comprising:

a solid-state image sensor defined in claim 14; and

a processing unit configured to process a signal output from the solid-state image sensor.