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US20180076065A1 - Integrated system for semiconductor process - Google Patents

Integrated system for semiconductor process Download PDF

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Publication number
US20180076065A1
US20180076065A1 US15/418,506 US201715418506A US2018076065A1 US 20180076065 A1 US20180076065 A1 US 20180076065A1 US 201715418506 A US201715418506 A US 201715418506A US 2018076065 A1 US2018076065 A1 US 2018076065A1
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Prior art keywords
chamber
transfer chamber
coupled
chambers
substrate
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Abandoned
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US15/418,506
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English (en)
Inventor
Xinyu Bao
Hua Chung
Schubert S. Chu
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Applied Materials Inc
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Applied Materials Inc
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Priority to US15/418,506 priority Critical patent/US20180076065A1/en
Assigned to APPLIED MATERIALS, INC. reassignment APPLIED MATERIALS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BAO, XINYU, CHU, SCHUBERT S., CHUNG, HUA
Priority to TW106120104A priority patent/TWI821158B/zh
Priority to TW110124719A priority patent/TWI840682B/zh
Publication of US20180076065A1 publication Critical patent/US20180076065A1/en
Priority to US16/591,354 priority patent/US11164767B2/en
Abandoned legal-status Critical Current

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    • H10P72/0468—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B08—CLEANING
    • B08B—CLEANING IN GENERAL; PREVENTION OF FOULING IN GENERAL
    • B08B7/00—Cleaning by methods not provided for in a single other subclass or a single group in this subclass
    • B08B7/0035—Cleaning by methods not provided for in a single other subclass or a single group in this subclass by radiant energy, e.g. UV, laser, light beam or the like
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/04—Pattern deposit, e.g. by using masks
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/18—Epitaxial-layer growth characterised by the substrate
    • C30B25/186—Epitaxial-layer growth characterised by the substrate being specially pre-treated by, e.g. chemical or physical means
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
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    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32458—Vessel
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    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
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    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32798—Further details of plasma apparatus not provided for in groups H01J37/3244 - H01J37/32788; special provisions for cleaning or maintenance of the apparatus
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67184—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the presence of more than one transfer chamber
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
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    • H01L29/66795—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
    • H10D64/0112—
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/32—Processing objects by plasma generation
    • H01J2237/33—Processing objects by plasma generation characterised by the type of processing
    • H01J2237/334—Etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H10P72/0464—

Definitions

  • Implementations of the present disclosure generally relate to methods and apparatuses for epitaxial deposition on substrate surfaces.
  • Integrated circuits are formed in and on silicon and other semiconductor substrates.
  • substrates are made by growing an ingot from a bath of molten silicon, and then sawing the solidified ingot into multiple wafers.
  • An epitaxial silicon layer may then be formed on the monocrystalline silicon wafer to form a defect-free silicon layer that may be doped or undoped.
  • Semiconductor devices, such as transistors, are manufactured from the epitaxial silicon layer. The electrical properties of the formed epitaxial silicon layer will generally be better than the properties of the monocrystalline silicon substrate.
  • surfaces of the monocrystalline silicon and the epitaxial silicon layer are susceptible to contamination when exposed to typical wafer fabrication facility ambient conditions. For example, contaminants present in the ambient environment may deposit on the monocrystalline surface. Additionally, the various chemical interactions utilized to form the semiconductor components may interact during manufacturing and contaminate or degrade both the chamber components and the substrate. Moreover, current process systems suffer from low throughput when manufacturing substrates having advanced device integration schemes.
  • a cluster tool for processing a substrate includes a first transfer chamber, a pre-clean chamber coupled to the first transfer chamber, an etch chamber coupled to the first transfer chamber, a second transfer chamber coupled to the first transfer chamber, one or more pass through chambers disposed between the first transfer chamber and the second transfer chamber, one or more outgassing chambers coupled to the second transfer chamber, and one or more deposition chambers coupled to the second transfer chamber.
  • a cluster tool in another implementation, includes a first transfer chamber, a pre-clean chamber coupled to the first transfer chamber, an etch chamber coupled to the first transfer chamber, a second transfer chamber coupled to the first transfer chamber, and four epitaxial deposition chambers coupled to the second transfer chamber.
  • a cluster tool in another implementation, includes a first transfer chamber, a pre-clean chamber coupled to the first transfer chamber, an etch chamber coupled to the first transfer chamber, a second transfer chamber coupled to the first transfer chamber, two pass through chambers disposed between the first transfer chamber and the second transfer chamber, one or more outgassing chambers coupled to the second transfer chamber, and four epitaxial deposition chambers coupled to the second transfer chamber.
  • FIG. 1 is a flow chart illustrating a method in accordance with one implementation of the present disclosure.
  • FIG. 2 is a schematic top view of a process system that can be used to complete the processing sequence illustrated in FIG. 1 according to implementations described herein.
  • the following disclosure generally describes methods and apparatuses for epitaxial deposition on substrate surfaces. Implementations described herein will be described below in reference to cleaning, etching and deposition processes that can be carried out using systems available from Applied Materials, Inc. of Santa Clara, Calif. Other tools capable of performing these cleaning, etching and deposition processes may also be adapted to benefit from the implementations described herein. In addition, any system enabling the cleaning, etching and deposition processes described herein can be utilized advantageously according to the implementations described herein.
  • the apparatus described herein is illustrative and should not be construed or interpreted as limiting the scope of the implementations described herein.
  • FIG. 1 illustrates a method 100 in accordance with one implementation of the present disclosure.
  • Method 100 starts at operation 110 , in which one or more substrates are loaded to the system.
  • the substrates are loaded into the system using pods.
  • the pods typically are front opening unified pods (FOUP) that are accessible from a clean room.
  • FOUP front opening unified pods
  • a substrate is transferred to a first process chamber to remove the native oxide on a surface of a substrate by a cleaning process.
  • the substrate may include a silicon-containing material and the surface may include a material, such as silicon (Si), germanium (Ge) or silicon germanium alloys (SiGe).
  • the Si, Ge, or SiGe surface may have an oxide layer, such as native oxide layer, disposed thereon.
  • the substrate may be a semiconductor substrate with devices formed thereon.
  • the substrate has a plurality of semiconductor fins formed thereon and each semiconductor fin may be located between two trenches formed in a dielectric material.
  • the native oxide layer may be formed on the plurality of fins and in the trenches.
  • operation 120 is performed in a process region of a first process chamber.
  • the first process chamber is positioned on a cluster tool allowing for transfer of the substrate without exposing the substrate to atmosphere (e.g., in a vacuum environment.)
  • Suitable cleaning processes include sputter etch processes, plasma dry etch processes, or combinations thereof.
  • Exemplary cleaning processes include NF 3 /NH 3 plasma-based processes or NF 3 /NH 3 inductively coupled plasma processes.
  • the plasma etch process is a remote plasma assisted dry etch process which involves the simultaneous exposure of a substrate to NF 3 and NH 3 plasma by-products.
  • the plasma etch process may be an inductively couple plasma (ICP) process.
  • the plasma etch process may be performed in the SiCoNiTM chamber that is available from Applied Materials, Inc. of Santa Clara, Calif.
  • the first process chamber may be the SiCoNiTM chamber.
  • the remote plasma etch can be predominantly conformal and selective towards silicon oxide layers, and thus does not readily etch silicon regardless of whether the silicon is amorphous, crystalline or polycrystalline.
  • the plasma etch process results in a substrate surface having silicon-hydrogen (Si—H) bonds thereon.
  • the substrate is removed from the first process chamber and transferred to a second process chamber where operation 130 is performed.
  • the first process chamber and the second process chamber may be positioned on the cluster tool allowing for transfer of the substrate without exposing the substrate to atmosphere (e.g., in a vacuum environment).
  • the second process chamber may be the SelectraTM etch chamber that is available from Applied Materials, Inc. of Santa Clara, Calif.
  • both operation 120 and operation 130 are performed in the same process chamber.
  • silicon is removed from a source/drain region disposed on a substrate. In one implementation, the silicon is removed from the source/drain region using an etching process.
  • the substrate includes a plurality of semiconductor fins and trenches formed in a dielectric material, and a portion of each semiconductor fin located within each trench is removed.
  • Each semiconductor fin may be fabricated from silicon.
  • the semiconductor fin may be the source/drain region of an n-MOS transistor, and the removal of portions of the semiconductor fin may be referred to as source/drain extension etch back.
  • the silicon etching process may be a plasma-based etching process.
  • an etching process gas is introduced into the chamber.
  • the etching process gas may comprise one or more etchants.
  • the etchants may be excited by a RF power.
  • the etchant includes a halogen-containing gas, optionally a hydrogen-containing gas, and optionally an inert gas.
  • the halogen-containing gas is chlorine gas
  • the hydrogen-containing gas is hydrogen gas
  • the optional inert gas is argon, helium, or both.
  • Exemplary chlorine-containing gases include diatomic chlorine (Cl 2 ) gas.
  • the inert gas may include at least one of argon, helium, neon, xenon and the like.
  • the substrate is removed from the second process chamber and transferred to a third process chamber where an epitaxial layer is deposited on the surface of the substrate.
  • both the second process chamber and the third process chamber are positioned on a cluster tool allowing for transfer of the substrate from the second process chamber to the third process chamber without exposing the substrate to atmosphere (e.g., in a vacuum environment.)
  • the third process chamber may be a reduced pressure (RP) Epi chamber that is available from Applied Materials, Inc. of Santa Clara, Calif.
  • the surface of the substrate is substantially or completely contaminant free which improves the quality of the epitaxial layer subsequently formed on the surface of the substrate.
  • the epitaxial layer may be silicon doped with arsenide (Si:As).
  • the epitaxial layer may be a binary film, ternary film, or quaternary film.
  • the epitaxial layer may be deposited using any suitable epitaxial deposition technique, such as selective epitaxial deposition.
  • the epitaxial layer is a Si:As layer and is deposited on a portion of each semiconductor fin that is inside of each trench.
  • the epitaxial layer may be referred to as a source/drain extension layer.
  • the substrate is transferred to a fourth process chamber and an epitaxial layer may be formed on the substrate.
  • the epitaxial layer may be formed by an epitaxial deposition process, such as a selective epitaxial deposition process.
  • the fourth process chamber may be a RP Epi chamber that is available from Applied Materials, Inc. of Santa Clara, Calif.
  • operation 140 and operation 150 are performed in the same process chamber, such as a RP Epi chamber.
  • the epitaxial layer is silicon doped with phosphorous (Si:P).
  • the surface of the substrate is contaminant free which improves the quality of the epitaxial layer subsequently formed on the surface of the substrate.
  • the epitaxial layer is a Si:P layer and is deposited in each trench formed in the dielectric material, and the Si:P layer is in contact with the Si:As layer that is formed on each semiconductor fins on the substrate.
  • the substrate is transferred to a fifth process chamber and a titanium silicide layer may be selectively formed on the substrate.
  • the fifth process chamber may be a RP Epi chamber that is available from Applied Materials, Inc. of Santa Clara, Calif.
  • operation 140 , operation 150 and operation 160 are performed in the same process chamber, such as a RP Epi chamber.
  • the titanium silicide layer may be formed by a selective epitaxial deposition process.
  • titanium and silicon precursors are flowed into the process chamber to form the titanium silicide layer.
  • the titanium and silicon precursors initially may be in liquid form, and may be vaporized to form vapor prior to flow into the process chamber.
  • one or more bubblers are utilized to vaporize the liquid precursors.
  • the substrate is transferred to a chamber for outgassing.
  • the chamber may be part of the cluster tool that includes the first, second, third, fourth and fifth process chambers.
  • the chamber may be a load-lock chamber.
  • the chamber may be a pass through chamber.
  • An abatement process may be performed on the one or more process chambers.
  • the abatement process is performed by an advanced foreline cleaning system, a dry clean absorber, and a combustible system.
  • the foreline cleaning system may utilize ammonium fluoride (NF 3 ) to react with and bind any arsenic compounds in the foreline.
  • the dry clean absorber may then remove the arsenic compounds from the foreline.
  • the combustible system is utilized to convert any remaining hydrogen into water.
  • the three stage exhaust abatement system provides for clean and safe disposal of by-products remaining within the chamber components after semiconductor processing.
  • FIG. 2 illustrates a process system 200 that can be used to perform the method 100 illustrated in FIG. 1 , according to implementations of the disclosure.
  • the process system 200 is the Centura® system available from Applied Materials, Inc., of Santa Clara, Calif.
  • a plurality of process chambers 202 is coupled to a first transfer chamber 204 .
  • four process chambers 202 are coupled to the first transfer chamber 204 , as shown in FIG. 2 .
  • the plurality of process chambers 202 are RP Epi chambers.
  • one of the four process chambers 202 is utilized to perform operation 140 , while the remaining three process chambers 202 are utilized to perform operations 150 and 160 .
  • all four process chambers 202 are utilized to perform operations 140 , 150 and 160 .
  • the first transfer chamber 204 is also coupled to one or more pass through chambers 206 and one or more post process chambers 220 .
  • two pass through chambers 206 are coupled to the first transfer chamber 204 and two post process chambers 220 are coupled to the first transfer chamber 204 .
  • the one or more pass through chambers 206 may be utilized to perform operation 170 .
  • the post process chambers 220 may be degas, cooling or surface passivation chambers.
  • the first transfer chamber 204 has a centrally disposed transfer robot 218 for transferring substrates between the pass through chambers 206 and the process chambers 202 .
  • the pass through chambers 206 are coupled to a second transfer chamber 210 , which is coupled to a cleaning chamber 214 for pre-clean the substrate (operation 120 ) and an etching chamber 216 for etching the substrate (operation 130 ).
  • the cleaning chamber 214 may be particularly useful for performing a thermal or plasma-based oxidation process and/or a plasma assisted dry etch process.
  • the cleaning chamber 214 is the SiCoNiTM chamber and the etching chamber 216 is the SelectraTM etch chamber.
  • both operations 120 and 130 may be performed in a single process chamber, such as in the cleaning chamber 214 .
  • the second transfer chamber 210 has a centrally disposed transfer robot 222 for transferring substrates between a set of load-lock chambers 208 and the cleaning chamber 214 or the etching chamber 216 . Operation 170 may be performed in the load-lock chambers 208 .
  • a factory interface 212 is connected to the second transfer chamber 210 by the load-lock chambers 208 .
  • the factory interface 212 is coupled to one or more pods 224 on the opposite side of the load-lock chambers 208 .
  • the pods 224 typically are front opening unified pods (FOUP) that are accessible from the clean room.
  • FOUP front opening unified pods
  • a substrate is first transferred to the cleaning chamber 214 where a cleaning process is performed to remove native oxide and contaminants such as carbon or hydrocarbons from the substrate surface.
  • the cleaning process is described in FIG. 1 under operation 120 .
  • the substrate is transferred to the etching chamber 216 in which operation 130 is performed.
  • operations 120 and 130 may be performed in a single chamber 214 .
  • the substrate is then transferred to one or more process chambers 202 in which operations 140 , 150 , and 160 are performed.
  • the substrate may then be transferred to the chamber 206 or the load-lock chamber 208 for outgassing as described under operation 170 . Because operations 120 , 130 , 140 , 150 , 160 , and 170 may be performed within the same process system, vacuum is not broken as the substrate is transferred to various chambers, which decreases the chance of contamination and improves the quality of the deposited epitaxial film.
  • benefits of the present disclosure provide an integrated system and method for pre-cleaning a silicon-containing substrate prior to epitaxial deposition, a source drain etch back, epitaxial deposition utilizing a source drain extension, epitaxial deposition, and wafer outgassing which results in an improved semiconductor device.
  • Clustering process chambers through vacuum transfer reduces exposure to atmosphere and correspondingly reduces exposure to oxygen contaminants. For example, performing inductively coupled plasma chlorine etching of silicon prior to epitaxial deposition without breaking vacuum between etching and deposition reduces exposure to oxygen contaminants.
  • Clustering the native oxide removal chamber along with the etching of silicon and epitaxial deposition also leads to a reduction in oxygen contaminants.
  • the integrated system advantageously provides for an improved semiconductor device.

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10199215B2 (en) * 2015-09-22 2019-02-05 Applied Materials, Inc. Apparatus and method for selective deposition
CN112930591A (zh) * 2018-09-18 2021-06-08 应用材料公司 原位集成型腔室
US20220005705A1 (en) * 2019-02-20 2022-01-06 Applied Materials, Inc. Methods and apparatus for metal silicide deposition
US20220093749A1 (en) * 2018-12-21 2022-03-24 Applied Materials, Inc. Method of fabricating a semiconductor device having reduced contact resistance
CN114975162A (zh) * 2021-02-26 2022-08-30 格科微电子（上海）有限公司 外延-刻蚀一体机
US20230075715A1 (en) * 2021-09-03 2023-03-09 Applied Materials, Inc. Cluster tools, systems, and methods having one or more pressure stabilization chambers

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20200144397A1 (en) * 2018-11-05 2020-05-07 Applied Materials, Inc. Methods and apparatus for silicon-germanium pre-clean
US11555250B2 (en) * 2020-04-29 2023-01-17 Applied Materials, Inc. Organic contamination free surface machining

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030082307A1 (en) * 2001-10-26 2003-05-01 Applied Materials, Inc. Integration of ALD tantalum nitride and alpha-phase tantalum for copper metallization application
US20130040080A1 (en) * 2008-10-07 2013-02-14 Kenneth J. Bhang Apparatus for efficient removal of halogen residues from etched substrates
US20140273515A1 (en) * 2013-03-15 2014-09-18 Applied Materials, Inc. Integrated platform for fabricating n-type metal oxide semiconductor (nmos) devices
US20150079784A1 (en) * 2013-09-13 2015-03-19 Applied Materials, Inc. Surface treatment to improve cctba based cvd co nucleation on dielectric substrate

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6281098B1 (en) * 1999-06-15 2001-08-28 Midwest Research Institute Process for Polycrystalline film silicon growth
US20030027427A1 (en) 2001-08-06 2003-02-06 Applied Materials, Inc. Integrated system for oxide etching and metal liner deposition
US7049226B2 (en) 2001-09-26 2006-05-23 Applied Materials, Inc. Integration of ALD tantalum nitride for copper metallization
US6908865B2 (en) * 2001-09-28 2005-06-21 Applied Materials, Inc. Method and apparatus for cleaning substrates
US6911695B2 (en) * 2002-09-19 2005-06-28 Intel Corporation Transistor having insulating spacers on gate sidewalls to reduce overlap between the gate and doped extension regions of the source and drain
KR101177576B1 (ko) * 2003-06-13 2012-08-27 어플라이드 머티어리얼스, 인코포레이티드 구리 금속배선을 위한 통합식 질화탄탈 원자층 증착 방법및 이를 위한 장치
KR101025740B1 (ko) * 2003-12-19 2011-04-04 주식회사 하이닉스반도체 증착 접합을 갖는 트랜지스터의 제조 방법
US7494545B2 (en) * 2006-02-03 2009-02-24 Applied Materials, Inc. Epitaxial deposition process and apparatus
US7651948B2 (en) 2006-06-30 2010-01-26 Applied Materials, Inc. Pre-cleaning of substrates in epitaxy chambers
KR20090035578A (ko) * 2006-07-03 2009-04-09 어플라이드 머티어리얼스, 인코포레이티드 향상된 전단부 처리를 위한 클러스터 기기
US7554110B2 (en) * 2006-09-15 2009-06-30 Taiwan Semiconductor Manufacturing Company, Ltd. MOS devices with partial stressor channel
US20100075499A1 (en) * 2008-09-19 2010-03-25 Olsen Christopher S Method and apparatus for metal silicide formation
US8207023B2 (en) * 2009-08-06 2012-06-26 Applied Materials, Inc. Methods of selectively depositing an epitaxial layer
US8999798B2 (en) * 2009-12-17 2015-04-07 Applied Materials, Inc. Methods for forming NMOS EPI layers
US8329547B2 (en) * 2010-07-22 2012-12-11 United Microelectronics Corp. Semiconductor process for etching a recess into a substrate by using an etchant that contains hydrogen peroxide
US8616821B2 (en) * 2010-08-26 2013-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated apparatus to assure wafer quality and manufacturability
KR102245729B1 (ko) * 2013-08-09 2021-04-28 어플라이드 머티어리얼스, 인코포레이티드 에피택셜 성장 이전에 기판 표면을 사전 세정하기 위한 방법 및 장치

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030082307A1 (en) * 2001-10-26 2003-05-01 Applied Materials, Inc. Integration of ALD tantalum nitride and alpha-phase tantalum for copper metallization application
US20130040080A1 (en) * 2008-10-07 2013-02-14 Kenneth J. Bhang Apparatus for efficient removal of halogen residues from etched substrates
US20140273515A1 (en) * 2013-03-15 2014-09-18 Applied Materials, Inc. Integrated platform for fabricating n-type metal oxide semiconductor (nmos) devices
US20150079784A1 (en) * 2013-09-13 2015-03-19 Applied Materials, Inc. Surface treatment to improve cctba based cvd co nucleation on dielectric substrate

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10199215B2 (en) * 2015-09-22 2019-02-05 Applied Materials, Inc. Apparatus and method for selective deposition
CN112930591A (zh) * 2018-09-18 2021-06-08 应用材料公司 原位集成型腔室
US11037838B2 (en) 2018-09-18 2021-06-15 Applied Materials, Inc. In-situ integrated chambers
US20220093749A1 (en) * 2018-12-21 2022-03-24 Applied Materials, Inc. Method of fabricating a semiconductor device having reduced contact resistance
US20220005705A1 (en) * 2019-02-20 2022-01-06 Applied Materials, Inc. Methods and apparatus for metal silicide deposition
CN114975162A (zh) * 2021-02-26 2022-08-30 格科微电子（上海）有限公司 外延-刻蚀一体机
US20230075715A1 (en) * 2021-09-03 2023-03-09 Applied Materials, Inc. Cluster tools, systems, and methods having one or more pressure stabilization chambers
US11965241B2 (en) * 2021-09-03 2024-04-23 Applied Materials, Inc. Cluster tools, systems, and methods having one or more pressure stabilization chambers

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WO2018052479A1 (en) 2018-03-22
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KR20210063459A (ko) 2021-06-01
EP3513428A4 (en) 2020-06-10
KR20190041030A (ko) 2019-04-19
US20200035525A1 (en) 2020-01-30
US11164767B2 (en) 2021-11-02
TW201824427A (zh) 2018-07-01

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