US20180012858A1

US20180012858A1 - Rare earth interlays for mechanically layering dissimilar semiconductor wafers

Info

Publication number: US20180012858A1
Application number: US15/612,797
Authority: US
Inventors: Andrew Clark; Rytis Dargis; Michael Lebby; Rodney Pelzel
Original assignee: IQE PLC
Current assignee: IQE PLC
Priority date: 2016-06-02
Filing date: 2017-06-02
Publication date: 2018-01-11
Also published as: JP2019522358A; CN109478504A; WO2017210629A1; US20170353002A1; TW201816947A; JP2019522359A; WO2017210622A1; WO2017210597A1; EP3488462A1; CN109478504B; US10615141B2; TWI753915B; EP3465743A1; JP6937783B2; TW201813010A; JP6937784B2; US10332857B2; US20190139761A1; EP3465744A1; TW201810542A

Abstract

Structures described herein may include mechanically bonded interlayers for formation between a first Group III-V semiconductor layer and a second semiconductor layer. The mechanically bonded interlayers provide reduced lattice strain by strain balancing between the Group III-V semiconductor layer and the second semiconductor layer, which may be silicon.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to U.S. Provisional Application Ser. No. 62/385,744 filed Sep. 9, 2016, and U.S. Provisional Application Ser. No. 62/344,439, filed Jun. 2, 2016, which are hereby incorporated herein by reference in their entirety. This application is related to co-pending PCT Application No. ______ (Attorney Docket No. 111848-0023-WO1) filed Jun. 2, 2017, which is hereby incorporated herein by reference in its entirety.

BACKGROUND

Group III-V semiconductors, and specifically Indium Phosphide (InP) semiconductors, are difficult to form on semi insulating materials, such as silicon. InP is of particular interest because of its widespread application in Heterojunction Bipolar Transistor (HBT) technology, which requires the use of a semi insulating InP substrate. For example, it would be beneficial to provide thin active layers of InP on silicon substrates to reduce the cost of the resulting wafers and substrates. However, lattice mismatch between InP and silicon is such that forming InP directly on silicon is not currently feasible without cracking or dislocation. Previous solutions to the formation of Group III-V semiconductors on silicon have included uses of intermediate layers of GaAs or Ge, however in many instances this results in a conductive path at the interface between the Group III-V semiconductor and silicon, which degrades device performance.

SUMMARY

Structures are described herein for the use of mechanically bonded interlayers in reducing lattice strain between Group III-V semiconductors and a second semiconductor material. The structures described herein describe mechanically bonded interlayers formed from various rare earth based materials including pnictides and rare earth oxides (REOs).
The structures described herein may include a first layer of a Group IV semiconductor, a second layer of at least one rare earth element. A portion of the second layer is either lattice matched or strain balanced to the first layer. The structure may include a third layer of a Group III-V semiconductor. The layer structure may contain at least one bonded interface.
In some embodiments, the third layer includes at least one shared element with a second portion of the second layer. In some embodiments, the at least one bonded interface is between the second and third layer. In some embodiments, the second layer offsets at least a fraction of a lattice mismatch between the first layer and the third layer. In some embodiments, the first layer is silicon.
In some embodiments, the second layer is conductive. In some embodiments, the second layer includes at least one rare earth pnictide. In some embodiments, a first region of the second layer includes a first rare earth pnictide alloy with rare earth elements in first proportions. A second region of the second layer includes the first rare earth pnictide alloy with rare earth elements in second proportions.
In some embodiments, a first region of the second layer includes a first rare earth pnictide alloy with Group V elements in first proportions. A second region of the second layer includes the first rare earth pnictide alloy with Group V elements in second proportions.
In some embodiments, the second layer includes a multilayer structure of at least two binary rare earth pnictides. In some embodiments, a second portion of the second layer includes GdAs. In some embodiments, a second portion of the second layer includes ErP. In some embodiments, a portion of the second layer includes a rare earth oxide. In some embodiments, a second portion of the second layer includes a Group III oxide.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features of the present disclosure will be more apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which:

FIG. 1 depicts mechanically bonded layer structures with stress-reducing interlayers, according to an illustrative implementation;

FIG. 2 depicts a layer structure with InP formed over mechanically bonded rare earth interlayers and silicon, according to an illustrative implementation;

FIG. 3 depicts a layer structure with InP formed over insulating and mechanically bonded interlayers and silicon, according to an illustrative implementation;

FIG. 4 depicts a layer structure with InP formed over mechanically bonded conductive rare earth interlayers and silicon, according to an illustrative implementation;

FIG. 5 depicts layer structures with a semiconductor layer formed over graded interlayers and silicon, according to an illustrative implementation;

FIG. 6 is a graph of the lattice constants for the pnictide family of rare earth alloys relative to semiconductor materials, according to an illustrative implementation;

FIG. 7 depicts a representation of the lattice spacing mismatch values for two different rare earth and arsenide/nitride pairs, according to an illustrative implementation;

FIG. 8 depicts a graphical representation of lattice strain balancing between ErN and ErAs relative to silicon, according to an illustrative implementation;

FIG. 9 depicts example layer structures of interlayers formed over semiconductor layers for mechanical bonding, according to an illustrative implementation; and

FIG. 10 depicts a schematic of stress reduction in mechanically bonded interlayers with differing coefficients of temperature expansion (CTE's) formed over semiconductor layers, according to an illustrative implementation.

DETAILED DESCRIPTION

In the following description, numerous details are set forth for the purpose of explanation. However, one of ordinary skill in the art will realize that the embodiments described herein may be practiced without the use of these specific details. In other instances, well-known structures and devices are shown in block diagram form so that the description will not be obscured with unnecessary detail.
Lattice mismatch between the lattice constants of Group III-V semiconductor materials and silicon make forming Group III-V semiconductor material over silicon incredibly difficult. In most cases, the lattice stress created between these two materials results in dislocations, crystalline defects, and fractures at the interface. However, for certain applications, forming Group III-V semiconductor material on semi insulating substrates is commercially important. For example, in HBT technology, InP must be formed on semi insulating substrates. Additionally, forming Group III-V semiconductors on silicon substrates with insulating interlayers is commercially important for FET, laser diode, emitter and detector technologies. The insulating interlayers ensure current flows along the InP layer, and reduces current leakage to the silicon substrate. Reducing lattice strain by forming additional layers in between Group III-V semiconductor materials and silicon may help distribute the strain across multiple layers, such that the integrity of each layer is preserved while still allowing for the formation of quality semiconductor material. For example, one solution to reducing the lattice strain between InP and silicon uses intermediate layers such as GaAs or Ge. However, this may be undesirable since it can result in a conductive path at the interface between InP and silicon, which degrades device performance.
Other solutions use insulating layers of a silicon compound formed on a first semiconductor wafer, and a layer of rare earth material formed on one surface of a second semiconductor wafer. Each of the layers of material has a different amount or type of lattice stress. The two surfaces can then be mechanically bonded to provide a predetermined amount of stress in the final active semiconductor layer. However, this technique produces an insulating layer between the two semiconductors, and may also have breakage and dislocation at the interface between the rare earth layer and the silicon compound layer.
There is thus a need for improvements in layer structures to allow for the formation of Group III-V semiconductors on silicon and other semiconductor materials, as well as improvements in the characteristics of the interlayer or interlayers, including conductivity/non-conductivity, stress formation or reduction.
FIG. 1 depicts mechanically bonded layer structures with stress-reducing interlayers. As shown in the structure 100, an interlayer 104 is formed over a first semiconductor layer 102. The interlayer 104 then allows for the formation of the second semiconductor layer 106. Lattice strain that results from a mismatch between a lattice constant of the first semiconductor layer 102 and the second semiconductor layer 106 is distributed throughout the interlayer 104. Thus interlayer 104 acts as a stress-reducing layer, and improves the integrity of the crystal structure of both semiconductor 102 and semiconductor 106. Furthermore, interlayer 104 may have a bonding interface, which allows for the separate growth of portions of interlayer 104 on each of the first semiconductor layer 102 and second semiconductor layer 106.
Structure 120 includes an interlayer 124 formed over a silicon layer 122. A device wafer 126 is formed over the interlayer 124 and the silicon layer 122. The device wafer 126 may be the second semiconductor layer 106, the interlayer 124 may be the interlayer 104, and the silicon layer 122 may be the first semiconductor layer 102, as shown in structure 100. Silicon layer 122 as shown in structure 120 may have a <111> orientation, a <100> orientation or a <110> orientation.
Structure 140 includes an interlayer 144 formed over a silicon layer 142. An InP layer 146 is then formed over the interlayer 144 and silicon layer 142. The InP layer 146 may be the device wafer 126, the interlayer 144 may be the interlayer 124, and the silicon layer 142 may be the silicon layer 122, as shown in structure 120. The InP layer 146 may be the second semiconductor layer 106, the interlayer 144 may be the interlayer 104, and the silicon layer 142 may be the first semiconductor layer 102, as shown in structure 100.
In some embodiments, in structures 100, 120 and 140, the interlayers 104, 124 and 144 respectively contain a bonded interface. The bonded interface may be between sublayers of interlayers 104, 124 and 144, which are described in further detail with respect to FIGS. 4-6 and FIGS. 8-12. In some embodiments, interlayers 104, 124 and 144 are graded, as described in further detail with respect to FIG. 7. In some embodiments, interlayer 104 shares one or more elements with first semiconductor layer 102 and/or second semiconductor layer 106. In some embodiments, interlayer 124 shares one or more elements with device wafer 126. In some embodiments, interlayer 144 shares one or more elements with InP layer 146. In some embodiments, the lattice constant of interlayer 104 is matched to the lattice constant of first semiconductor layer 102 and/or second semiconductor layer 106. In some embodiments, the lattice constant of interlayer 124 is matched to the lattice constant of silicon layer 122 and/or device wafer 126. In some embodiments, lattice constant of interlayer 144 is lattice matched to silicon layer 142 and/or InP layer 146.
In some embodiments, portions of interlayers 104, 124, and 144 may be lattice matched to the silicon layers 102, 122, and 142, respectively. In some embodiments, portions of interlayers 104, 124 and 144 may be lattice matched to layers 106, 126 and 146, respectively. In some embodiments, portions of interlayers 104, 124 and 144 may be strain balanced to silicon layers 102, 122 and 142, respectively. Portions of interlayers 104, 124 and 144 may be sublayers of the interlayers, such as those described in further detail with reference to FIGS. 2-5 and FIG. 9.
Lattice matching a lattice constant of one material to another material means that the absolute difference between the first lattice constant and the second lattice constant is small, but may be greater than or equal to 0 and is generally below some threshold, such as 4%, 3%, 2%, 1%, 0.5%, or any other suitable amount.
FIG. 2 depicts a layer structure 200 with InP formed over mechanically bonded rare earth interlayers and silicon. Structure 200 shows a first cubic Rare Earth Oxide (REO) layer 404 formed over a silicon layer 202. A second cubic REO layer 206 is formed over the first cubic REO layer 204. An InP layer 208 is formed over the second cubic REO layer 206, the first cubic REO layer 404, and the silicon layer 202.
The structure 200 has a first interface 210 between the first REO layer 204 and the second REO layer 206. Interface 210 may be a mechanically bonded interface. The first cubic REO layer 204 may be epitaxially grown over the silicon layer 202. The second cubic REO layer 206 may be epitaxially grown over the InP layer 208. Thus the bonded interface 210 may be a mechanically bonded interface between two separate structures (e.g., the first structure being the first cubic REO layer 204 epitaxially grown over the silicon layer 202, and the second structure being the second cubic REO layer 206 epitaxially grown over the InP layer 208), bonded together to form structure 200.
The interface 212 may be a mechanically bonded interface between the second cubic REO layer 406 and the InP layer 208. If interface 212 is mechanically bonded, then the second cubic REO layer 206 may be epitaxially grown over the first cubic REO layer 204. In some embodiments, the interface 210 is a mechanically bonded interface between the second cubic REO layer 206 and the first cubic REO layer 204. If interface 212 is mechanically bonded, then the first cubic REO layer 204 may be epitaxially grown over the silicon layer 202, and the second cubic REO layer 406 may be epitaxially grown over the InP layer 208. In some embodiments, both interfaces 210 and 212 may be mechanically bonded interfaces.
Structure 200 is an example of an insulating interlayer structure formed from a first cubic REO layer 204 and a second cubic REO layer 206. In this manner, first cubic REO layer 204 and second cubic REO layer 206 may together correspond to the interlayer 104, interlayer 124 and/or interlayer 144 as shown in FIG. 1. First cubic REO layer 204 may be a portion of interlayer 104, 124 and/or 144 as shown in FIG. 1. Second cubic REO layer 206 may be a portion of interlayer 104, 124 and/or 144 as shown in FIG. 1. The rare earth element of the first cubic REO layer 204 may be a different rare earth element from the second cubic REO layer 206. Together, first cubic REO layer 204 and second cubic REO layer 206 reduce a fraction of the lattice strain that would otherwise result from forming the InP layer 208 directly over the silicon layer 202. The lattice strain between InP layer 208 and silicon layer 202 is a result of the difference in lattice constants of InP and silicon. Silicon and InP are described herein by way of illustrative example only. In general, the composition of first cubic REO layer 204 and second cubic REO layer 206 may be modified to reduce lattice strain between any Group IV semiconductor material and a second semiconductor.
In some embodiments, the lattice constant of the first cubic REO layer 204 is matched to the lattice constant of the silicon layer 202. The lattice constant of the second cubic REO layer 206 may be matched to the lattice constant of the InP layer 208, or otherwise provide bonding sites for formation of the InP layer 208. Thus the second cubic REO layer 206 may be optimized for the formation of the InP layer 208, while the first cubic REO layer 204 may be optimized for formation over the silicon layer 202. The first cubic REO layer 204 may share an anion or a cation with the second cubic REO layer 206.
In some embodiments, a lattice strain between the first cubic REO layer 204 and the silicon layer 202 is strain balanced by a lattice strain existing between the second cubic REO layer 206 and the InP layer 208. In this case, the lattice constant of the first cubic REO layer 204 is matched to the lattice constant of the silicon layer 202, and the lattice constant of the second cubic REO layer 206 is matched to the lattice constant of the InP layer 208. In this case, the strain resulting from a lattice constant mismatch between the first cubic REO layer 204 and the silicon layer 202 is canceled by a substantially equal and opposite strain resulting from a lattice constant mismatch between the second cubic REO layer 206 and the InP layer 208. The structure 200 formed from mechanically bonding at interface at 210 or 212 will thus be strain balanced as a result of the first cubic REO layer 204 and the second cubic REO layer 206.
In some embodiments, first and second cubic REO layers 204 and 206 respectively are formed from any REO that forms a cubic bixbyite crystal structure. As an example, first cubic REO layer 204 is formed from Er₂O₃or (Er_1-xSc_x)O₃, while the composition of the second cubic REO layer 206 is selected to have a similar crystallographic structure as the first REO layer 204, while including bonding sites for the InP layer 208. Examples of materials used for the second cubic REO may be of the form RE₂(O_1-yP_y)₃, where the bounds for y are 0<=y to maintain insulating properties of the interlayer formed by the first cubic REO 204 and the second cubic REO 206. The upper surface of the second cubic REO 206 at interface 212 may be non-stoichiometric, for example either or both the rare earth element or the oxide might vary in different portions of the second cubic REO layer 206. The element phosphorous may be a common element in both the second cubic REO layer 206 and the InP layer 208.
FIG. 3 depicts a layer structure with InP formed over insulating and mechanically bonded interlayers and silicon. Structure 300 has a first cubic REO layer 304 formed over a silicon layer 302. A second cubic REO layer 306 is formed over the first cubic REO layer 304 and the silicon layer 302. An interface layer 308 is formed over the second cubic REO layer 306, the first cubic REO layer 304 and the silicon layer 302. The silicon layer 302 may have a <111> orientation, a <100> orientation or a <110> orientation. The rare earth element of the first cubic REO layer 304 may be a different rare earth element from the second cubic REO layer 306. In some embodiments, the rare earth element of the first cubic REO layer 304 may be the same rare earth element from the second cubic REO layer 306.
In some embodiments, the interface layer 308 has a similar material composition as the second cubic REO layer 306. In this case, the interface layer 308 has the same rare earth element as the cubic REO layer 306. In some embodiments, the interface layer 308 contains oxygen. In some embodiments, the second cubic REO layer 306 has the composition (RE_1-zIn_z)₂O₃, and the interface layer 308 has the composition InO₃where the value of z ranges from 0 to 1. In this case, interface layer 308 provides an interface between the second cubic REO layer 306 and the InP layer 310 or device layer where an element in the interface layer 308 is shared with the second cubic REO layer 306 and a second element is shared with the InP or device layer 310. The interface layer 308 may thus further reduce lattice strain in the structure 300, and also provide an improved surface on which to bond either the InP or device layer 310 or the second cubic REO layer 306.
Interfaces 312, 314, and/or 316 (or any suitable combination thereof) may be bonded interfaces. In some embodiments, the first cubic REO layer 304 may be epitaxially grown over the silicon layer 302. In this example, the bonded interface may be between the first cubic REO layer 304 and the second cubic REO layer 306. This would then allow for the formation of structure 300 from the bonding of two structures: the first consisting of the first REO layer 304 epitaxially grown on the silicon layer 302, and a second structure formed from the second cubic REO layer 306 epitaxially grown over both the interface layer 308 and the InP layer 310. In this example the interface layer 308 may be epitaxially grown over the InP or device layer 310. The bonding interface in structure 300 may be selected to be between two layers that would otherwise not be epitaxially grown, or may be difficult to epitaxially grow over each other. The bonding interface allows for flexibility in forming structure 300 and selecting which layers to epitaxially grow over each other.
The first cubic REO layer 304, the second cubic REO layer 306, and the interface layer 308 may be insulating. Insulating the InP or device layer 310 from the silicon layer 302 may be useful for FET, laser diode, emitter, and detector technologies, or any other technology in which a current may be confined to the InP or device layer 310. In these examples, a current may flow along the InP or device layer 310, while the insulating layers of the first cubic REO layer 304, and second cubic REO layer 306 reduce the current leakage from the InP or device layer 310 to the silicon layer 302. The interface layer 308 may have a different conductivity than the first cubic REO layer 304 and the second cubic REO layer 306. The interfacing layer may thus allow for further flexibility in defining the conductivity between the InP or device layer 310 and the silicon layer 302.
In some embodiments, the structure 300 is similar to the structure 200 shown in FIG. 2. Specifically, the silicon layer 302 may be the silicon layer 202, the first cubic REO layer 304 may be the first cubic REO layer 204, the second cubic REO layer 306 may be the second cubic REO layer 206, and the InP or device layer 310 may be the InP layer 208.
First cubic REO layer 304, second cubic REO layer 206 and interface layer 308 may together correspond to the interlayer 104, interlayer 124 and/or interlayer 144 as shown in FIG. 1. First cubic REO layer 204 may be a portion of interlayer 104, 124 and/or 144 as shown in FIG. 1. Second cubic REO layer 206 may be a portion of interlayer 104, 124 and/or 144 as shown in FIG. 1. Interface layer 308 may be a portion of interlayer 104, 124 and/or 144 as shown in FIG. 1.
FIG. 4 depicts a layer structure with InP formed over mechanically bonded conductive rare earth interlayers and silicon. The structure 400 has a first rare earth and Group V (RE-V) pnictide layer 404 formed over a silicon layer 402. A second RE-V pnictide layer 406 is formed over the first RE-V layer 404 and the silicon layer 402. An InP or device layer 408 is formed over the second RE-V pnictide layer 406, the first RE-V pnictide layer 404 and the silicon layer 402.
The interface 410 between the first RE-V pnictide layer 404 and the second RE-V pnictide layer 406 may be a mechanically bonded interface. In this example, the second RE-V pnictide layer 406 may be epitaxially grown on the InP or device layer 408, while the first RE-V pnictide layer 404 is epitaxially grown on the silicon layer 402. The structure 400 would then be formed by mechanically bonding at interface 410 between two separate structures: the first structure including the first RE-V pnictide layer 404 epitaxially grown over the silicon layer 402, and the second structure including the second RE-V pnictide layer 406 epitaxially grown over the InP layer 408.
In some embodiments, the interface 412 between the second RE-V pnictide layer 406 and the InP or device layer 408 may be a mechanically bonded interface. In this example, the first RE-V pnictide layer 404 may be epitaxially grown on the silicon layer 402, and the second RE-V pnictide layer 406 may be epitaxially grown on the first RE-V pnitcide layer 404. The structure 400 would then be formed by mechanically bonding at interface 412 between two separate structures: the first structure including the first and second RE-V pnictide layers 404 and 406 epitaxially grown over the silicon layer 402, and the second structure including the InP layer 408.
The lattice constant of the first RE-V pnictide layer may be matched to the lattice constant of the silicon layer 402. Silicon layer 402 may have a <100> orientation, a <100> or a <110> orientation. The lattice constant of the second RE-V pnictide layer may be matched to the lattice constant of the InP or device layer 408.
The first RE-V pnictide layer 404 and second RE-V pnictide layer 406 are conductive, as most pnictides are of a semi-metallic nature. In addition to lattice matching the first RE-V pnticide layer 404 to the silicon layer 402, and/or lattice matching the second RE-V pnictide layer 406 to the InP or device layer 408, the first and second RE-V pnictide layers 404 and 406 may strain balance the structure 400. A lattice strain that would otherwise exist as a result of the lattice constant mismatch between the InP layer 408 and the silicon layer 402 is thus distributed through the first and second RE-V pnictide layers 404 and 406. Examples of using the first and second RE-V pnictide layers 404 and 406 to strain balance structure 400 are discussed in further detail with respect to FIG. 6-10.
In some embodiments, first and second RE-V pnictide layers 404 and 406 are included within the interlayer 104, interlayer 124, and/or interlayer 144 as shown in FIG. 1. In this case, silicon layer 402 may be the same as semiconductor layer 102, silicon layer 122, and/or silicon layer 142, and the InP or device layer 408 may be the same as semiconductor 106, device wafer 126 and/or InP layer 146. First RE-V pnictide layer 404 may be a portion of interlayer 104, 124 and/or 144 as shown in FIG. 1. Second RE-V pnictide layer 406 may be a portion of interlayer 104, 124 and/or 144 as shown in FIG. 1.
FIG. 5 depicts three example layer structures with a semiconductor layer formed over graded interlayers and silicon. Instead of a pair of binary alloys (as shown in FIG. 4), the layer structures 510, 540 and 570 have rare earth pnictide interlayers 514, 544, and 574 that each includes a homogenous ternary alloy. In some embodiments, it is possible to achieve the same stress reducing affect of a pair of binary alloys in the rare earth pnictide buffer by introducing ternary alloys. The composition of the compound of ternary alloy is of the generic form GdN_xAs_1-x(0<x <1).
Layer structure 510 includes a silicon layer 512 and a semiconductor layer 520. Between them is the rare earth pnictide interlayer 514, which has the composition ErN_xAs_1-xwhere the value of x takes on a value from 0 to 1 and varies from x₁to x₂. In a first region 516, the value of x₁may be chosen such that the bottom surface of the rare earth pnictide layer 514 interfacing with the silicon layer 512 is lattice matched to the silicon layer 512. In a second region 518, the value of x₂may be chosen such that the top surface of the rare earth pnictide layer 514 interfacing with the semiconductor 520 is lattice matched to the semiconductor layer 520. Lattice matching in regions 518 and 516 reduce strain that would otherwise be present if the semiconductor layer 520 was formed directly over the silicon layer 512. By gradually varying the value of x from x₁to x₂, the lattice constant of the rare earth pnictide layer 514 is gradually modified from the lattice constant of the first region 516 to the second region 518.
Layer structure 540 depicts a structure similar to the layer structure 510, but the ternary alloy comprises phosphorous instead of arsenic. In some embodiments, the composition of ternary alloy GdN_y1P_1-y1in a first region 546 is lattice matched to silicon 542 to minimize the strain introduced in silicon. Thus the value of y₁may be chosen such that the bottom surface of rare earth pnictide layer 544 interfacing with the silicon layer 542 is lattice matched to silicon 542. In a second region 548, the composition of ternary alloy GdN_y2P_1-y2is lattice matched to semiconductor 550 to reduce the strain force introduced in semiconductor 550. Thus the value of y₂may be chosen such that the top surface of rare earth pnictide layer 544 is lattice matched to semiconductor 550. The value of y takes on a value from 0 to 1 and varies from y₁to y₂. The lattice constant of rare earth pnictide buffer layer 544 is gradually modified from the lattice constant of the first region 546 to the lattice constant of the second region 548 to maintain the structural strain balance in structure 540.
Layer structure 570 depicts a structure similar to the layer structures 510 and 540. In some embodiments, the composition of ternary alloy is GdN_z1A_1-z1in a first region 576 is lattice matched to silicon 572 to minimize the strain introduced in silicon. Thus the value of z₁may be chosen such that a bottom surface of the rare earth pnictide layer 574 is lattice matched to silicon. In a second region 578, the composition of ternary alloy is GdN_z2As_1-z2and is lattice matched to semiconductor 580 to reduce the strain force introduced in semiconductor 580. Thus the value of z₂may be chosen such that a top surface of the rare earth pnictide layer 574 is lattice matched to the semiconductor 580. The value of z takes on a value from 0 to 1 and varies from z₁to z₂. The lattice constant of rare earth pnictide buffer layer 574 is gradually modified from the lattice constant of the first region 576 to the lattice constant of the second region 578 to maintain the structural strain balance of structure 570. By providing a transition in lattice constant from the silicon layers (e.g., layers 512, 542 and 572) to the semiconductor layer (e.g., layers 520, 550 and 580), the rare earth pnictide layer (e.g., layers 514, 544 and 574) allows for mechanical bonding of the semiconductor layers 520, 550 and 580 with minimal defect levels.
Rare earth pnictide buffer layers 514, 544 and 574 may be the same as interlayers 104, 124, and/or 144 as shown in FIG. 1. Regions 516, 518, 546, 548, 578 and/or 576 may be portions of interlayers 104, 124, and/or 144 as shown in FIG. 1.
FIG. 6 is a graph of the lattice constants for the pnictide family of rare earth alloys relative to semiconductor materials. For simplicity, only binary alloy constructions are shown in graph 600. Pnictide alloys can, for example, include two rare-earth elements, such as Sc—Er or Gd—Nd, or two group V elements, such as N—P or P—As. The general form for pnictide alloys as used herein is: (RE1_1-xRE2_x)V or RE(V1_1-yV2_y), where RE represents a rare earth element and V represents a group V element.
In graph 600, the horizontal axis 602 represents rare earth elements in increasing order of atomic number, and the vertical axis 604 represents lattice constants, which may be referred to herein as lattice parameter or lattice spacing. Rare earth alloys are shown grouped according to the group V species contained in the pnictide alloy. Curve 606 represents how the lattice constant of a Re—N alloy changes as the rare earth element in the alloy changes. As is depicted in the graph 600, the lattice constant of Re—N compounds generally increases as the atomic number of the rare earth element in the alloy increases. For example, ScN has a lower lattice constant than GdN, both of which are on curve 606. Similarly, curve 608 represents how the lattice constant of a RE-P alloy changes, curve 610 represents how the lattice constant of a RE-As alloy changes, curve 612 represents how the lattice constant of a RE-Sb alloy changes, and curve 614 represents how the lattice constant of a RE-Bi alloy changes as the rare earth element in the alloy changes.
The systems and methods of this disclosure use or incorporate a mixed pnictide buffer to bridge a lattice mismatch between a Group IV semiconductor material (such as Si, whose lattice constant is shown as horizontal line 616) and a second semiconductor material, such as InP (horizontal line 618), or GaAs (horizontal line 620). In the example shown in FIG. 6, the lattice mismatch is represented by the difference in lattice constant coordinate between the horizontal line 616 and the horizontal lines 618 and 620. When Si is the Group IV semiconductor material, the first material adjacent to Si may be selected to be ErN, which intersects the RE-N curve 606, RE-As curve 610 and Si lattice constant along vertical line 622. A layer immediately adjacent to the ErN layer may be selected to be ErAs. ErN has a lattice constant below that of Si, while ErAs has a lattice constant above that of Si. It would then be possible, based on the distance of these lattice constants from the Si lattice constant, to construct a strain balanced pnictide interlayer of a layer of ErAs and a layer of ErN that would balance the strain associated with forming these materials over Si. The graph 600 is a pnictide alloy map that allows for correct lattice constants for a lattice match to be determined or engineered. This is described in detail with reference to FIG. 7 and FIG. 8. Also shown in graph 600 is the intersection of the vertical line representing Gd with the RE-N curve 606 and RE-As curve 610. Similarly to an ErN and ErAs pairing, GdN has a lattice constant below that of Si, while GdAs has a lattice constant above that of Si. It is therefore possible to construct a strain balanced pnictide interlayer of a layer of GdAs and a layer of GdN that would reduce the strain associated with forming these materials over Si. This is described in detail with reference to FIG. 7 and FIG. 8.
FIG. 7 depicts a diagram 700 of the lattice spacing mismatch values for two different rare earth and arsenide/nitride pairs. The diagram 700 shows examples of the pnictide lattice mismatch relative to silicon for two different pnictide pairs. The vertical axis 702 represents the lattice constant of silicon. Points 704, 706, 708 and 710 indicate, through their lateral distance from this vertical axis 702, the percentage difference between the lattice constants of various compounds and the lattice constant of silicon. Point 704, located to the right of the vertical axis 702, indicates that the lattice constant of ErAs is greater than the lattice constant of silicon. The mismatch of the lattice constant of ErAs relative to silicon is 5.7%. Point 708, located to the left of the vertical axis 702, indicates that the lattice constant of ErN is less than the lattice constant of silicon. The lattice mismatch of the lattice constant of ErN relative to silicon is −10.8%. If, referring to the example depicted in FIG. 4, the first RE-V pnictide layer 404 is a layer of ErN, while the second RE-V pnictide layer 406 is a layer of ErAs, it would be possible to strain balance an interlayer that includes these layers with respect to the silicon layer 402. The strain contributed by each layer is directly proportional to both the thickness of the layer and the lattice mismatch values shown at points 708 and 704. Thus, by adjusting the thickness of a layer of ErN and the thickness of a layer of ErAs, the strain contribution of each of their respective lattice mismatch relative to silicon is balanced. This is described by the following equation:
Δa ₁(ErAs)×t ₁(ErAs)=Δa ₂(ErN)×t ₂(ErN) (1)
Where Δa₁represents the lattice mismatch relative to silicon of ErAs, t₁represents the thickness of a layer of ErAs, Δa₂represents the lattice mismatch relative to silicon of ErN, and t₂represents the thickness of a layer of ErN. Thus for various thicknesses of layers of ErAs, the thickness of a layer of ErN necessary to strain balance relative to silicon may be calculated. Examples of these values are shown and described in relation to FIG. 8.
Similarly, point 706 shows the lattice mismatch of GdAs relative to silicon. Point 706, located to the right of the vertical axis 702, indicates that the lattice constant of GdAs is greater than the lattice constant of silicon. The lattice mismatch of the lattice constant of GdAs relative to silicon is 7.9%. Point 710, located to the left of the vertical axis 702, indicates that the lattice constant of GdN is less than the lattice constant of silicon. The lattice mismatch of the lattice constant of GdN relative to silicon is −8.9%. To strain balance a structure, it is possible to layer of GdN formed over a layer of GdAs, with layer thicknesses determined by Equation 1 above. Strain balancing may be achieved through any other combination of pnictide alloys. The strain balancing may also be calculated from any other semiconductor, other than silicon, and thus the values Δa₁and Δa₂may represent the lattice mismatch relative to a semiconductor other than silicon.
FIG. 8 depicts a graphical representation of lattice strain balancing between ErN and ErAs relative to silicon. A similar graphical representation may be calculated for any other pnictide pairing, such as GdN and GdAs. Horizontal axis 802 represents the thickness of an ErAs layer in nm. This may be the thickness of any RE-V layer described herein. Vertical axis 804 represents the required thickness in nm of a layer of ErN to strain balance the corresponding layer of ErAs relative to silicon. Since the percentage of lattice mismatch of ErAs relative to silicon is positive, while ErN lattice mismatch relative to silicon is negative, the slope of the line 806 is negative. As the strain contribution of a layer of ErAs increases, the corresponding negative strain of ErN must also increase. Referring to Equation 1, the relation shown by line 806 is given by:
$\begin{matrix} t_{2} (ErN) = t_{1} (ErAs) \frac{Δ a_{1} (ErAs)}{Δ a_{2} (ErN)} \approx t_{1} (ErAs) \times - 0.53 & (2) \end{matrix}$
A similar relation may be calculated to determine the required layer thickness for strain balancing relative to a semiconductor other than silicon.
While FIGS. 6-8 depict strain balancing an interlayer formed from pairs of pnictides relative to a silicon layer, it is also possible to include additional pnictide sub-layers (not shown) to strain balance to a device wafer, such as the InP layer 408 as shown in FIG. 4. Referring to FIG. 4, an additional pnictide sub-layer may be included in between the second RE-V pnictide layer 406 and the InP or device layer 408. This additional pnictide sub-layer may include GdAs. The additional pnictide sublayer may share one or more elements with the InP or device layer 408. Thus in the example shown in FIG. 4, in which the device layer 408 includes InP, the additional pnictide sublayer may be ErP, InP, or any compound of the form Er_1-xIn_xP. The additional pnictide sublayer may be epitaxially grown over the second RE-V pnictide layer 406, mechanically bonded to the second RE-V pnictide layer 406, and/or epitaxially grown over the InP or device layer 408.
FIG. 9 depicts example layer structures of interlayers formed over semiconductor layers for mechanical bonding. As shown in the first structure 902, a pnictide layer 906 of the composition Er_xP_1-xis formed over a layer of InP. As shown in the second structure 908, an REO layer 912 of the composition Er₂(O_1-yP_y)₃is formed over a silicon layer 910. The silicon layer may have a <111> orientation, an <100> orientation or a <110> orientation.
The value of x ranges from 0 to 1 across the thickness of the layer 906, forming a gradient. At the interface with the InP layer 904, the value of x may be 0, such that it forms a chemically similar interface with the InP layer 904. If the value of x is 0, at the interface with the InP layer 904 the material 906 reduces to P. At the top of the layer 906, x may be 1, such that the material 906 becomes Er. The value of y ranges from 0 to 1 across the thickness of layer 912. At the top of the layer 912 (e.g. opposite the interface with the silicon layer 910) the value of y may be 1, such that the top of the layer 912 is of the form RE-V and is a pnictide. When the value of y is 1, the material 912 reduces to Er₂P₃. The first structure 902 may be mechanically bonded to the second structure 908, such that a mechanically bonded interface exists between the pnictide layer 906 and the layer 912. By varying the values of x and y from 0 to 1, the bonded interface may be between two pnictide interfaces. Layer 906 may be formed from any material having the composition RE-P, while layer 912 may be formed from any material having the composition RE-OP.
Together, layer 906 and layer 912 may form interlayers 104, 124, and/or 144 as shown in FIG. 1. Layer 906 may be a portion of interlayers 104, 124, and/or 144 as shown in FIG. 1. Layer 912 may be a portion of interlayers 104, 124, and/or 144 as shown in FIG. 1.
FIG. 10 depicts a schematic of stress reduction in mechanically bonded interlayers with differing CTE's formed over semiconductor layers. In the top example of FIG. 10, a layer of InP 1008 is formed over a layer of silicon 1010, resulting in the first structure 1006. Because the CTE of InP is 4.6E-6° C.⁻¹and the CTE of silicon is 2.3E-6° C.⁻¹the resulting structure 1006 will be concave with any application of heat. The bending of structure 1006 is generally undesirable, especially if integrated into a device, and may result in cracking or fracturing of the structure 1006.
In the middle example of FIG. 10, a layer of cubic REO 1012 is formed over a layer of silicon 1014, resulting in the second structure 1004. The thickness of the cubic REO layer 1012 can be modified so that when formed over the silicon layer 1014, a convex curvature of the resulting structure 1004 is formed. Thickness of the cubic REO layer 1012 may be modified to change the degree of convex curvature of the resulting structure 1004. Examples of cubic REOs that produce such convex curvature as a result of their crystalline structures include Er₂O₃.
In the bottom example of FIG. 10, the convex curvature of second structure 1004 is combined with the inherent concave curvature that exists between the InP layer 1008 and silicon layer 1010 to balance mechanical strain, thus producing the strain balanced third structure 1002. The thickness of the cubic REO layer 1012 may be adjusted to partially or fully strain balance the third structure 1002.
The structures described herein describe various ways of strain balancing between a Group III-V semiconductor layer and a Group IV semiconductor using mechanically bonded interlayers. Various sublayers of the interlayer may allow for flexibility in the placement of the mechanically bonded region in a layer structure, while lattice matching sublayers to semiconductor layers reduces strain in the resulting structures.
As described herein, a portion of a layer may refer to a sublayer, region, or percentage of a layer. A portion of a layer may refer to any region within the layer.
Various changes and modifications to the embodiments herein chosen for purposes of illustration will readily occur to those skilled in the art. To the extent that such modifications and variations do not depart from the spirit of the invention, they are intended to be included within the scope thereof.
A lattice constant, or lattice parameter or lattice spacing, refers to the physical dimension of unit cells in crystal lattice. Lattice constants are typically on the order of several angstroms (Å). Matching lattice constants between semiconductor materials allows layers to be grown without a change in crystal structure.
Group V elements are the elements belonging to group V (as used in semiconductor physics) of the periodic table. Group V is understood in the field to include nitrogen (N), phosphorous (P), arsenic (As), antimony (Sb), and bismuth (Bi). This group of elements is understood to be the same group referred to as, for example, Group 15 in modern IUPAC notation, the nitrogen family, or pnictogens.
The lanthanide series includes the metals cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu). Throughout this disclosure it should be understood that the term rare-earth elements or rare-earth metals includes scandium and yttrium, as well as all lanthanides.
The growth and/or deposition described herein can be performed using one or more of chemical vapor deposition (CVD), metalorganic chemical vapor deposition (MOCVD), organometallic vapor phase epitaxy (OMVPE), atomic layer deposition (ALD), molecular beam epitaxy (MBE), halide vapor phase epitaxy (HVPE), pulsed laser deposition (PLD), and/or physical vapor deposition (PVD).
III-nitride (III-N) materials are semiconducting materials comprising nitrogen and one or more Group III elements. Common Group III elements used to form III-nitride materials include aluminum, gallium, and indium. III-nitride materials have large direct band gaps, making them useful for high-voltage devices, radio-frequency devices, and optical devices. Furthermore, because multiple Group III elements can be combined in a single III-nitride film in varying compositions, the properties of III-nitride films are highly tunable.
In some embodiments, the III-V and III-nitride materials used in the layer structures described herein are grown using metal-organic chemical vapor deposition (MOCVD). In MOCVD, one or more Group III precursors react with a Group V precursor to deposit a III-nitride film on a substrate. Some Group III precursors include trimethylgallium (TMGa) as a gallium source, trimethylaluminum (TMA) as an aluminum source, and trimethylindium (TMI) as an indium source. Ammonia is a Group V precursor which can be used as a nitrogen source. Tert-butylarsine and arsine are Group V precursors which can be used as arsenic sources. Tert-butylphosphine and phosphine are Group V precursors which can be used as phosphorous sources.
In some embodiments, the III-V and III-nitride materials used in the layer structures described herein are grown using molecular beam epitaxy (MBE). MBE is an epitaxy method for thin-film deposition of single crystals that takes place in high or ultra-high vacuum. In MBE, precise beams of gaseous atoms or molecules are fired at a heated substrate. When the molecules land on the substrate's surface, they condense and build up slowly and systematically in ultra-thin layers.
As described herein, a layer means a substantially-uniform thickness of a material covering a surface. A layer can be either continuous or discontinuous (i.e., having gaps between regions of the material). For example, a layer can completely cover a surface, or be segmented into discrete regions, which collectively define the layer (i.e., regions formed using selective-area epitaxy). A layer structure means a set of layers, and can be a stand-alone structure or part of a larger structure. A III-nitride structure means a structure containing III-nitride material, and can contain additional materials other than III-nitrides, a few examples of which are Si, a silicon oxide (SiO_x), silicon nitride (Si_xN_y) and III-V materials. Likewise, a III-V structure means a structure containing III-V material, and can contain additional materials other than III-Vs, a few examples of which are Si, a silicon oxide (SiO_x), silicon nitride (Si_xN_y) and III-nitride materials (a subset of III-Vs).
“Monolithically-integrated” means formed on the surface of the substrate, typically by depositing layers disposed on the surface.
Disposed on means “exists on” an underlying material or layer. This layer may comprise intermediate layers, such as transitional layers, necessary to ensure a suitable surface. For example, if a material is described to be “disposed on a substrate,” this can mean either (1) the material is in direct contact with the substrate; or (2) the material is in contact with one or more transitional layers that reside on the substrate.
Single-crystal means a crystal structure that comprises substantially only one type of unit-cell. A single-crystal layer, however, may exhibit some crystal defects such as stacking faults, dislocations, or other commonly occurring crystal defects.
Single-domain (or monocrystal) means a crystalline structure that comprises substantially only one structure of unit-cell and substantially only one orientation of that unit cell. In other words, a single-domain crystal exhibits no twinning or anti-phase domains.
Single-phase means a crystal structure that is both single-crystal and single-domain.
Crystalline means a crystal structure that is substantially single-crystal and substantially single-domain. Crystallinity means the degree to which a crystal structure is single-crystal and single-domain. A highly crystalline structure would be almost entirely, or entirely single-crystal and single-domain.
Epitaxy, epitaxial growth, and epitaxial deposition refer to growth or deposition of a crystalline layer on a crystalline substrate. The crystalline layer is referred to as an epitaxial layer. The crystalline substrate acts as a template and determines the orientation and lattice spacing of the crystalline layer. The crystalline layer can be, in some examples, lattice matched or lattice coincident. A lattice matched crystalline layer can have the same or a very similar lattice spacing as the top surface of the crystalline substrate. A lattice coincident crystalline layer can have a lattice spacing that is an integer multiple, or very similar to an integer multiple, of the lattice spacing of the crystalline substrate. In some embodiments, an number may be considered an integer if it is within 0.5% of an integer. For example, numbers between 1.95 and 2.05 may be considered the integer 2. In some embodiments, the lattice spacing in lattice matched crystalline structures may be approximately 0.1%, 0.2%, 0.3%, 0.4%, 0.5%, or any other suitable percentage. In general, the lattice spacing in lattice matched crystalline structures may be less than 1%. Alternatively, the lattice spacing of the crystalline substrate can be an integer multiple, or very similar to an integer multiple, of the lattice spacing of the lattice coincident crystalline layer. The quality of the epitaxy is based in part on the degree of crystallinity of the crystalline layer. Practically, a high quality epitaxial layer will be a single crystal with minimal defects and few or no grain boundaries.
Substrate means the material on which deposited layers are formed. Exemplary substrates include, without limitation: bulk silicon wafers, in which a wafer comprises a homogeneous thickness of single-crystal silicon; composite wafers, such as a silicon-on-insulator wafer that comprises a layer of silicon that is disposed on a layer of silicon dioxide that is disposed on a bulk silicon handle wafer; or any other material that serves as base layer upon which, or in which, devices are formed. Examples of such other materials that are suitable, as a function of the application, for use as substrate layers and bulk substrates include, without limitation, gallium nitride, silicon carbide, gallium oxide, germanium, alumina, gallium-arsenide, indium-phosphide, silica, silicon dioxide, borosilicate glass, pyrex, and sapphire.
A rare earth pnictide material is a material that contains one or more group V elements and one, two, or more rare earth (RE) elements. The rare earth elements include lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), luthium (Lu), scandium (Sc) and yttrium (Y).
Semiconductor-on-Insulator means a composition that comprises a single-crystal semiconductor layer, a single-phase dielectric layer, and a substrate, wherein the dielectric layer is interposed between the semiconductor layer and the substrate. This structure may include silicon-on-insulator (“SOI”) compositions.
Carrier concentration means the number of majority carriers per unit volume.
Charge carrier density denotes the number of charge carriers per volume.
Interface means the surface between two layers or regions of dissimilar crystalline semiconductors.
Semiconductor-on-insulator compositions include but are not limited to a silicon, germanium, or silicon-germanium “active” layer. In other words, exemplary semiconductor-on-insulator compositions include, without limitation: silicon-on-insulator, germanium-on-insulator, and silicon-germanium-on-insulator. In some embodiments, various structures of silicon that may be used are Si <100>, Si <110>, Si <111>, for example.
A first layer described and/or depicted herein as “on” or “over” a second layer can be immediately adjacent to the second layer, or one or more intervening layers can be between the first and second layers. An intervening layer described and/or depicted as “between” first and second layers can be immediately adjacent to the first and/or the second layers, or one or more additional intervening layers may be between the intervening layer and the first and second layers. A first layer that is described and/or depicted herein as “directly on” or “directly over” a second layer or a substrate is immediately adjacent to the second layer or substrate with no intervening layer present, other than possibly an intervening alloy layer that may form due to mixing of the first layer with the second layer or substrate. In addition, a first layer that is described and/or depicted herein as being “on,” “over,” “directly on,” or “directly over” a second layer or substrate may cover the entire second layer or substrate, or a portion of the second layer or substrate.
A substrate is placed on a substrate holder during layer growth, and so a top surface or an upper surface is the surface of the substrate or layer furthest from the substrate holder, while a bottom surface or a lower surface is the surface of the substrate or layer nearest to the substrate holder. Any of the structures depicted and described herein can be part of larger structures with additional layers above and/or below those depicted. For clarity, the figures herein can omit these additional layers, although these additional layers can be part of the structures disclosed. In addition, the structures depicted can be repeated in units, even if this repetition is not depicted in the figures.
From the above description it is manifest that various techniques may be used for implementing the concepts described herein without departing from the scope of the disclosure. The described embodiments are to be considered in all respects as illustrative and not restrictive. It should also be understood that the techniques and structures described herein are not limited to the particular examples described herein, but can be implemented in other examples without departing from the scope of the disclosure. Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Additionally, the different examples described are not singular examples and features from one example may be included within the other disclosed examples. Accordingly, it will be understood that the claims are not to be limited to the examples disclosed herein, but is to be understood from the technical teachings provided above, as those teachings will inform the person of skill in the art.

Claims

1. A structure comprising:

a first layer comprising a Group IV semiconductor;

a second layer comprising at least one rare earth element, wherein a first portion of the second layer is either lattice matched or strain balanced to the first layer;

a third layer comprising a III-V semiconductor, and wherein the structure contains at least one bonded interface.

2. The structure of claim 1, wherein the third layer includes at least one shared element with a second portion of the second layer.

3. The structure of claim 1, wherein the at least one bonded interface is between the second and third layer.

4. The structure of claim 1, wherein the second layer offsets at least a fraction of a lattice mismatch between the first layer and the third layer.

5. The structure of claim 1, wherein the first layer is silicon.

6. The structure of claim 1, wherein the second layer is conductive.

7. The structure of claim 1, wherein the second layer is comprises of at least one rare earth pnictide.

8. The structure of claim 1, wherein:

a first region of the second layer comprises a first rare earth pnictide alloy with rare earth elements in first proportions; and

a second region of the second layer comprises the first rare earth pnictide alloy with rare earth elements in second proportions.

9. The structure of claim 1, wherein:

a first region of the second layer comprises a first rare earth pnictide alloy with Group V elements in first proportions; and

a second region of the second layer comprises the first rare earth pnictide alloy with Group V elements in second proportions.

10. The structure of claim 1, wherein the second layer is comprised of a multilayer structure of at least two binary rare earth pnictides.

11. The structure of claim 1, wherein a second portion of the second layer comprises GdAs.

12. The structure of claim 1, wherein a second portion of the second layer comprises ErP.

13. The structure of claim 1, wherein a portion of the second layer comprises a rare earth oxide.

14. The structure of claim 1, wherein a second portion of the second layer comprises a Group III oxide.

15. The structure of claim 1, wherein a second portion of the second layer comprises RE-OP.