[go: up one dir, main page]

US20170277603A1 - Data saving method, device and terminal - Google Patents

Data saving method, device and terminal Download PDF

Info

Publication number
US20170277603A1
US20170277603A1 US15/514,446 US201515514446A US2017277603A1 US 20170277603 A1 US20170277603 A1 US 20170277603A1 US 201515514446 A US201515514446 A US 201515514446A US 2017277603 A1 US2017277603 A1 US 2017277603A1
Authority
US
United States
Prior art keywords
data
power failure
power supply
data saving
saving device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US15/514,446
Other languages
English (en)
Inventor
Shukui Zhu
Xiaofei SHI
Qi Zhang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ZTE Corp
Original Assignee
ZTE Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ZTE Corp filed Critical ZTE Corp
Assigned to ZTE CORPORATION reassignment ZTE CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ZHANG, QI, SHI, Xiaofei, ZHU, SHUKUI
Publication of US20170277603A1 publication Critical patent/US20170277603A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1471—Saving, restoring, recovering or retrying involving logging of persistent data for recovery
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level
    • G06F11/1441—Resetting or repowering
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/16—Protection against loss of memory contents
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1028—Power efficiency
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present disclosure relates to the field of communications, and more particularly, to a data saving method and device, and a terminal.
  • the existing patents can be roughly seen as a combination of three methods.
  • the first method is a method of increasing backup power supply in the system. By virtue of this method, the backup power supply can is replace the system power supply to supply power in the event of power failure to meet the data saving time requirements.
  • the second method is the use of a non-volatile flash memory (NAND FLASH) in the pursuit of a faster write speed to shorten the time to save data in a disguised form.
  • the third method is the adoption of data compression after power failure to reduce the size of the write data.
  • the addition of backup power supply means an increase in cost.
  • the data of the base station product has a high reliability requirement. A “bad block” would appear randomly in the using process of NAND FLASH, which makes it hard to guarantee the correctness of the write data during the power failure.
  • the time of compression will inevitably lead to a delay in writing to the non-volatile memory, further increasing the requirement for power supplying time of the backup power supply.
  • the duration of the power failure of base station products is generally up to tens of milliseconds on the order of magnitude.
  • NAND FLASH and Non-volatile Flash are the most common non-volatile memories.
  • NOR FLASH Non-volatile Flash
  • data of NOR FLASH has a higher reliability.
  • System firmware of for example automotive, industrial, medical, wireless communication products, or consumer electronics has a very high requirement for the read speed and reliability, but does not emphasize the write speed.
  • NOR FLASH is still a key device affecting the device function and performance.
  • Some embodiments of the present disclosure provide a data saving method, a data saving device, or a terminal to solve the problem of increased system cost due to the use of a backup power supply when the power failure data is saved in the related art.
  • a data saving method power failure of a power supply is detected; a protection mechanism program for power failure data protection is triggered; and power failure data stored before occurrence of the power failure of the power supply is stored into a predetermined memory according to the protection mechanism program.
  • the data saving method may further include a step as follows.
  • the power failure data is stored in a partitioned storage mode according to degree of importance of data in the power failure data.
  • the power failure data stored before the occurrence of the power failure of the power supply is stored into the predetermined memory according to the protection mechanism program in the following manner: data, the degree of importance of which exceeds a predetermined value, in the power failure data is preferentially stored into the predetermined memory.
  • the predetermined memory may include a high speed non-volatile memory
  • the high speed non-volatile memory may include at least one of the following memories: a Serial Peripheral Interface NOR Flash (SPI NOR FLASH), a Phase-Change Random Access Memory (PRAM), a variable Resistive Random Access Memory (RRAM), a Ferroelectric Random Access Memory (FRAM), and a Magnetic Random Access Memory (MRAM).
  • SPI NOR FLASH Serial Peripheral Interface NOR Flash
  • PRAM Phase-Change Random Access Memory
  • RRAM variable Resistive Random Access Memory
  • FRAM Ferroelectric Random Access Memory
  • MRAM Magnetic Random Access Memory
  • the data saving method may further include a step as follows. Data stored in a region, into which the power failure data is to be written, of the predetermined memory is erased.
  • a data saving device including: a detecting module, a triggering module and a first storage module.
  • the detecting module is arranged to detect power failure of a power supply.
  • the triggering module is arranged to trigger a protection mechanism program for power failure data protection.
  • the first storage module is arranged to store, into a predetermined memory according to the protection mechanism program, power failure data stored before occurrence of the power failure of the power supply.
  • the data saving device may further include a is second storage module.
  • the second storage module is arranged to store the power failure data in a partitioned storage mode according to degree of importance of data in the power failure data.
  • the first storage module includes a storage unit.
  • the storage unit is arranged to preferentially store data, the degree of importance of which exceeds a predetermined value, in the power failure data into the predetermined memory.
  • the data saving device may further include an erasing module.
  • the erasing module is arranged to erase data stored in a region, into which the power failure data is to be written, of the predetermined memory.
  • a terminal including the data saving device according to any one of the above.
  • FIG. 1 is a flow diagram of a data saving method according to an embodiment of the present disclosure
  • FIG. 2 is a chip block diagram of an SPI NOR FLASH according to an embodiment of the present disclosure
  • FIG. 3 is a structure block diagram of a data saving device according to an embodiment of the present disclosure.
  • FIG. 4 is a first exemplary structure block diagram of a data saving device is according to an embodiment of the present disclosure
  • FIG. 5 is a structure block diagram of a first storing module 36 in a data saving device according to an embodiment of the present disclosure
  • FIG. 6 is a second exemplary block diagram of a data saving device according to an embodiment of the present disclosure.
  • FIG. 7 is a structure block diagram of a terminal according to an embodiment of the present disclosure.
  • FIG. 8 is a flow diagram of a method for protecting power failure data according to an embodiment of the present disclosure.
  • FIG. 9 is a system frame diagram of a system according to an embodiment of the present disclosure.
  • FIG. 1 is a flow diagram of a data saving method according to the embodiment of the present disclosure. As shown in FIG. 1 , the flow includes the following steps.
  • a step of S 102 power failure of a power supply is detected.
  • a protection mechanism program for power failure data protection is triggered.
  • a step of S 106 Power failure data stored before occurrence of the power failure of the power supply is stored into a predetermined memory according to the protection mechanism program.
  • the data saving method may further include the following step.
  • the power failure data is stored in a partitioned storage mode according to degree of importance of data in the power failure data. That is, before the occurrence of the power failure, a part of data with a high degree of importance may be stored in the system, such as voltage, current, semaphore, switch quantity and other important parameters are preferentially stored in the system. In the moment of the occurrence of the power failure, these data stored within the system can be preferentially saved to the predetermined memory so as to improve the saving efficiency of important data.
  • the power failure data stored before occurrence of the power failure of the power supply may be stored into a predetermined memory according to the protection mechanism program in the following manner.
  • Data, the degree of importance of which exceeds a predetermined value, in the power failure data is preferentially stored into the predetermined memory. That is, the data stored in advance can be divided according to degree of importance of data in the power failure data at the time of storage.
  • the data with a high degree of importance can be preferentially stored at the time of power failure.
  • the data with a low degree of importance can be subjected to some compression processing, and can be stored after the data with a high degree of importance is stored so as to ensure the storage integrity of important data.
  • the above predetermined memory may include a high-speed non-volatile memory, and the high-speed non-volatile memory may include at least one of the following memories: a SPI NOR FLASH, a PRAM, a variable RRAM, a FRAM, and a MRAM.
  • the SPI NOR FLASH has a capacity of more than 64 M bytes.
  • the read-write speed of the SPI NOR FLASH in the mode of the double data rate (DDR) can reach tens of millions of bytes per second, which is ten times of the parallel peripheral interface NOR FLASH.
  • FIG. 2 is a chip block diagram of an SPI NOR FLASH according to an embodiment of the present disclosure. As shown in FIG. 2 , the design of the chip is relatively simple.
  • the PRAM is a non-volatile memory. Compared with an ordinary flash memory, PRAM has the characteristics of a high speed and a low power consumption. If the development is smooth, it is expected that PRAM will gradually replace FLASH to become a dominant force in the next generation of memory products.
  • the variable Resistive Random Access Memory (ReRAM/RRAM) is a new type of non-volatile memories. The advantage is that the power consumption is low and the write speed is fast.
  • the Ferroelectric Random Access Memory (FeRAM/FRAM) is a new type of non-volatile memories, using the ferroelectric effect of ferroelectric crystals to achieve data storage.
  • the advantage is that the power consumption is low, and the write speed is fast.
  • the Magnetic Random Access Memory (MRAM) is a non-volatile magnetic random access memory. It has a high-speed read-write capability like a static random access memory (SRAM) as well as high integration like a dynamic random access memory (DRAM), and can be basically written repeatedly indefinitely.
  • the data saving method may further include the following step.
  • Data stored in a region, into which the power failure data is to be written, of the predetermined memory is erased.
  • the storage area in the predetermined memory can be erased when the system is just powered on so as to ensure that no erasing operation is caused during the power failure process, and provide more time for data storage.
  • module may implement a combination of software and/or hardware of a predetermined function.
  • the data saving device described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.
  • FIG. 3 is a structure block diagram of a data saving device according to an embodiment of the present disclosure. As shown in FIG. 3 , the data saving device includes a detecting module 32 , a triggering module 34 , and a first storage module 36 . The data saving device will be described below.
  • the detecting module 32 is arranged to detect power failure of a power supply; the triggering module 34 is coupled to the above detecting module 32 and arranged to trigger a protection mechanism program for power failure data protection; and the is first storage module 36 is coupled to the above triggering module 34 and arranged to store, into a predetermined memory according to the protection mechanism program, power failure data stored before occurrence of the power failure of the power supply.
  • FIG. 4 is a first exemplary structure block diagram of a data saving device according to an embodiment of the present disclosure. As shown in FIG. 4 , in addition to all the modules shown in FIG. 3 , the data saving device may further include a second storage module 42 . The data saving device will be described below.
  • the second storage module 42 is coupled to the above detecting module 32 and arranged to store the power failure data in a partitioned storage mode according to degree of importance of data in the power failure data.
  • FIG. 5 is a structure block diagram of a first storing module 36 in a data saving device according to an embodiment of the present disclosure. As shown in FIG. 5 , the first storage module 36 includes a storage unit 52 . The data saving device will be described below.
  • the storage unit 52 is arranged to preferentially store data, the degree of importance of which exceeds a predetermined value, in the power failure data into the predetermined memory.
  • FIG. 6 is a second exemplary block diagram of a data saving device according to an embodiment of the present disclosure. As shown in FIG. 6 , in addition to all the modules shown in FIG. 3 , the data saving device may further include an erasing module 62 . The data saving device will be described below.
  • the erasing module 62 is coupled to the above detecting module 32 and arranged to erase data stored in a region, into which the power failure data is to be written, of the predetermined memory.
  • FIG. 7 is a structure block diagram of a terminal according to an embodiment of the present disclosure. As shown in FIG. 7 , the terminal 70 includes a data saving device 72 according to any one of the embodiments.
  • an embodiment of the present disclosure also provides a power failure data saving method and device as described below.
  • the present disclosure will be described below with reference to specific embodiments.
  • the method for protecting the power failure data for the wireless communication product can improve the recovery capability and reliability of the wireless communication product system and the abnormal recording capability.
  • the method relates to a power supply, a power supply detecting unit (equivalent to the above detecting module 32 ), a controller (equivalent to the above trigger module 34 and the first storage module 36 ), and a stable and reliable high-speed non-volatile memory.
  • the controller may include SOC chip of the high-speed SRAM.
  • the stable and reliable high-speed non-volatile memory may include at least one of the five kinds of memories such as SPI NOR FLASH, PRAM, ReRAM/RRAM, FRAM/FeRAM, and MRAM.
  • FIG. 8 is a flow diagram of a method for protecting power failure data according to an embodiment of the present disclosure. As shown in FIG. 8 , the flow includes the following steps.
  • the power supply module supplies power normally.
  • the power supply detecting module detects the power supply.
  • step of S 808 it is judged whether the power supply works normally.
  • Step S 810 when the power supply works normally, the power supply is continuously detected, and the flow proceeds to Step S 806 .
  • the power supply detecting unit detects the power failure event and informs the controller.
  • the controller executes the protection mechanism program in the high-speed SRAM with the time from the occurrence of the power failure event of the power supply to the time when the power supply is completely disabled, and writes the data in the high-speed SRAM into the stable and reliable high-speed non-volatile memory.
  • step of S 818 the processing for system power failure is completed.
  • the controller can retrieve the data before the power failure from the stable and reliable high-speed non-volatile memory.
  • the power supply detecting unit detects the power failure event and informs the controller. Then the controller executes the protection mechanism program in the high-speed SRAM with the time from the occurrence of the power failure event of the power supply to the time when the power supply is completely disabled, and writes the data in the high-speed SRAM into the stable and reliable high-speed non-volatile memory.
  • the controller can retrieve the data before the power failure from the stable and reliable high-speed non-volatile memory.
  • the area to be written in the stable and reliable high-speed non-volatile memory may ensure that the erasing operation is not introduced during the entire power failure process.
  • FIG. 9 is a system frame diagram of a system according to an embodiment of the present disclosure. As shown in FIG. 9 , the system includes the following four parts: a power supply module 902 , a power supply detecting module 904 , a controller module 906 , and a stable and reliable high speed non-volatile memory 908 .
  • the power supply detecting module 904 detects that the power failure occurs, the cache data is immediately protected, and the protection data can be recovered quickly and efficiently after the system power is recovered.
  • the power detecting module 904 is responsible for the completion of the power supply detection of the system power supply and the power supply module.
  • the power detecting module 904 is arranged to implement functions including: detecting whether the system power supply is normal, and then triggering the related data protection behavior of the controller module 906 .
  • the power supply module 902 is the power supply part of the system, and provides necessary power supply to the controller module 906 and the stable and reliable high-speed non-volatile memory 908 .
  • the controller module 906 contains a high-speed SRAM, a part of which is used to store the processing code for managing the operation of the entire protection system after the power failure, and another part of which is used to store the power failure data which is not written to the stable and reliable high-speed non-volatile memory 908 in the normal operation.
  • the stable and reliable high-speed non-volatile memory 908 stores the protection data read out by the high-speed SRAM of the controller module 906 .
  • the controller module 906 After the power failure, after discovering the power failure state detected by the power supply detecting module 904 , the controller module 906 starts executing the power failure protection program in the high speed SRAM, copies the data into the stable and reliability high-speed non-volatile memory 908 .
  • the controller module 906 can acquire the protection data from the stable and reliable high-speed non-volatile memory 908 after the system power supply module 902 is recovered.
  • the stable and reliable high-speed non-volatile memory is used, including the five kinds of memories such as SPI NOR FLASH, PRAM, ReRAM/RRAM, FRAM/FeRAM, and MRAM. This is an improvement for some related arts using other memories.
  • the common feature of these kinds of memories is a fast write speed and high data reliability.
  • the memories in the related art have various problems, such as for the NAND FLASH, there is a risk that a bad block appears randomly and the written data may be wrong; for the parallel peripheral interface NOR FLASH or disk, the write speed is too slow to write data in the duration of power failure in time.
  • the data to be saved is placed in the high-speed SRAM inside the SOC, and is optimized for some related arts using a Synchronous Dynamic Random Access Memory (SDRAM) as a data cache, which is characterized in that implementation of the data saving reduces the normal operation of the SDRAM, which is the prerequisite. Moreover, compared to the SRAM inside the SOC, the SDRAM, as an off-chip memory, has a slow read-write speed, which is not conducive to upgrading the data saving efficiency of the scenario without a backup power supply.
  • SDRAM Synchronous Dynamic Random Access Memory
  • the program for executing the protection mechanism is also stored in the high-speed SRAM, and is optimized for some related arts using an external memory as a data cache.
  • the storage of the program in the high-speed SRAM is characterized in that the condition for the implementation of the data saving does not include the normal operation of the SDRAM anymore, which was a prerequisite condition.
  • the SDRAM as an off-chip memory, has a slow read-write speed, which is not conducive to upgrading the data saving efficiency of the scenario without a backup power supply.
  • the data to be saved is subjected to the data processing, e.g., arranging the data needing to be saved according to a certain priority and performing different data processing.
  • the most important data such as the voltage, current and other parameters, are not subjected to data compression, and are first saved to a stable and reliable high-speed non-volatile memory after a power failure.
  • the semaphore, switch quantity and other parameters with a lower degree of importance are subjected to the data encoding processing, and then saved to the stable and reliable high-speed non-volatile memory.
  • the log file run by the system with the lowest degree of importance are subjected to file compression and then saved to the stable and reliable high-speed non-volatile memory. The purpose of doing so is to save the most important data in the worst power failure scenarios as much as possible.
  • the area into which data is to be written in the stable and reliable high-speed non-volatile memory is pre-erased because of the characteristics that the data area of non-volatile memory should be first erased before the data can be correctly written to ensure that no erasing operation is introduced during the entire power failure process to avoid the waste of valuable time.
  • the erasing action of one sector may have consumed the full time of the power failure event.
  • the system for saving power failure data provided in the embodiment of the present disclosure is characterized by the integration of two key points, i.e., containing no backup power supply, and containing no external cache.
  • Containing no backup power supply is an improvement for some related arts using power supply other than the main power supply, and the system does not contain other power supply other than the system power supply.
  • Containing no external cache is an improvement for some technologies using memories other than SOC for saving data and power failure protection program. When the system has a power failure, these technologies will have one more prerequisite than the system in the embodiment of the present disclosure, that is, it should be ensured that the power supply for the memories other than SOC has to be normal in the power failure data saving process.
  • the system provided in the embodiment of the present disclosure allows the absence of a backup power supply.
  • the constituent part in the system realizing the data saving requirement in the power failure scenario may also use the following component as an alternative.
  • the future memories such as future NAND FLASH may have a breakthrough in technology, solving the bad block problem, and ensuring the reliability of the performance of each data block in its life cycle.
  • the future memories may have a breakthrough in technology, and new memories may appear.
  • the write speed of the new memories is faster than several types of memories specified herein.
  • the non-volatile memory in the embodiment of the present disclosure may be replaced with the related memories that appear in the future.
  • the stable and reliable high-speed non-volatile memory in the application example may adopt SPI NOR FLASH, and the process includes the following steps.
  • the area in which power failure data is to be written is prepared.
  • the area should guarantee to accommodate single or multiple power failure data.
  • the “power failure data” here refers to all the data in the high-speed SRAM that is to be saved in the power failure.
  • the original storage area may be subjected to erasing operation.
  • each power failure data is corresponding to a previous power failure event, each power failure data circulates successively according to the time, i.e., the power failure data with the longest time is erased. After the implementation of this step, it can be ensured that in the event of a power failure event in this operation, it is unnecessary to perform data erasing operation in the process of saving power failure data.
  • the power supply detecting module monitors the operation of the system power supply in real time, and the basis of determining a power failure event may be detecting that the power supply voltage drops to a threshold.
  • the log file for the running of the system is stored in the external SDRAM in a file form.
  • the “parameter” may refer to all the data in the high-speed SRAM to be saved in a power failure, and may contain several sampling values. Each sampling value corresponds to a previous sampling. Each sampling value is circulated in a chronological sequence, and the latest sampling value overrides the sampling value with the longest time.
  • the most important voltage, current and other data values may not be subjected to data processing.
  • the less important semaphore, switch quantity and other data may be subjected to data encoding processing. Each sample occupies only one or more bits.
  • the log file for the running of the system may be stored in the external SDRAM in a file form.
  • the power supply detecting module informs the controller module by virtue of interruption.
  • the controller module executes the protection mechanism program in the high-speed SRAM, reads the most important voltage, current and other data immediately, writes the sampling value circulation in the high-speed SRAM, labels the latest value for distinguishing, and then writes the parameter immediately to SPI NOR FLASH.
  • the controller module executes the protection mechanism program in the high-speed SRAM, reads the less important semaphore, switch quantity and other data, writes the sampling value circulation in the high-speed SRAM, labels the latest value for distinguishing, and then writes the parameter immediately to SPI NOR FLASH.
  • the controller module read the latest log file for the running of the system from the external SDRAM, and then performs file compression and writes the file to SPI NOR FLASH. Since there may be a power failure at any time in this step, the log file may be saved incompletely.
  • each module or step of the embodiment of the present disclosure may be implemented by a universal computing device, and the modules or steps may be concentrated on a single computing device or distributed on a network formed by a plurality of computing devices, and may optionally be implemented by programmable codes executable for the computing devices, so that the modules or steps may be stored in a storage medium for execution with the computing devices, and, in some cases, the steps shown or described may be performed in a order different from the order herein, or the modules or steps may form each integrated circuit module, or multiple modules or steps therein may form a single integrated circuit module for implementation.
  • the present disclosure is not limited to any specific hardware and software combination.
  • the problem of increased system cost due to the use of a backup power supply when the power failure data is saved in the related art is solved.
  • the power failure data can be saved without using a backup power supply.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Power Sources (AREA)
  • Retry When Errors Occur (AREA)
US15/514,446 2014-09-24 2015-02-10 Data saving method, device and terminal Abandoned US20170277603A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CN201410495841.4 2014-09-24
CN201410495841.4A CN105512056A (zh) 2014-09-24 2014-09-24 数据保存方法、装置及终端
PCT/CN2015/072700 WO2016045303A1 (zh) 2014-09-24 2015-02-10 数据保存方法、装置及终端

Publications (1)

Publication Number Publication Date
US20170277603A1 true US20170277603A1 (en) 2017-09-28

Family

ID=55580212

Family Applications (1)

Application Number Title Priority Date Filing Date
US15/514,446 Abandoned US20170277603A1 (en) 2014-09-24 2015-02-10 Data saving method, device and terminal

Country Status (5)

Country Link
US (1) US20170277603A1 (zh)
EP (1) EP3200085A4 (zh)
JP (1) JP2017537369A (zh)
CN (1) CN105512056A (zh)
WO (1) WO2016045303A1 (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170330403A1 (en) * 2014-12-03 2017-11-16 Giesecke & Devrient Gmbh Banknote processing machine having power control electronics
US20200293199A1 (en) * 2014-10-28 2020-09-17 SK Hynix Inc. Memory device
CN114780356A (zh) * 2022-06-22 2022-07-22 北京得瑞领新科技有限公司 Ssd系统日志数据的存储方法及装置、介质、设备
USRE49496E1 (en) 2015-07-30 2023-04-18 SK Hynix Inc. Semiconductor device
US11755255B2 (en) 2014-10-28 2023-09-12 SK Hynix Inc. Memory device comprising a plurality of memories sharing a resistance for impedance matching

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3493060A1 (en) * 2017-11-30 2019-06-05 Vestel Elektronik Sanayi ve Ticaret A.S. Method and electronic device for operating a flash-based file system
CN108763371B (zh) * 2018-05-17 2021-06-18 上海威固信息技术股份有限公司 一种Exfat文件系统断电保护及文件检测恢复方法
CN109215171A (zh) * 2018-08-20 2019-01-15 深圳市长龙铁路电子工程有限公司 一种机车信号设备数据记录的存储方法
CN112882656A (zh) * 2021-02-03 2021-06-01 深圳市麦格米特控制技术有限公司 一种掉电数据存储方法和掉电数据存储电路
CN113312207B (zh) * 2021-05-07 2023-12-05 埃森智能科技（深圳）有限公司 一种采用铁电存储器的数据存储方法及其可编程逻辑控制器
CN113219952B (zh) * 2021-05-10 2022-07-19 东风电子科技股份有限公司 基于车身控制模块bcm功能实现总体控制的方法、装置、处理器及其计算机可读存储介质
JP2023042175A (ja) * 2021-09-14 2023-03-27 キオクシア株式会社 メモリシステム及びメモリシステムの制御方法
CN113791931B (zh) * 2021-09-22 2022-05-17 宁波迦南智能电气股份有限公司 一种电表掉电数据快速存储方法
CN113687710B (zh) * 2021-10-26 2022-03-22 西安羚控电子科技有限公司 一种固定翼无人机的飞控管理计算机掉电处理方法及系统
CN114564416A (zh) * 2022-02-21 2022-05-31 中煤科工集团沈阳研究院有限公司 一种露天煤矿车载终端意外断电数据保存系统及保存方法
CN116166200A (zh) * 2023-03-17 2023-05-26 山东云海国创云计算装备产业创新中心有限公司 一种数据存储方法、系统、计算机设备及存储介质
CN119759624A (zh) * 2024-12-11 2025-04-04 北京忆恒创源科技股份有限公司 存储设备异常掉电时保存固件调试信息的方法和装置

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI308694B (en) * 2005-12-13 2009-04-11 Wistron Corp Method of data protection for computers
CN100428203C (zh) * 2006-11-23 2008-10-22 北京飞天诚信科技有限公司 基于非易失性存储的便携式设备的实现掉电保护的方法
JP4575346B2 (ja) * 2006-11-30 2010-11-04 株式会社東芝 メモリシステム
JP4536785B2 (ja) * 2008-02-01 2010-09-01 富士通株式会社 情報処理装置、該情報処理装置で行われるデータ記憶を制御する制御部およびデータ記憶の制御方法
KR101602939B1 (ko) * 2009-10-16 2016-03-15 삼성전자주식회사 불휘발성 메모리 시스템 및 그것의 데이터 관리 방법
US8566561B2 (en) * 2010-05-14 2013-10-22 Rockwell Automation Technologies, Inc. Method to separate and persist static and dynamic portions of a control application
US9251005B2 (en) * 2010-12-20 2016-02-02 Avago Technologies General Ip (Singapore) Pte. Ltd. Power isolation for memory backup
JP5742362B2 (ja) * 2011-03-28 2015-07-01 富士通株式会社 退避処理装置
JP2012226569A (ja) * 2011-04-20 2012-11-15 Fanuc Ltd 記憶装置のデータ保護装置
CN102307367A (zh) * 2011-08-18 2012-01-04 大唐移动通信设备有限公司 一种通信设备及掉电告警方法
JP2013088928A (ja) * 2011-10-14 2013-05-13 Hitachi Ltd 計算機及びデータ退避方法
CN103135735B (zh) * 2011-11-25 2017-01-25 航天信息股份有限公司 一种掉电保护的控制方法及系统
KR101919934B1 (ko) * 2012-04-19 2018-11-20 삼성전자주식회사 불휘발성 메모리 장치를 제어하는 컨트롤러의 동작 방법 및 극 부호화된 부호어를 불휘발성 메모리 장치의 멀티 비트 데이터에 매핑하는 매핑 패턴을 선택하는 매핑 패턴 선택 방법
US20140219021A1 (en) * 2013-02-07 2014-08-07 Seagate Technology Llc Data protection for unexpected power loss
US9335808B2 (en) * 2013-03-08 2016-05-10 Intel Corporation Indicating critical battery status in mobile devices
JP2014174972A (ja) * 2013-03-13 2014-09-22 Meidensha Corp デジタル形保護継電装置
CN103455449B (zh) * 2013-08-29 2016-12-28 华为技术有限公司 非易失性存储介质访问方法、数据更新方法及设备
CN103744747A (zh) * 2014-01-08 2014-04-23 东南大学 一种用于plc掉电控制装置
CN104035893A (zh) * 2014-06-30 2014-09-10 浪潮(北京)电子信息产业有限公司 一种在计算机异常掉电时的数据保存方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20200293199A1 (en) * 2014-10-28 2020-09-17 SK Hynix Inc. Memory device
US11755255B2 (en) 2014-10-28 2023-09-12 SK Hynix Inc. Memory device comprising a plurality of memories sharing a resistance for impedance matching
US20170330403A1 (en) * 2014-12-03 2017-11-16 Giesecke & Devrient Gmbh Banknote processing machine having power control electronics
US10937266B2 (en) * 2014-12-03 2021-03-02 Giesecke+Devrient Currency Technology Gmbh Banknote processing machine having power control electronics
USRE49496E1 (en) 2015-07-30 2023-04-18 SK Hynix Inc. Semiconductor device
CN114780356A (zh) * 2022-06-22 2022-07-22 北京得瑞领新科技有限公司 Ssd系统日志数据的存储方法及装置、介质、设备

Also Published As

Publication number Publication date
CN105512056A (zh) 2016-04-20
EP3200085A4 (en) 2017-09-27
JP2017537369A (ja) 2017-12-14
WO2016045303A1 (zh) 2016-03-31
EP3200085A1 (en) 2017-08-02

Similar Documents

Publication Publication Date Title
US20170277603A1 (en) Data saving method, device and terminal
US8164967B2 (en) Systems and methods for refreshing non-volatile memory
US8751903B2 (en) Methods and systems for monitoring write operations of non-volatile memory
US10592134B1 (en) Open block stability scanning
CN102004706B (zh) 一种基于ftl的闪存擦写掉电保护方法
US11688483B2 (en) Managing block retirement for temporary operational conditions
US20190347174A1 (en) Power Fail Handling Using Stop Commands
US9652330B2 (en) Method for data management and memory storage device and memory control circuit unit
CN101963891A (zh) 数据存储处理方法与装置、固态硬盘系统与数据处理系统
TW201435729A (zh) 固態硬碟機架構
JP2014120179A (ja) 停電障害状況におけるイベントトレース情報の復旧
US10997516B2 (en) Systems and methods for predicting persistent memory device degradation based on operational parameters
US20120084503A1 (en) Disk control apparatus, disk control method, and storage medium storing disk control program
US12118229B2 (en) Memory sub-system event log management
CN108920094B (zh) 擦除单元raid方法、装置、计算机设备及存储介质
US11928036B2 (en) Recovery from broken mode
JP2015215675A (ja) 制御装置、制御方法、及び制御プログラム
US11733923B2 (en) Generating command snapshots in memory devices
US9880926B1 (en) Log structured reserved zone for a data storage device
CN106354580A (zh) 一种数据恢复方法及装置
US12481549B1 (en) Communication error handling in a memory sub-system
US12542168B2 (en) Data storage device and data protection method thereof
CN112506686A (zh) 一种dcs控制器日志系统实现方法和装置
US20260038546A1 (en) Memory sub-system incomplete shutdown debugging
US20250378900A1 (en) Determining health of a non-volatile memory device based on a predetermined data pattern

Legal Events

Date Code Title Description
AS Assignment

Owner name: ZTE CORPORATION, CHINA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ZHU, SHUKUI;SHI, XIAOFEI;ZHANG, QI;SIGNING DATES FROM 20170304 TO 20170320;REEL/FRAME:041734/0598

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION