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US20170207183A1 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
US20170207183A1
US20170207183A1 US15/249,696 US201615249696A US2017207183A1 US 20170207183 A1 US20170207183 A1 US 20170207183A1 US 201615249696 A US201615249696 A US 201615249696A US 2017207183 A1 US2017207183 A1 US 2017207183A1
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Prior art keywords
electrode
insulating film
semiconductor device
film
semiconductor layer
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US15/249,696
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Naoto ANDO
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Assigned to MITSUBISHI ELECTRIC CORPORATION reassignment MITSUBISHI ELECTRIC CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ANDO, NAOTO
Publication of US20170207183A1 publication Critical patent/US20170207183A1/en
Priority to US16/218,352 priority Critical patent/US10811371B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/564—Details not otherwise provided for, e.g. protection against moisture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/60—Impurity distributions or concentrations
    • H10D62/605—Planar doped, e.g. atomic-plane doped or delta-doped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/64—Electrodes comprising a Schottky barrier to a semiconductor
    • H10D64/647—Schottky drain or source electrodes for IGFETs
    • H10W42/00—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for individual devices of subclass H10D
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H01L29/408—
    • H01L29/66848—
    • H01L29/8128—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/061—Manufacture or treatment of FETs having Schottky gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/061—Manufacture or treatment of FETs having Schottky gates
    • H10D30/0612—Manufacture or treatment of FETs having Schottky gates of lateral single-gate Schottky FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/792—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/87—FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET]
    • H10D30/877—FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET] having recessed gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/118—Electrodes comprising insulating layers having particular dielectric or electrostatic properties, e.g. having static charges
    • H10W20/40—
    • H10W44/20—
    • H10W70/041—
    • H10W70/465—
    • H10W70/481—
    • H10W74/016—
    • H10W74/121—
    • H10W74/137—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6683—High-frequency adaptations for monolithic microwave integrated circuit [MMIC]
    • H10W44/251—
    • H10W90/756—

Definitions

  • the present invention relates to a semiconductor device and a manufacturing method thereof.
  • FET gate electrodes having an caves structure that includes a lower electrode joined to a semiconductor substrate and an upper electrode wider than the lower electrode.
  • An insulating film that covers the gate electrode having such an eaves structure is conventionally formed using a CVD method.
  • the insulating film that covers the lower electrode becomes thinner than other parts, which reduces a water blocking capability, causing moisture resistance to be more likely to deteriorate.
  • the gate electrode having the eaves structure is totally embedded with a thick insulating film (e.g., see JP 2015-99865 A), it is possible to prevent the above-described problem with deterioration of moisture resistance.
  • the present invention has been implemented to solve the above-described problem and it is an object of the present invention to provide a semiconductor device and a manufacturing method thereof capable of preventing deterioration of the moisture resistance and the high-frequency characteristic.
  • a semiconductor device includes: a semiconductor substrate; a semiconductor layer on the semiconductor substrate; a source electrode and a drain electrode spaced apart from each other on the semiconductor layer; a gate electrode on the semiconductor layer between the source electrode and the drain electrode; and insulating film covering the semiconductor layer, the source electrode, the drain electrode and the gate electrode, the gate electrode has an eaves structure including a lower electrode joined to the semiconductor layer and an upper electrode provided on the lower electrode and wider than the lower electrode, a principal ingredient of the insulating film is an oxide film where atomic layers are alternately arrayed for each monolayer, and a film thickness of the insulating film that covers the lower electrode of the gate electrode is equal to a film thickness of the insulating film that covers the upper electrode.
  • a principal ingredient of the insulating film that covers the gate electrode having an eaves structure is an oxide film where atomic layers are alternately arrayed for each monolayer. Furthermore, the film thickness of the insulating film that covers the lower electrode of the gate electrode is equal to the film thickness of the insulating film that covers the upper electrode. Therefore, deterioration of the moisture resistance and the high-frequency characteristic can be prevented.
  • FIG. 1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment of the present invention.
  • FIGS. 2 to 5 are cross-sectional views illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 6 is a cross-sectional view illustrating a semiconductor device according to a comparative example.
  • FIG. 7 is a cross-sectional view illustrating a semiconductor device according to a second embodiment of the present invention.
  • FIG. 8 is a plan view illustrating an interior of the semiconductor device according to the second embodiment of the present invention.
  • FIG. 9 is a cross-sectional view illustrating the semiconductor device in FIG. 7 mounted on a mounting substrate.
  • FIG. 1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment of the present invention.
  • a conductive layer 2 and a cap layer 3 are provided on a semiconductor substrate 1 .
  • the elements are separated from each other by a nonconductor portion 4 .
  • a source electrode 5 and a drain electrode 6 are provided spaced apart from each other on the cap layer 3 .
  • the source electrode 5 and the drain electrode 6 are ohmic-joined to the cap layer 3 .
  • a gate electrode 8 is provided on the conductive layer 2 between the source electrode 5 and the drain electrode 6 .
  • An insulating film 9 covers the conductive layer 2 , the cap layer 3 , the source electrode 5 , the drain electrode 6 and the gate electrode 8 .
  • the insulating film 9 is in direct contact with at least part of the source electrode 5 , the drain electrode 6 and the gate electrode 8 .
  • the gate electrode 8 has an eaves structure including a lower electrode 8 a Schottky-joined to the conductive layer 2 on a bottom surface of the concave portion 7 and an upper electrode 8 b which is provided on the lower electrode 8 a and wider than the lower electrode 8 a .
  • the area of a planar shape of the upper electrode 8 b is greater than the junction area between the lower electrode 8 a and the conductive layer 2 .
  • the insulating film 9 has an oxide film where atomic layers are alternately arrayed for each monolayer as a principal ingredient.
  • the film thickness of the insulating film 9 that covers the lower electrode 8 a of the gate electrode 8 is equal to the film thickness of the insulating film 9 that covers the upper electrode 8 b .
  • cases where both films have the same film thickness include not only a case where the two films are completely the same but also a case where the two films are substantially equal within an error range of ⁇ 10%.
  • FIGS. 2 to 5 are cross-sectional views illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention.
  • the conductive layer 2 and the cap layer 3 are formed on the semiconductor substrate 1 using an epitaxial growth method.
  • the nonconductor portion 4 is formed and the elements are separated apart from each other.
  • the source electrode 5 and the drain electrode 6 are formed on the cap layer 3 using, for example, a vapor deposition lift-off method.
  • a gate generating resist 10 for forming an eaves structure is formed.
  • the concave portion 7 is formed by etching the conductive layer 2 and the cap layer 3 with, for example, phosphoric acid so that a desired amount of current is obtained.
  • the gate electrode 8 having an eaves structure is formed using, for example, a vapor deposition lift-off method.
  • the insulating film 9 that covers the conductive layer 2 , the cap layer 3 , the source electrode 5 , the drain electrode 6 and the gate electrode 8 is formed.
  • the insulating film 9 is formed using a method of laminating films of molecules of raw material compound by repeating steps of film formation through surface adsorption and reaction and removal of surplus molecules through purging for each monolayer, such as ALD (atomic layer deposition). After that, the respective elements are connected by wiring and a protective film to cover them is formed, and the semiconductor device is thus manufactured.
  • ALD atomic layer deposition
  • FIG. 6 is a cross-sectional view illustrating a semiconductor device according to a comparative example.
  • an insulating film 11 that covers the gate electrode 8 having an eaves structure is formed using a CVD method.
  • the insulating film 11 that covers the lower electrode 8 a becomes thinner than other parts. Therefore, its water blocking capability decreases, causing moisture resistance to be more likely to deteriorate.
  • the present embodiment forms the insulating film 9 that covers the gate electrode 8 having an eaves structure using a method of laminating films of molecules of raw material compound by repeating steps of film formation through surface adsorption and reaction and removal of surplus molecules through purging for each monolayer, such as ALD. That is, a principal ingredient of the insulating film 9 is an oxide film where atomic layers are alternately arrayed for each monolayer. It is thereby possible to make the film thickness of the insulating film 11 that covers the lower electrode 8 a of the gate electrode 8 equal to the film thickness of the insulating film 11 that covers the upper electrode 8 b . Therefore, it is possible to prevent a decrease in moisture resistance due to an insufficient film thickness. Moreover, since the film thickness of the insulating film 9 need not be increased more than necessary to prevent a decrease in moisture resistance, it is also possible to prevent deterioration of the high frequency characteristic.
  • the insulating film 9 is an insulating film whose principal ingredient is a Ta oxide film. Without being limited to this, however, the insulating film 9 may also be an insulating film whose principal ingredient is a Si oxide film or an insulating film whose principal ingredient is a layered structure of a Ta oxide film and a Si oxide film. Using the layered structure of a Ta oxide film and a Si oxide film in particular can improve the reliability and the high-frequency characteristic of the semiconductor device more than their respective single layer structures.
  • FIG. 7 is a cross-sectional view illustrating a semiconductor device according to a second embodiment of the present invention.
  • FIG. 8 is a plan view illustrating an interior of the semiconductor device according to the second embodiment of the present invention.
  • FIG. 9 is a cross-sectional view illustrating the semiconductor device in FIG. 7 mounted on a mounting substrate.
  • a semiconductor chip 11 is, for example, a transistor and a wiring structure provided on a semiconductor substrate.
  • the semiconductor chip 11 is connected to leads 13 via wires 12 .
  • Parts of the semiconductor chip 11 , the wires 12 and the leads 13 are covered with mold resin or the like, and a package 14 in which the semiconductor chip 11 is mounted is formed.
  • An insulating film 15 covers an entire case of the package 14 .
  • the package 14 is mounted on a mounting substrate 16 . In this case, the leads 13 are joined to electrodes 17 on the mounting substrate 16 .
  • the insulating film 15 is formed using a method of laminating films of molecules of raw material compound by repeating steps of film formation through surface adsorption and reaction and removal of surplus molecules through purging for each monolayer, such as ALD. That is, a film whose principal ingredient is an oxide film on which atomic layers are alternately arrayed for each monolayer is used as the insulating film 15 .
  • the insulating film 15 of the present embodiment can cover all exposed portions of the case of the package 14 with a film of uniform thickness. Therefore, it is possible to prevent deterioration of moisture resistance of an FET or MMIC in the package 14 due to the high difference in height and insufficient film thickness in the rear portion.
  • the insulating film 15 is an insulating film whose principal ingredient is a Ta oxide film.
  • the insulating film 15 may also be an insulating film whose principal ingredient is a Si oxide film or the insulating film 15 may be an insulating film whose principal ingredient is a layered structure of a Ta oxide film and a Si oxide film.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Manufacturing & Machinery (AREA)
  • Formation Of Insulating Films (AREA)
  • Chemical Vapour Deposition (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A semiconductor device includes: a semiconductor substrate; a semiconductor layer on the semiconductor substrate; a source electrode and a drain electrode spaced apart from each other on the semiconductor layer; a gate electrode on the semiconductor layer between the source electrode and the drain electrode; and an insulating film covering the semiconductor layer, the source electrode, the drain electrode and the gate electrode, the gate electrode has an eaves structure including a lower electrode joined to the semiconductor layer and an upper electrode provided on the lower electrode and wider than the lower electrode, a principal ingredient of the insulating film is an oxide film where atomic layers are alternately arrayed for each monolayer, and a film thickness of the insulating film that covers the lower electrode of the gate electrode is equal to a film thickness of the insulating film that covers the upper electrode.

Description

    BACKGROUND OF THE INVENTION
  • Field
  • The present invention relates to a semiconductor device and a manufacturing method thereof.
  • Background
  • There are FET gate electrodes having an caves structure that includes a lower electrode joined to a semiconductor substrate and an upper electrode wider than the lower electrode. An insulating film that covers the gate electrode having such an eaves structure is conventionally formed using a CVD method. However, since the supply of an insulating film material to the lower part of the eaves decreases, the insulating film that covers the lower electrode becomes thinner than other parts, which reduces a water blocking capability, causing moisture resistance to be more likely to deteriorate. Note that if the gate electrode having the eaves structure is totally embedded with a thick insulating film (e.g., see JP 2015-99865 A), it is possible to prevent the above-described problem with deterioration of moisture resistance.
  • However, embedding the gate electrode with a thick insulating film to prevent the problem with deterioration of moisture resistance may lead to the problem that the film thickness of the insulating film increases more than necessary, causing the high-frequency characteristic of the FET to deteriorate.
    • Summary
  • The present invention has been implemented to solve the above-described problem and it is an object of the present invention to provide a semiconductor device and a manufacturing method thereof capable of preventing deterioration of the moisture resistance and the high-frequency characteristic.
  • According to the present invention, a semiconductor device includes: a semiconductor substrate; a semiconductor layer on the semiconductor substrate; a source electrode and a drain electrode spaced apart from each other on the semiconductor layer; a gate electrode on the semiconductor layer between the source electrode and the drain electrode; and insulating film covering the semiconductor layer, the source electrode, the drain electrode and the gate electrode, the gate electrode has an eaves structure including a lower electrode joined to the semiconductor layer and an upper electrode provided on the lower electrode and wider than the lower electrode, a principal ingredient of the insulating film is an oxide film where atomic layers are alternately arrayed for each monolayer, and a film thickness of the insulating film that covers the lower electrode of the gate electrode is equal to a film thickness of the insulating film that covers the upper electrode.
  • In the present invention, a principal ingredient of the insulating film that covers the gate electrode having an eaves structure is an oxide film where atomic layers are alternately arrayed for each monolayer. Furthermore, the film thickness of the insulating film that covers the lower electrode of the gate electrode is equal to the film thickness of the insulating film that covers the upper electrode. Therefore, deterioration of the moisture resistance and the high-frequency characteristic can be prevented.
  • Other and further objects, features and advantages of the invention will appear more from the following description.
    • BRIEF DESCRIPTION OF DRAWINGS
  • FIG. 1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment of the present invention.
  • FIGS. 2 to 5 are cross-sectional views illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 6 is a cross-sectional view illustrating a semiconductor device according to a comparative example.
  • FIG. 7 is a cross-sectional view illustrating a semiconductor device according to a second embodiment of the present invention.
  • FIG. 8 is a plan view illustrating an interior of the semiconductor device according to the second embodiment of the present invention.
  • FIG. 9 is a cross-sectional view illustrating the semiconductor device in FIG. 7 mounted on a mounting substrate.
    •  DESCRIPTION OF EMBODIMENTS
  • A semiconductor device and a manufacturing method thereof according to the embodiments of the present invention will be described with reference to the drawings. The same components will be denoted by the same symbols, and the repeated description thereof may be omitted.
  • First Embodiment
  • FIG. 1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment of the present invention. A conductive layer 2 and a cap layer 3 are provided on a semiconductor substrate 1. The elements are separated from each other by a nonconductor portion 4. A source electrode 5 and a drain electrode 6 are provided spaced apart from each other on the cap layer 3. The source electrode 5 and the drain electrode 6 are ohmic-joined to the cap layer 3.
  • Part of the cap layer 3 is removed and a concave portion 7 is formed there. A gate electrode 8 is provided on the conductive layer 2 between the source electrode 5 and the drain electrode 6. An insulating film 9 covers the conductive layer 2, the cap layer 3, the source electrode 5, the drain electrode 6 and the gate electrode 8. The insulating film 9 is in direct contact with at least part of the source electrode 5, the drain electrode 6 and the gate electrode 8.
  • The gate electrode 8 has an eaves structure including a lower electrode 8 a Schottky-joined to the conductive layer 2 on a bottom surface of the concave portion 7 and an upper electrode 8 b which is provided on the lower electrode 8 a and wider than the lower electrode 8 a. The area of a planar shape of the upper electrode 8 b is greater than the junction area between the lower electrode 8 a and the conductive layer 2. The insulating film 9 has an oxide film where atomic layers are alternately arrayed for each monolayer as a principal ingredient. The film thickness of the insulating film 9 that covers the lower electrode 8 a of the gate electrode 8 is equal to the film thickness of the insulating film 9 that covers the upper electrode 8 b. Here, cases where both films have the same film thickness include not only a case where the two films are completely the same but also a case where the two films are substantially equal within an error range of ±10%.
  • Next, a method of manufacturing the semiconductor device according to the present embodiment will be described. FIGS. 2 to 5 are cross-sectional views illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention.
  • First, as shown in FIG. 2, the conductive layer 2 and the cap layer 3 are formed on the semiconductor substrate 1 using an epitaxial growth method. By injecting, for example, hydrogen ions after covering only a region where the FET is intended to be formed with a resist or the like, the nonconductor portion 4 is formed and the elements are separated apart from each other.
  • Next, as shown in Fig, 3, the source electrode 5 and the drain electrode 6 are formed on the cap layer 3 using, for example, a vapor deposition lift-off method.
  • Next, as shown in FIG. 4, a gate generating resist 10 for forming an eaves structure is formed. The concave portion 7 is formed by etching the conductive layer 2 and the cap layer 3 with, for example, phosphoric acid so that a desired amount of current is obtained.
  • Next, as shown in FIG. 5, the gate electrode 8 having an eaves structure is formed using, for example, a vapor deposition lift-off method. Next, as shown in FIG. 1, the insulating film 9 that covers the conductive layer 2, the cap layer 3, the source electrode 5, the drain electrode 6 and the gate electrode 8 is formed. Here, the insulating film 9 is formed using a method of laminating films of molecules of raw material compound by repeating steps of film formation through surface adsorption and reaction and removal of surplus molecules through purging for each monolayer, such as ALD (atomic layer deposition). After that, the respective elements are connected by wiring and a protective film to cover them is formed, and the semiconductor device is thus manufactured.
  • Next, effects of the present embodiment will be described in comparison with a comparative example. FIG. 6 is a cross-sectional view illustrating a semiconductor device according to a comparative example. In the comparative example, an insulating film 11 that covers the gate electrode 8 having an eaves structure is formed using a CVD method. However, since the interval between the eaves of the gate electrode 8 and a bottom surface of the concave portion 7 is narrow and the supply of the insulating film material decreases, the insulating film 11 that covers the lower electrode 8 a becomes thinner than other parts. Therefore, its water blocking capability decreases, causing moisture resistance to be more likely to deteriorate.
  • In contrast, the present embodiment forms the insulating film 9 that covers the gate electrode 8 having an eaves structure using a method of laminating films of molecules of raw material compound by repeating steps of film formation through surface adsorption and reaction and removal of surplus molecules through purging for each monolayer, such as ALD. That is, a principal ingredient of the insulating film 9 is an oxide film where atomic layers are alternately arrayed for each monolayer. It is thereby possible to make the film thickness of the insulating film 11 that covers the lower electrode 8 a of the gate electrode 8 equal to the film thickness of the insulating film 11 that covers the upper electrode 8 b. Therefore, it is possible to prevent a decrease in moisture resistance due to an insufficient film thickness. Moreover, since the film thickness of the insulating film 9 need not be increased more than necessary to prevent a decrease in moisture resistance, it is also possible to prevent deterioration of the high frequency characteristic.
  • The insulating film 9 is an insulating film whose principal ingredient is a Ta oxide film. Without being limited to this, however, the insulating film 9 may also be an insulating film whose principal ingredient is a Si oxide film or an insulating film whose principal ingredient is a layered structure of a Ta oxide film and a Si oxide film. Using the layered structure of a Ta oxide film and a Si oxide film in particular can improve the reliability and the high-frequency characteristic of the semiconductor device more than their respective single layer structures.
  • Second Embodiment
  • FIG. 7 is a cross-sectional view illustrating a semiconductor device according to a second embodiment of the present invention. FIG. 8 is a plan view illustrating an interior of the semiconductor device according to the second embodiment of the present invention. FIG. 9 is a cross-sectional view illustrating the semiconductor device in FIG. 7 mounted on a mounting substrate.
  • A semiconductor chip 11 is, for example, a transistor and a wiring structure provided on a semiconductor substrate. The semiconductor chip 11 is connected to leads 13 via wires 12. Parts of the semiconductor chip 11, the wires 12 and the leads 13 are covered with mold resin or the like, and a package 14 in which the semiconductor chip 11 is mounted is formed. An insulating film 15 covers an entire case of the package 14. The package 14 is mounted on a mounting substrate 16. In this case, the leads 13 are joined to electrodes 17 on the mounting substrate 16.
  • The insulating film 15 is formed using a method of laminating films of molecules of raw material compound by repeating steps of film formation through surface adsorption and reaction and removal of surplus molecules through purging for each monolayer, such as ALD. That is, a film whose principal ingredient is an oxide film on which atomic layers are alternately arrayed for each monolayer is used as the insulating film 15.
  • Although the package 14 mounted with the semiconductor chip 11 includes a large difference in height, the insulating film 15 of the present embodiment can cover all exposed portions of the case of the package 14 with a film of uniform thickness. Therefore, it is possible to prevent deterioration of moisture resistance of an FET or MMIC in the package 14 due to the high difference in height and insufficient film thickness in the rear portion.
  • Furthermore, the insulating film 15 is an insulating film whose principal ingredient is a Ta oxide film. Without being limited to this, however, the insulating film 15 may also be an insulating film whose principal ingredient is a Si oxide film or the insulating film 15 may be an insulating film whose principal ingredient is a layered structure of a Ta oxide film and a Si oxide film.
  • Obviously many modifications and variations of the present invention are possible in the light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described.
  • The entire disclosure of Japanese Patent Application No. 2016-005382, filed on Jan. 14, 2016 including specification, claims, drawings and summary, on which the Convention priority of the present application is based, is incorporated herein by reference in its entirety.

Claims (11)

1. A semiconductor device comprising:
a semiconductor substrate;
a semiconductor layer on the semiconductor substrate;
a source electrode and a drain electrode spaced apart from each other on the semiconductor layer;
a gate electrode on the semiconductor layer between the source electrode and the drain electrode; and
an insulating film covering the semiconductor layer, the source electrode, the drain electrode and the gate electrode,
the gate electrode has an eaves structure including a lower electrode joined to the semiconductor layer and an upper electrode provided on the lower electrode and wider than the lower electrode,
a principal ingredient of the insulating film is an oxide film where atomic layers are alternately arrayed for each monolayer, and
a film thickness of the insulating film that covers the lower electrode of the gate electrode is equal to a film thickness of the insulating film that covers the upper electrode.
2. The semiconductor device of claim 1, wherein a concave portion is formed in the semiconductor layer, and the lower electrode of the gate electrode is joined to a bottom surface of the concave portion
3. The semiconductor device of claim 1, wherein the principal ingredient of the insulating film is a Ta oxide film.
4. The semiconductor device of claim 1, wherein the principal ingredient of the insulating film is a Si oxide film.
5. The semiconductor device of claim 1, wherein the principal ingredient of the insulating film is a layered structure of a Ta oxide film and a Si oxide film.
6. A semiconductor device comprising:
a semiconductor chip;
a package in which the semiconductor chip is mounted; and
an insulating film covering the package,
wherein a principal ingredient of the insulating film is an oxide film where atomic layers are alternately arrayed for each monolayer.
7. The semiconductor device of claim 6, wherein the principal ingredient of the insulating film is a Ta oxide film.
8. The semiconductor device of claim 6, wherein the principal ingredient of the insulating film is a Si oxide film.
9. The semiconductor device of claim 6, wherein the principal ingredient of the insulating film is a layered structure of a Ta oxide film and a Si oxide film.
10. A manufacturing method of a semiconductor device comprising:
forming a semiconductor layer on a semiconductor substrate;
forming a source electrode and a drain electrode spaced apart from each other on the semiconductor layer;
forming a gate electrode on the semiconductor layer between the source electrode and the drain electrode; and
forming an insulating film covering the semiconductor layer, the source electrode, the drain electrode and the gate electrode,
the gate electrode has an eaves structure including a lower electrode joined to the semiconductor layer and an upper electrode provided on the lower electrode and wider than the lower electrode,
the insulating film is formed using a method of laminating films of molecules of raw material compound by repeating steps of film formation through surface adsorption and reaction and removal of surplus molecules through purging for each monolayer, and
a film thickness of the insulating film that covers the lower electrode of the gate electrode is equal to a film thickness of the insulating film that covers the upper electrode.
11. A manufacturing method of a semiconductor device comprising:
forming a package in which the semiconductor chip is mounted; and
forming an insulating film covering the package,
wherein the insulating film is formed using a method of laminating films of molecules of raw material compound by repeating steps of film formation through surface adsorption and reaction and removal of surplus molecules through purging for each monolayer.
US15/249,696 2016-01-14 2016-08-29 Semiconductor device and manufacturing method thereof Abandoned US20170207183A1 (en)

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JP6672812B2 (en) 2020-03-25
CN106972059A (en) 2017-07-21
KR20170085431A (en) 2017-07-24
CN106972059B (en) 2021-06-29
JP2017126670A (en) 2017-07-20

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