US20170077231A1

US20170077231A1 - SiGe CMOS WITH TENSELY STRAINED NFET AND COMPRESSIVELY STRAINED PFET

Info

Publication number: US20170077231A1
Application number: US14/849,683
Authority: US
Inventors: Karthik Balakrishnan; Kangguo Cheng; Pouya Hashemi; Alexander Reznicek
Original assignee: International Business Machines Corp
Current assignee: International Business Machines Corp
Priority date: 2015-09-10
Filing date: 2015-09-10
Publication date: 2017-03-16
Anticipated expiration: 2035-09-10
Also published as: US9685510B2

Abstract

A method includes providing a Si substrate having an overlying layer of Si_1-xGe_x; growing, over the layer of Si_1-xGe, a layer of Si in an NFET region and a second layer of Si_1-xGe_xin a PFET region; partitioning the layer of Si_1-xGe_xinto a structure including a first Si_1-xGe_xsub-layer disposed in the NFET region and a second Si_1-xGe_xsub-layer disposed in the PFET region; annealing the structure to convert the first Si_1-xGe_xsub-layer and the overlying Si layer into a tensily strained Si_1-xGe_xintermixed layer and to convert the second Si_1-xGe_xsub-layer and the overlying second layer of Si_1-xGe_xinto a compressively strained Si_1-xGe_xintermixed layer, where a value of x in the tensily strained Si_1-xGe_xintermixed layer is less than a value of x in the compressively strained Si_1-xGe_xintermixed layer and forming a first transistor in the NFET region and a second transistor in the PFET region.

Description

TECHNICAL FIELD

The various embodiments of this invention relate generally to semiconductor devices and fabrication techniques and, more specifically, relate to the fabrication of complementary metal oxide semiconductor (CMOS) transistor devices comprised of SiGe.

BACKGROUND

Tensile strained silicon (s-Si) enhances electron mobility by lifting the conduction band degeneracies, reducing carrier scattering and increasing the population of carriers in sub-bands with lower transverse effective mass. Channel engineering using Si or s-Si for an NFET and compressive strained SiGe for a PFET is one option for realizing small geometry devices while meeting performance targets. However, the fabrication of transistors having a tensile strained silicon germanium (SiGe) channel, for n-type field effect transistors (NFETs), and a compressive strained SiGe channel, for p-type field effect transistors (PFETs), on the same common substrate would provide advantages and would be a desirable goal.

SUMMARY

In a first aspect thereof the embodiments of this invention provide a method that comprises providing a Si substrate having an overlying layer of Si_1-xGe_x; growing, over the layer of Si_1-xGe_x, a layer of Si in what will be an NFET region and a second layer of Si_1-xGe_xin what will be a PFET region; partitioning the layer of Si_1-xGe_xinto a structure comprised of a first Si_1-xGe_xsub-layer disposed in the NFET region and into a second Si_1-xGe_xsub-layer disposed in the PFET region; annealing the structure to convert the first Si_1-xGe_xsub-layer and the overlying Si layer into a tensily strained Si_1-xGe_xintermixed layer and to convert the second Si_1-xGe_xsub-layer and the overlying second layer of Si_1-xGe_xinto a compressively strained Si_1-xGe_xintermixed layer, where a value of x in the tensily strained Si_1-xGe_xintermixed layer is less than a value of x in the compressively strained Si_1-xGe_xintermixed layer; and forming a first transistor device in the NFET region and a second transistor device in the PFET region.
In another aspect thereof the embodiments of this invention provide a structure that comprises a substrate comprised of Si; a layer of dielectric material disposed on a surface of the substrate and a first transistor device disposed over the layer of dielectric material and a second transistor device disposed over the layer of dielectric material. In the structure the first transistor device is an NFET device having a tensily strained channel comprised of a first layer of intermixed Si_1-xGe_x, and the second transistor device is a PFET device having a compressively strained channel comprised of a second layer of intermixed Si_1-xGe_x. In the structure a value of x in the first layer of intermixed Si_1-xGe_xis less than a value of x in the second layer of intermixed Si_1-xGe_x.
In yet another aspect thereof the embodiments of this invention provide a structure that comprises NFET tensile strained CMOS transistors and PFET compressive strained CMOS transistors that are disposed on a common substrate. The structure is fabricated by a process that comprises providing a Si substrate having an overlying layer of Si_1-xGe_x; growing, over the layer of Si_1-xGe_x, a layer of Si in what will be an NFET region and a second layer of Si_1-xGe_xin what will be a PFET region; partitioning the layer of Si_1-xGe_xinto a structure comprised of a first Si_1-xGe_xsub-layer disposed in the NFET region and into a second Si_1-xGe_xsub-layer disposed in the PFET region; annealing the structure to convert the first Si_1-xGe_xsub-layer and the overlying Si layer into a tensily strained Si_1-xGe_xintermixed layer and to convert the second Si_1-xGe_xsub-layer and the overlying second layer of Si_1-xGre_xinto a compressively strained Si_1-xGe_xintermixed layer, where a value of x in the tensily strained Si_1-xGe_xintermixed layer is less than a value of x in the compressively strained Si_1-xGe_xintermixed layer; and forming a first transistor device in the NFET region and a second transistor device in the PFET region.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIGS. 1-5 are each an enlarged cross-sectional view showing various initial, intermediate and completed or substantially completed structures that are fabricated in accordance with embodiments of this invention, wherein the various layer thicknesses and other dimensions are not necessarily drawn to scale. More specifically:

FIG. 1 shows a starting structure (starting wafer) comprised of a Si substrate, an overlying BOX and a layer of strain relaxed Si_1-xGe_x;

FIG. 2 shows a result of performing patterned epitaxial growth processes that are used to grow, over the layer of strain relaxed Si_1-xGe_x, a layer of Si on what will be an NFET region and a layer of Si_1-xGe_xon what will be a PFET region, and that further shows the formation of a trench that partitions the layer of strain relaxed Si_1-xGe_xinto a first Si_1-xGe_xsub-layer disposed in the NFET region and into a second Si_1-xGe_xsub-layer disposed in the PFET region;

FIG. 3 shows a result of deposition of a capping layer and a performance of an anneal process that converts the first Si_1-xGe_xsub-layer and the overlying Si layer into a first Si_1-xGe_xintermixed layer and that simultaneously converts the second Si_1-xGe_xsub-layer and the overlying layer of Si_1-xGe_xinto a second Si_1-xGe_xintermixed layer;

FIG. 4 shows the structure of FIG. 3 after photolithographically defining fins and etching the first Si_1-xGe_xintermixed layer and the second Si_1-xGe_xintermixed layer to form an NFET fin and a PFET fin; and

FIG. 5 illustrates an alternate embodiment where planar CMOS transistors are formed in the first Si_1-xGe_xintermixed layer and in the second Si_1-xGe_xintermixed layer instead of the FinFET CMOS transistors shown in FIG. 4.

DETAILED DESCRIPTION

The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments. All of the embodiments described in this Detailed Description are exemplary embodiments provided to enable persons skilled in the art to make or use the invention and not to limit the scope of the invention which is defined by the claims.
The terms “epitaxial growth and/or deposition” and “epitaxially formed and/or grown” mean the growth of a semiconductor material on a deposition surface of a semiconductor material, in which the semiconductor material being grown has the same crystalline characteristics as the semiconductor material of the deposition surface. In an epitaxial deposition process, the chemical reactants provided by source gases are controlled and the system parameters are set so that the depositing atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the atoms of the deposition surface. Therefore, an epitaxial semiconductor material has the same crystalline characteristics as the deposition surface on which it is formed. For example, an epitaxial semiconductor material deposited on a {100} crystal surface will take on a {100} orientation. In some embodiments, epitaxial growth and/or deposition processes are selective to forming on semiconductor surface, and do not deposit material on dielectric surfaces, such as silicon dioxide or silicon nitride surfaces.
Examples of various epitaxial growth process apparatuses and methods that are suitable for use in implementing the embodiments of this invention can include, but are not limited to, chemical vapor deposition (CVD) such as, for example, rapid thermal chemical vapor deposition (RTCVD), atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD) and ultra-high vacuum chemical vapor deposition (UHVCVD). Other suitable epitaxial growth processes can include, but are not limited to, molecular beam epitaxy (MBE) and low-energy plasma deposition (LEPD). The temperature for an epitaxial deposition process typically ranges from about 300° C. to about 900° C. Although higher temperature will typically result in faster deposition of the semiconductor material, the faster deposition may also result in crystal defects and film cracking.
In at least one embodiment thereof this invention can employ semiconductor on insulator (SOI) technology where a thin semiconductor layer, such as a layer of SiGe, is formed over an insulating layer, such as silicon oxide, which in turn is formed over a (bulk) substrate, such as a Si substrate. The insulating (dielectric) layer can be referred to as a buried oxide (BOX) layer or simply as a BOX. For a single BOX SOI wafer the SOI layer can be divided into active regions by shallow trench isolation (STI) which intersects the BOX and provides total isolation for active device regions formed in the SOI layer. For FinFET devices fin structures can be defined in the SOI layer and sources and drains can be formed, for example, by ion implantation of N-type or P-type dopants into the fins. A FET channel region between a source/drain pair can be created so as to underlie a gate structure.
It is pointed out that while certain aspects and embodiments of this invention can be employed with SOI substrates, such as a SiGe on insulator substrate, in some further embodiments a bulk (e.g., SiGe) substrate might be used,
The embodiments of this invention pertain to a CMOS integrated circuit with SiGe channels for both NFETs and PFETs, wherein the NFETs are tensily strained and the PFETs are compressively strained.
FIG. 1 shows a starting structure (starting wafer) that can be comprised of a Si substrate 10 of arbitrary thickness, an overlying layer of BOX 12 having an exemplary thickness in a range of about 10 nm-400 nm, and a layer 14 of strain relaxed Si_1-xGe_x(e.g., where x can have a value in a range of about 0.15 to about 0.40). The layer 14 of Si_1-xGe_xcould have an exemplary thickness in a range of about 1 nm to about 20 nm, with about 4 nm being one suitable nominal value. The layer 14 of Si_1-xGe_xcan be formed using, for example, Ge intermix or Ge thermal condensation processes with initial layers of Si and Ge (e.g., carried out at an exemplary temperature of about 1200° C.). The layer 14 of Si_1-xGe_xcan also be formed using, for example, a wafer bonding process where the layer 14 of Si_1-xGe_xis disposed on a handle wafer and thermally bonded to the BOX 12, followed by removal of the handle wafer and thinning, if needed, of the layer 14 of Si_1-xGe_xto the desired thickness.
FIG. 2 shows a result of performing patterned epitaxial growth processes that are used to grow a layer 16 of Si on what will be an NFET region and to grow a layer 18 of Si_1-xGe_x(e.g., x=0.50) on what will be a PFET region. This can be accomplished by applying a mask to the surface of the layer 14 of Si_1-xGe_xin the PFET region and epitaxially growing the Si layer 16 upon the surface of the layer 14 of Si_1-xGe_xin the NFET region. The Si layer 16 can have an exemplary thickness in a range of about 10 nm to about 60 nm, with about 40 nm-50 nm being suitable nominal values. The thickness is preferably less that the critical thickness so as to minimize a presence of dislocation defects. This can be followed by applying a mask to a top surface of the Si layer 16 and then epitaxially growing the layer 18 of Si_1-xGe_xupon the surface of the layer 14 of Si_1-xGe_xin the PFET region. It should be noted that the layer 18 of Si_1-xGe_xcould be grown prior to growing the layer of 16 of Si. In the layer 18 the value of x is greater than the value of x in the layer 14 of Si_1-xGe_x. For example, if the value of x in the layer 14 of Si_1-xGe_xis in the range of about 0.15 to about 0.40 then the value of x in the layer 18 of Si_1-xGe_xcan be in a range of about 0.40 to about 0.70. The thickness of the layer 18 is preferably equal to or substantially equal to the thickness of the layer 16.
A trench 20 is formed to physically and electrically isolate the NFET region from PFET region. The trench 20 preferably extends downwards at least to the top surface of the BOX 12. The trench 20 can be formed by partially masking the layers 16 and 18 and then etching the exposed semiconductor material. The trench 20 can be considered to partition the layer 14 of Si_1-xGe_xinto a first Si_i-_xGe_x sub-layer 14A that is disposed in the NFET region and into a second Si_1-xGe_xsub-layer 14B that is disposed in the PFET region.
FIG. 3 shows a result of deposition of a capping layer 22, e.g., one composed of an oxide or a nitride, that fills the trench 20, as well as the performance of a thermal anneal process (e.g., one conducted at an exemplary temperature of about 1000° C.) to mix the Si and the Ge. The anneal converts the first Si_1-xGe_x sub-layer 14A and the overlying Si layer 16 into a first Si_1-xGe_xintermixed layer 16A and simultaneously converts the second Si_1-xGe_xsub-layer 14B and the overlying layer 18 of Si_1-xGe_xinto a second Si_1-xGe_xintermixed layer 18A. In the NFET region the final Ge percentage of the first Si_1-xGe_xintermixed layer 16A is less than the original Ge percentage of the relaxed layer 14 of Si_1-xGe_xdue to the dilution resulting from the presence of the Si layer 16. For example, and assuming the various layer thicknesses and Ge concentrations noted above, the Ge concentration in the first Si_1-xGe_xintermixed layer 16A could be about 0.05%. Due to the resulting difference in the lattice between the first Si_1-xGe_xintermixed layer 16A and the Si substrate 10 the first Si_1-xGe_xintermixed layer 16A is tensile strained. In the PFET region the final Ge percentage of the second Si_1-xGe_xintermixed layer 18A is greater than the original Ge percentage of the relaxed layer 14 of Si_1-xGe_xdue to the Ge enhancement resulting from the presence of the SiGe layer 18 that has the greater Ge percentage than the underlying second Si_1-xGe_xsub-layer 14B. Due to the resulting difference in the lattice between the second Si_1-xGe_xintermixed layer 18A and the Si substrate 10 the second Si_1-xGe_xintermixed layer 18A is compressively strained.
FIG. 4 shows the structure of FIG. 3 after photolithographically defining fins and etching the first Si_1-xGe_xintermixed layer 16A and the second Si_1-xGe_xintermixed layer 18A to form an NFET fin 24A and a PFET fin 24B. The capping layer 22 can first be removed and fin patterning masks applied or it can be patterned and selectively removed to leave portions where fins 24A and 24B are desired. The NFET fin 24A is tensile strained and the PFET fin 24B is compressively strained. The height of the fins 24A, 24B is comparable to the sum of the thicknesses of the layer 14 of Si_1-xGe_x(e.g., about 4 nm) and the thicknesses of the Si layer 16 and the Si_1-xGe_xlayer 18 (e.g., 40 nm). If desired, and by example, the thicknesses of the first Si_1-xGe_xintermixed layer 16A and the second Si_1-xGe_xintermixed layer 18A can be adjusted prior to fin patterning to obtain a desired fin height for the fins 24A and 24B. The fins 24A and 24B can have a width governed by the width of the fin patterning mask, e.g., about 7 nm to about 14 nm (or greater). The fin length can have any desired value depending on the end use. Processing of the fins 24A and 24B can then continue in a conventional manner to form source/drains (S/Ds), gate structures, dielectric layer deposition(s) and vertical and horizontal metallization as needed for the final circuitry.
FIG. 5 illustrates an alternate embodiment where planar CMOS transistors are formed instead of the FinFET CMOS transistors shown in FIG. 4. In this embodiment the first Si_1-xGe_xintermixed layer 16A and the second Si_1-xGe_xintermixed layer 18A are processed to fabricate a planar NFET 26A and a planar PFET 26B by forming source (S), channel (C) and drain (D) regions adjacent to the top surfaces. For example, the surfaces can be implanted with suitable S/D dopants followed by other conventional processes to form S/D contacts, gate stack structures and contacts, dielectric layer deposition(s) and vertical and horizontal metallization as needed for the final circuitry. In some embodiments the S/Ds could be raised S/Ds. A STI 28 can be formed (if the capping layer material that fills the trench 20 is not retained) to electrically isolate the planar NFET device 26A from the planar PFET device 26B. In this embodiment the channel of the planar NFET 26A is tensily strained and the channel of the planar PFET 26B is compressively strained. It can be noted that in some embodiments both the FinFET device structures of FIG. 4 and the planar device structures of FIG. 5 can be formed on the same Si substrate 10.
In view of the foregoing description of the exemplary embodiments of this invention it can be realized that a semiconductor structure can be formed over a substrate to comprise an NFET and a PFET, where both the NFET and the PFET have SiGe channels, where the NFET has a lower Ge % than the PFET, where the NFET SiGe is tensily strained and where the PFET SiGe is compressively strained.
It is noted that any one of the structures shown in FIGS. 1-5 could be viewed as an intermediate structure formed during the overall process of providing the semiconductor structure.
It is to be understood that although the exemplary embodiments discussed above with reference to FIGS. 1-5 can be used on common variants of the FET device including, e.g., FET devices with multi-fingered FIN and/or gate structures and FET devices of varying gate width and length. Moreover, transistor devices can be connected to metalized pads or other devices by conventional ultra-large-scale integration (ULSI) metalization and lithographic techniques.
Integrated circuit dies can be fabricated with various devices such as a field-effect transistors, bipolar transistors, metal-oxide-semiconductor transistors, diodes, resistors, capacitors, inductors, etc. An integrated circuit in accordance with the present invention can be employed in applications, hardware, and/or electronic systems. Suitable hardware and systems in which such integrated circuits can be incorporated include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell phones), solid-state media storage devices, functional circuitry, etc. Systems and hardware incorporating such integrated circuits are considered part of this invention. Given the teachings of the invention provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of the techniques of the invention.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated. As such, various modifications and adaptations may become apparent to those skilled in the relevant arts in view of the foregoing description, when read in conjunction with the accompanying drawings and the appended claims. As but some examples, the use of other similar or equivalent semiconductor fabrication processes, including deposition processes and etching processes may be used by those skilled in the art. Further, the exemplary embodiments are not intended to be limited to only those materials, insulators, Ge concentrations, layer thicknesses and the like that were specifically disclosed above. Any and all such and similar modifications of the teachings of this invention will still fall within the scope of this invention.

Claims

1. A method, comprising:

providing a Si substrate having an overlying first layer of Si_1-xGe_x;

growing, over the first layer of Si_1-xGe_x, a layer of Si in what will be an NFET region and a second layer of Si_1-xGe_xin what will be a PFET region, where the second layer of Si_1-xGe_xis grown directly upon a top surface of the first layer of Si_1-xGe_x;

partitioning the first layer of Si_1-xGe_xinto a structure comprised of a first Si_1-xGe_xsub-layer disposed in the NFET region and into a second Si_1-xGe_xsub-layer disposed in the PFET region;

annealing the structure to convert the first Si_1-xGe_xsub-layer and the overlying Si layer into a tensily strained Si_1-xGe_xintermixed layer and to convert the second Si_1-xGe_xsub-layer and the overlying second layer of Si_1-xGe_xinto a compressively strained Si_1-xGe_xintermixed layer, where a value of x in the tensily strained Si_1-xGe_xintermixed layer, due to dilution of the first Si_1-xGe_xsub-layer by the overlying Si layer, is less than a value of x in the compressively strained intermixed layer; and

forming a first transistor device in the NFET region and a second transistor device in the PFET region.

2. The method as in claim 1, where the first layer of Si_1-xGe_xis a strain relaxed Si_1-xGe_xlayer.

3. The method of claim 1, where providing the Si substrate having the overlying first layer of Si_1-xGe_xprovides a dielectric layer disposed between the Si substrate and the first layer of Si_1-xGe_x.

4. The method of claim 1, where in the first layer of x has a value in a range of about 0.15 to about 0.40.

5. The method of claim 1, where the first layer of Si_1-xGe_xhas a thickness in a range of about 10 nm to about 20 nm.

6. The method as in claim 1, where the layer of Si and the second layer of Si_1-xGe_xeach have a thickness in a range of about 10 nm to about 60 nm.

7. The method as in claim 1, where in the second layer of Si_1-xGe_xx has a value in a range of about 0.40 to about 0.70.

8. The method of claim 1, where in the first layer of Si_1-xGe_xhas a value in a range of about 0.15 to about 0.40, and where in the second layer of Si_1-xGe_xhas a value in a range of about 0.40 to about 0.70.

9. The method as in claim 1, where forming the first transistor device in the NFET region and the second transistor device in the PFET region comprises forming a first fin structure in the tensily strained Si_1-xGe_xintermixed layer and forming a second fin structure in the compressively strained Si_1-xGe_xintermixed layer.

10. The method as in claim 1, where forming the first transistor device in the NFET region and the second transistor device in the PFET region comprises forming a first planar transistor structure in the tensily strained Si_1-xGe_xintermixed layer and forming a second planar transistor structure in the compressively strained Si_1-xGe_xintermixed layer.

11. A structure, comprising:

a substrate comprised of Si;

a layer of dielectric material disposed on a surface of the substrate;

a first layer of Si_1-xGe_xdisposed over the layer of dielectric material, the first layer of Si_1-xGe_xhaving a top surface and being differentiated into a first sub-layer of Si_1-xGe_xand a second sub-layer of Si_1-xGe_x;

a layer of Si disposed on the top surface of the first sub-layer of Si_1-xGe_xin what will be a tensily strained channel NFET device region; and

a second layer of Si_1-xGe_xdisposed directly on the top surface of the second sub-layer of Si_1-xGe_xin what will be a compressively strained channel PFET device region;

wherein in the first layer of Si_1-xGe_xx has a value in a range of about 0.15 to about 0.40, and wherein in the second layer of Si_1-xGe_xhas a value in a range of about 0.40 to about 0.70.

12. The structure as in claim 11, where the NFET device and the PFET device are both FinFET devices.

13. The structure as in claim 11, where the NFET device and the PFET device are both planar transistor devices.

14. The structure as in claim 11, where the first layer of Si_1-xGe_xis a strain relaxed Si_1-xGe_xlayer.

15. A structure comprising NFET tensile strained CMOS transistors and PFET compressive strained CMOS transistors disposed on a common substrate, the structure fabricated by a process that comprises:

providing a Si substrate having an overlying first layer of Si_1-xGe_x;

growing, over the first layer of Si_1-xGe_xa layer of Si in what will be an NFET region and a second layer of Si_1-xGe_xin what will be a PFET region, where the second layer of Si_1-xGe_xis grown directly upon a top surface of the first layer of Si_1-xGe_xin the PFET region;

annealing the structure to convert the first Si_1-xGe_xsub-layer and the overlying Si layer into a tensily strained Si_1-xGe_xintermixed layer and to convert the second Si_1-xGe_xsub-layer and the overlying second layer of Si_1-xGe_xinto a compressively strained Si_1-xGe_xintermixed layer, where a value of x in the tensily strained Si_1-xGe_xintermixed layer is less than a value of x in the compressively strained Si_1-xGe_xintermixed layer; and

forming a first transistor device in the NFET region and a second transistor device in the PFET region; wherein

the value of x in the tensily strained Si_1-xGe_xintermixed layer is a result of a value of x in the first Si_1-xGe_xsub-layer as diluted by the Si in the overlying layer of Si.

16. The structure as in claim 15, where the first layer of Si_1-xGe_xis a strain relaxed Si_1-xGe_xlayer.

17. The structure as in claim 15, where providing the Si substrate having the overlying first layer of Si_1-xGe_xprovides a dielectric layer disposed between the Si substrate and the first layer of Si_1-xGe_x.

18. The structure as in claim 15, where in the first layer of Si_1-xGe_xx has a value in a range of about 0.15 to about 0.40, and where the first layer of Si_1-xGe_xhas a thickness in a range of about 1 nm to about 20 nm, where the layer of Si and the second layer of Si_1-xGe_xeach have a thickness in a range of about 10 nm to about 60 nm, and where in the second layer of Si_1-xGe_xx has a value in a range of about 0.40 to about 0.70.

19. The structure as in claim 15, where forming the first transistor device in the NFET region and the second transistor device in the PFET region comprises forming a first fin structure in the tensily strained Si_1-xGe_xintermixed layer and forming a second fin structure in the compressively strained Si_1-xGe_xintermixed layer.

20. The structure as in claim 15, where forming the first transistor device in the NFET region and the second transistor device in the PFET region comprises forming a first planar transistor structure in the tensily strained Si_1-xGe_xintermixed layer and forming a second planar transistor structure in the compressively strained Si_1-xGe_xintermixed layer.