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US20160301414A1 - Dynamic Interconnect with Partitioning on Emulation and Protyping Platforms - Google Patents

Dynamic Interconnect with Partitioning on Emulation and Protyping Platforms Download PDF

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Publication number
US20160301414A1
US20160301414A1 US15/032,465 US201315032465A US2016301414A1 US 20160301414 A1 US20160301414 A1 US 20160301414A1 US 201315032465 A US201315032465 A US 201315032465A US 2016301414 A1 US2016301414 A1 US 2016301414A1
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Prior art keywords
transmit
interconnect
signal
channel
signals
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Franz-Wilhelm Olbrich
Ralf Plate
Thorsten Mattner
Heiko Woelk
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Intel Corp
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Intel Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H03K19/17744—Structural details of routing resources for input/output signals
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses
    • G06F17/5054—
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form

Definitions

  • the present techniques relate generally to time division data multiplexing and transmission. More specifically, the present techniques relate to a dynamic interconnect with frequency aware capabilities.
  • FPGAs field programmable gate arrays
  • I/O input/output
  • FIG. 1 is an illustration of a dynamic interconnect including a transmit module and a receive module using four transmit channels;
  • FIG. 2 illustrates the timing for signal change detection and changing the transmission order
  • FIG. 3 is a block diagram of an application with channels running on e first partition and a second partition;
  • FIG. 4 is a process flow diagram illustrating a method for a runtime dynamic multiplexing scheme
  • FIG. 5 is a process flow diagram illustrating a method for a frequency aware dynamic multiplexing scheme
  • FIG. 6 an embodiment of a system on-chip (SOC) design in accordance with the inventions is depicted.
  • SOC system on-chip
  • Embodiments described herein are directed toward a dynamic interconnect with partitioning on emulation and prototyping platforms.
  • runtime time division multiplexing (TMD) scheme will enable the transmission of signals between two devices more effectively by using a runtime dynamic multiplexing scheme.
  • the devices can be FGPAs.
  • TMD runtime time division multiplexing
  • the sender can flag the signal change to the receiving chip, and the receiving chip can continue its normal operation after the change signal is de-asserted. Moreover, the receiving chip does not wait on the reception of unchanged signals.
  • the present techniques also uses switching characteristics of the different signal groups into account and selects different interconnect implementations for each group to better utilize the available physical links of the hardware platform.
  • switching characteristics refers to the frequency of signal changes.
  • interconnect implementations may include, but is not limited to different TDM and a different number of required physical links.
  • the switching frequency of the signals may be used when calculating the required TDM schema.
  • Signals which are running on the same application frequency can be grouped, and the knowledge of the required frequency and required interconnect width can be used to calculate the best fitting number of physical links for each individual group. Each group is using a fraction of the whole available number of links.
  • FIG. 1 is an illustration of a dynamic interconnect 100 including a transmit module 102 and a receive module 104 using 4 transmit channels.
  • a dedicated control module 106 selects the channel to be transmitted.
  • the n user signals 108 on the left side are divided into four channels 110 A, 110 B, 110 C, and 110 D.
  • Each channel 110 A, 110 B, 110 C, and 110 D processes a fixed multiplexing scheme synced by the control module 106 .
  • a TDM multiplexer 112 For each channel 110 , such as channel 110 A, a TDM multiplexer 112 is compared with the output of a first in, first out buffer 114 . Signal changes are detected by comparing the TDM multiplex 112 output against the output of a data first in, first out (FIFO) buffer 114 .
  • a start sync signal 113 may be used to start the TDM multiplexer 112 to ensure that each TDM multiplexer for each FPGA has been synced.
  • a counter can be used to as a mechanism to sync the TDM multiplexers.
  • the comparison occurs using an XOR operation at reference number 116 .
  • the signal change detection at 111 will switch the output to the channel where the change has been detected. This channel will then be selected for at least one complete TDM cycle.
  • the FIFO 114 input data is the actual transmission data. Otherwise, the FIFO 114 output data is fed back to the FIFO input. Accordingly, the FIFO 114 input may select from the old FIFO 114 data or the data transmitted from a multiplexer 117 , which is multiplexed at reference number 115 . A source select 128 is used to control the multiplexer 115 so that the correct data is passed back to the FIFO 114 .
  • the transmission order is given by the channel number.
  • the output of each channel is sent to another multiplexer 117 . This multiplexer passes the transmit data output to the receive module 104 .
  • a dedicated control bus 118 is transmitted to the receive module 104 flagging the current transmit channel through a control and channel decode block 120 .
  • the control bus indicates the origination of the data transmitted to the receive block 104 from the multiplexer 117 .
  • the receive TDM de-multiplexer module 122 is synced to the transmit module 102 by evaluating the channel information on the control bus 118 . In some cases, switching from channel three to zero synchronizes the receive-TDM counter.
  • a multiplexer 130 is used to demultiplex the channel data received from the transmit module 102 .
  • the control and channel decode 120 takes as input a control signal 118 and uses this to select a channel of the multiplexer 130 with a channel select signal 132 .
  • the selected channel is then sent as data out of the receive module at reference number 134 .
  • the transmit control module 106 will flag this by de-asserting a “data stable” signal 126 to the application design.
  • the data stable indicates that no changes have been detected. After a configuration period, the data stable signal may be reasserted. This signal 126 could be included in the control bus 118 to the receive module 104 as well.
  • the delay for “data stable” assertion appropriately, the execution of the next application clock cycle could be delayed automatically until the successful transmission of all changing signals to receive side is guaranteed and all signals are stable at receive module output.
  • the design performance is constantly slow based on the calculated worst case signal delay.
  • the system performance is faster as the next application clock edge will be enabled dynamically. Only if a signal is changing on the worst case path the performance could drop down to the same value as in a system without using the dynamic interconnect. Even with a signal change on the worst case path, the design could run faster with our invention as long as there are no signal changes in all channels belonging to the same interconnect module.
  • FIG. 2 illustrates the timing 200 for signal change detection and changing the transmission order.
  • FIG. 2 includes four channels: channel 0 at reference number 110 A, channel 1 at reference number 110 B, channel 2 at reference number 110 C, and channel 3 at reference number 110 D.
  • channel 0 at reference number 110 A has the highest priority
  • channel 1 at reference number 110 B has the second highest priority
  • channel 2 at reference number 110 C has the third highest priority
  • channel 3 at reference number has the lowest priority.
  • the priority can be assigned based on various design parameters, such as application frequency, a different TDM, a different number of physical required links and the like.
  • the transmission slots are illustrated at reference number 202 .
  • Each slot has a number that indicates the channel schedule for transmission at a certain point in time.
  • the transmission slots are of a TDM period of time length.
  • the data change signal at reference number 204 is low when there is no change in data, and is high while this is a change in transmission data.
  • the data stable signal at reference number 206 is high when the data is stable.
  • the data stable signal at reference number 206 is low when the data is changing, and does not return to high until a period of time has elapsed after the last data change. In some cases, the period of time is referred to as a configuration delay.
  • a channel scheduler may select channels for transmission according to any algorithm, such as a round robin algorithm.
  • the input of channel two at reference number 110 C changes. This change de-asserts the data stable signal at reference number 206 for a configurable time and channel two is marked for transmission in the next slot.
  • the configurable time may be any time period implemented by the design. As noted above, each transmission slot lasts TDM transmit clock cycles. The change is marked as long as the channel causing the change has not been transmitted.
  • channel zero at reference number 110 A Since data of channel zero at reference number 110 A changes shortly after channel two at reference number 110 C and channel zero at reference number 110 A has a higher priority, channel zero at reference number 110 A is marked for transmission in the next time slot before channel 2 at reference number 110 C.
  • time “B” at reference number 210 the data of channel one at reference number 110 B and channel three at reference number 110 D are changing.
  • Channel one at reference number 110 B has the higher priority and will be transmitted first, before channel three at reference number 110 D.
  • the channel scheduler After channel three at reference number 110 D is transmitted, the channel scheduler returns to a round robin algorithm, which was interrupted at time “A” and continues by transmitting channel two. The data stable signal will be asserted when the configured time has elapsed after data change de-assertion.
  • the number of transmit channels is configurable. Signal value change detection is applied to each channel, and signal transmission is prioritized for channels with changing signals.
  • a small control bus is used from transmit to receive module.
  • a locking mechanism on transmit side of the interconnect prevents the next application clock edge while signals are changing.
  • the dynamic interconnect results is a very small overhead on receive side compared to a standard TDM demultiplexer module.
  • the application design could run up to number of channel times faster than a system build up using a fixed TDM scheme.
  • FIG. 3 is a block diagram of an application 302 with channels running on e first partition 304 and a second partition 306 .
  • the application 302 is analyzed to determine the different clock domains, and the signals of the application 302 running the different domains are grouped or partitioned according to a respective clock domain.
  • the application includes a first CLK 1 domain at reference number 308 , and a second CLK 2 domain at reference number 310 .
  • two clock domains 308 and 310 are illustrated. However, any number of clock domains can be used.
  • a group of signals n is at reference number 312
  • a group of signals m is at reference number 314 .
  • the group of signals n at reference number 312 runs on the first clock domain 308
  • the group of signals m at reference number 314 runs of the second clock domain 310 .
  • the optimal TDM may be referred to as fmax, and is the highest frequency of all clocks in the application.
  • the clocks of the application are the first CLK 1 domain at reference number 308 , and the second CLK 2 domain at reference number 310 .
  • the number of physical links is represented between partition 304 and partition 306 at reference number 316 .
  • an individual TDM factor for each of the group of signals n at reference number 312 and the group of signals m at reference number 314 can be calculated:
  • n′ f ( n, f 1 , f max , x )
  • n′ is the TDM factor for the group of signals n at reference number 312 and is a function of the group of signals n, the application frequency for a first virtual link running on a physical link f 1 , the optimal TDM f max , and the number of available physical links x.
  • m′ is the TDM factor for the group of signals at reference number 314 and is a function of the group of signals m, the application frequency for a second virtual link running on a physical link f 2 , the optimal TDM f max , and the number of available physical links x.
  • signal groups which are running on slower application frequencies can use a smaller portion of the available physical link between the partitions, but can compensate this by having a higher TDM factor for their link. This can be done because these links have a higher timing budget to get their signal states across the physical link.
  • the signal group with the highest switching frequency should use the smallest TDM factor because this is mainly limiting the emulation performance.
  • FIG. 4 is a process flow diagram illustrating a method for a runtime dynamic multiplexing scheme.
  • a plurality of transmit signals is grouped into parallel compare units.
  • a transmit order of the signals is determined within a parallel compare unit dynamically in response to changing signal values within the parallel compare group and a transmit priority.
  • a data stable signal is de-asserted for a period of time.
  • the period of time may be a configurable time delay, implemented according to the particular design of the system.
  • a signal for transmission is scheduled based on the transmit order of signals.
  • the signals can be assigned slots of time by a channel scheduler. In some cases, the slots of time lasts a length of a TDM transmit clock cycle.
  • FIG. 5 is a process flow diagram illustrating a method for a frequency aware dynamic multiplexing scheme.
  • an application is analyzed for a plurality of clock domains.
  • a plurality of transmit signals is grouped into a number of groups running on the same clock domain. The total number of signals the per each group can be calculated using an application frequency, a required frequency, or a required interconnect width, or any combination thereof is used to calculate the number of physical links.
  • the first row shows N-physical, which is the total number of available physical wires for a link.
  • the link may be a link between two FPGAs.
  • the second row is f1, which represents the application frequency for a first virtual link running on a physical link.
  • the third row is N1-virtual, which designates the number of required virtual wires for the first virtual link running on the physical link.
  • the fourth row is f2, which represents the application frequency for a second virtual link running on the physical link.
  • the fifth row is N2-virtual, which designates the number of required virtual wires for the second virtual link running on the physical link.
  • the “TDM simple” row shows the resulting TDM using a traditional method of multiplexing if all virtual links are just added and routed via the available physical link.
  • the “TDMnew” row is illustrates the resulting TDM factor with the present techniques described herein, which takes the switching frequency of the virtual links into consideration.
  • the last row shows the performance improvement or increase of the present techniques compared to the traditional method of multiplexing.
  • each TDM factor uses more clock cycles to transfer the same amount of data as the new TDM factor according to the techniques described herein.
  • the new TDM factor transfers data between FPGAs using 60 clock cycles, whereas the traditional TDM transfers the same amount of data in 114 clock cycles. In this manner, the number of clock cycles used to transfer data is reduced by 54 clock cycles, which is nearly a 50% improvement.
  • SOC 600 is included in user equipment (UE).
  • UE refers to any device to be used by an end-user to communicate, such as a hand-held phone, smartphone, tablet, ultra-thin notebook, notebook with broadband adapter, or any other similar communication device.
  • a UE connects to a base station or node, which potentially corresponds in nature to a mobile station (MS) in a GSM network.
  • MS mobile station
  • SOC 600 includes 2 cores— 606 and 607 . Similar to the discussion above, cores 606 and 607 may conform to an Instruction Set Architecture, such as an Intel® Architecture CoreTM-based processor, an Advanced Micro Devices, Inc. (AMD) processor, a MIPS-based processor, an ARM-based processor design, or a customer thereof, as well as their licensees or adopters. Cores 606 and 607 are coupled to cache control 608 that is associated with bus interface unit 609 and L2 cache 610 to communicate with other parts of system 600 . Interconnect 610 includes an on-chip interconnect, such as an IOSF, AMBA, or other interconnect discussed above, which potentially implements one or more aspects of the described invention.
  • an Intel® Architecture CoreTM-based processor such as an Intel® Architecture CoreTM-based processor, an Advanced Micro Devices, Inc. (AMD) processor, a MIPS-based processor, an ARM-based processor design, or a customer thereof, as well as their licensees or adopters.
  • Interface 610 provides communication channels to the other components, such as a Subscriber Identity Module (SIM) 630 to interface with a SIM card, a boot ROM 635 to hold boot code for execution by cores 606 and 607 to initialize and boot SOC 600 , a SDRAM controller 640 to interface with external memory (e.g. DRAM 660 ), a flash controller 645 to interface with non-volatile memory (e.g. Flash 665 ), a peripheral control Q 1650 (e.g. Serial Peripheral Interface) to interface with peripherals, video codecs 620 and Video interface 625 to display and receive input (e.g. touch enabled input), GPU 615 to perform graphics related computations, etc. Any of these interfaces may incorporate aspects of the invention described herein.
  • SIM Subscriber Identity Module
  • boot ROM 635 to hold boot code for execution by cores 606 and 607 to initialize and boot SOC 600
  • SDRAM controller 640 to interface with external memory (e.g. DRAM 660 )
  • flash controller 645
  • a UE includes a radio for communication.
  • these peripheral communication modules are not all required.
  • a radio for external communication is to be included.
  • the dynamic interconnect includes a transmit module, a receive module, and a multiplexer. Signal changes are detected in a group of transmit channels, and in response to the signal changes an output of the multiplexer is switched to the channel where the change occurs.
  • Signal changes may be detected by comparing the output of the multiplexer with an output of a data first in, first out buffer.
  • the output of the multiplexer may be switched to the channel where the change occurs for at least one TDM cycle.
  • a transmission order of the coup of transmit channels may be given by a channel number.
  • a dedicated control bus can be transmitted to the receive module, and the dedicated control bus flags the current transmit channel.
  • a TDM demultiplexer of the receive module may be synced to the transmit module by evaluating channel information on the control bus.
  • a transmit control module flags the signal change by de-asserting a data stable signal.
  • the data stable signal can be included on a control bus to the receive module.
  • a configuration of the data stable signal can delay a next clock cycle until a changing signals have been received and are stable, and a switching frequency of the transmit channels is analyzed to determine the group of transmit channels.
  • a method for a runtime dynamic multiplexing scheme includes grouping a plurality of transmit signals into parallel compare units and determining a transmit order of the signals within a parallel compare unit dynamically in response to changing signal values within the parallel compare group and a transmit priority.
  • the method also includes scheduling a signal for transmission based on the transmit order of signals.
  • a data stable signal may be de-asserted for a period of time in response to changing signal values, and the period of time may be configurable time delay.
  • the signals can be assigned slots for transmission in the transmit order of the signals, and each slot lasts TDM transmit clock cycles.
  • the data stable signal can be asserted after the configured time has elapsed from the changing signal values.
  • the frequency aware dynamic interconnect includes a transmit module, a receive module, and a multiplexer.
  • the signal changes are detected in a plurality of groups of transmit channels, which are grouped by an application frequency.
  • an output of the multiplexer is switched to the channel where the change occurs using a number of physical links.
  • At least the application frequency, a required frequency, or a required interconnect width, or any combination thereof can be used to calculate the number of physical links.
  • Each group of transmit channels can use a fraction of the whole number of available links.
  • a sum of a plurality of virtual links can be routed over the available physical link between different partitions and devices.
  • the plurality of groups of transmit channels can be grouped by an application frequency across a plurality of different clock domains.
  • a method for a frequency aware dynamic multiplexing scheme includes analyzing an application for a plurality of clock domains and grouping a plurality of transmit signals into a number of groups running on the same clock domain.
  • the total number of signals per each group can be calculated using an application frequency, a required frequency, or a required interconnect width, or any combination thereof is used to calculate the number of physical links.
  • An optimal time-division-multiplex factor for each frequency group may be calculated based on the number of physical links and other interconnect implementations. Signal groups which are running on slower frequencies can use a smaller portion of the available physical link between the partitions and have a higher time-division-multiplex factor for their link. Signal groups which are running on higher frequencies can use a larger portion of the available physical link between the partitions, and have a lower time-division-multiplex factor for their link.
  • a design may go through various stages, from creation to simulation to fabrication.
  • Data representing a design may represent the design in a number of manners.
  • the hardware may be represented using a hardware description language or another functional description language.
  • a circuit level model with logic and/or transistor gates may be produced at some stages of the design process.
  • most designs, at some stage reach a level of data representing the physical placement of various devices in the hardware model.
  • the data representing the hardware model may be the data specifying the presence or absence of various features on different mask layers for masks used to produce the integrated circuit.
  • the data may be stored in any form of a machine readable medium.
  • a memory or a magnetic or optical storage such as a disc may be the machine readable medium to store information transmitted via optical or electrical wave modulated or otherwise generated to transmit such information.
  • an electrical carrier wave indicating or carrying the code or design is transmitted, to the extent that copying, buffering, or re-transmission of the electrical signal is performed, a new copy is made.
  • a communication provider or a network provider may store on a tangible, machine-readable medium, at least temporarily, an article, such as information encoded into a carrier wave, embodying techniques of embodiments of the present invention.
  • a module as used herein refers to any combination of hardware, software, and/or firmware.
  • a module includes hardware, such as a micro-controller, associated with a non-transitory medium to store code adapted to be executed by the micro-controller. Therefore, reference to a module, in one embodiment, refers to the hardware, which is specifically configured to recognize and/or execute the code to be held on a non-transitory medium.
  • use of a module refers to the non-transitory medium including the code, which is specifically adapted to be executed by the microcontroller to perform predetermined operations.
  • the term module in this example may refer to the combination of the microcontroller and the non-transitory medium.
  • a first and a second module may share hardware, software, firmware, or a combination thereof, while potentially retaining some independent hardware, software, or firmware.
  • use of the term logic includes hardware, such as transistors, registers, or other hardware, such as programmable logic devices.
  • phrase ‘to’ or ‘configured to,’ refers to arranging, putting together, manufacturing, offering to sell, importing and/or designing an apparatus, hardware, logic, or element to perform a designated or determined task.
  • an apparatus or element thereof that is not operating is still ‘configured to’ perform a designated task if it is designed, coupled, and/or interconnected to perform said designated task.
  • a logic gate may provide a 0 or a 1 during operation.
  • a logic gate ‘configured to’ provide an enable signal to a clock does not include every potential logic gate that may provide a 1 or 0. Instead, the logic gate is one coupled in some manner that during operation the 1 or 0 output is to enable the clock.
  • use of the phrases ‘capable of/to,’ and or ‘operable to,’ in one embodiment refers to some apparatus, logic, hardware, and/or element designed in such a way to enable use of the apparatus, logic, hardware, and/or element in a specified manner.
  • use of to, capable to, or operable to, in one embodiment refers to the latent state of an apparatus, logic, hardware, and/or element, where the apparatus, logic, hardware, and/or element is not operating but is designed in such a manner to enable use of an apparatus in a specified manner.
  • a value includes any known representation of a number, a state, a logical state, or a binary logical state. Often, the use of logic levels, logic values, or logical values is also referred to as 1's and 0's, which simply represents binary logic states. For example, a 1 refers to a high logic level and 0 refers to a low logic level.
  • a storage cell such as a transistor or flash cell, may be capable of holding a single logical value or multiple logical values.
  • the decimal number ten may also be represented as a binary value of 1010 and a hexadecimal letter A. Therefore, a value includes any representation of information capable of being held in a computer system.
  • states may be represented by values or portions of values.
  • a first value such as a logical one
  • a second value such as a logical zero
  • reset and set in one embodiment, refer to a default and an updated value or state, respectively.
  • a default value potentially includes a high logical value, i.e. reset
  • an updated value potentially includes a low logical value, i.e. set.
  • any combination of values may be utilized to represent any number of states.
  • a non-transitory machine-accessible/readable medium includes any mechanism that provides (i.e., stores and/or transmits) information in a form readable by a machine, such as a computer or electronic system.
  • a non-transitory machine-accessible medium includes random-access memory (RAM), such as static RAM (SRAM) or dynamic RAM (DRAM); ROM; magnetic or optical storage medium; flash memory devices; electrical storage devices; optical storage devices; acoustical storage devices; other form of storage devices for holding information received from transitory (propagated) signals (e.g., carrier waves, infrared signals, digital signals); etc, which are to be distinguished from the non-transitory mediums that may receive information there from.
  • RAM random-access memory
  • SRAM static RAM
  • DRAM dynamic RAM
  • ROM magnetic or optical storage medium
  • flash memory devices electrical storage devices
  • optical storage devices e.g., optical storage devices
  • acoustical storage devices other form of storage devices for holding information received from transitory (propagated) signals (e.g., carrier waves, infrared signals, digital signals); etc, which are to be distinguished from the non-transitory mediums that may receive information there from.
  • a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), but is not limited to, floppy diskettes, optical disks, Compact Disc, Read-Only Memory (CD-ROMs), and magneto-optical disks, Read-Only Memory (ROMs), Random Access Memory (RAM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), magnetic or optical cards, flash memory, or a tangible, machine-readable storage used in the transmission of information over the Internet via electrical, optical, acoustical or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.). Accordingly, the computer-

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160299869A1 (en) * 2013-12-26 2016-10-13 Intel Corporation Transition-minimized low speed data transfer
US20170293708A1 (en) * 2016-04-08 2017-10-12 Synopsys, Inc. Incrementally Distributing Logical Wires Onto Physical Sockets By Reducing Critical Path Delay
CN114330191A (zh) * 2022-03-08 2022-04-12 上海国微思尔芯技术股份有限公司 一种信号复用传输的方法及装置
US20230306169A1 (en) * 2020-08-20 2023-09-28 Siemens Industry Software Inc. Hybrid Switching Architecture For SerDes Communication Channels In Reconfigurable Hardware Modeling Circuits
US12481814B1 (en) * 2021-11-16 2025-11-25 Synopsys, Inc. Performing automatic sign-off for clock gating verification using toggle cover properties

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3772681A (en) * 1970-10-14 1973-11-13 Post Office Frequency synthesiser
US5446766A (en) * 1991-08-15 1995-08-29 Motorola Digital communication systems
US6150863A (en) * 1998-04-01 2000-11-21 Xilinx, Inc. User-controlled delay circuit for a programmable logic device
US6584535B1 (en) * 2000-01-31 2003-06-24 Cisco Technology, Inc. Configurable serial interconnection
US6735709B1 (en) * 2000-11-09 2004-05-11 Micron Technology, Inc. Method of timing calibration using slower data rate pattern
US6747485B1 (en) * 2000-06-28 2004-06-08 Sun Microsystems, Inc. Sense amplifier type input receiver with improved clk to Q
US20040122888A1 (en) * 2002-12-18 2004-06-24 Carmichael Ronnie Jerome Massively parallel computer network-utilizing multipoint parallel server (MPAS)
US20050213635A1 (en) * 2004-01-30 2005-09-29 Semiconductor Technology Academic Research Center Ultra-wideband receiver
US20070042721A1 (en) * 2005-08-17 2007-02-22 Teranetics, Inc Receiver ADC clock delay based on echo signals
US7397792B1 (en) * 2003-10-09 2008-07-08 Nortel Networks Limited Virtual burst-switching networks
US20110284727A1 (en) * 2010-05-20 2011-11-24 Panasonic Corporation Ccd charge transfer drive device
US8995912B2 (en) * 2012-12-03 2015-03-31 Broadcom Corporation Transmission line for an integrated circuit package

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5851461B2 (ja) * 1978-08-31 1983-11-16 富士通株式会社 時分割多重制御方式
JPS5570148A (en) * 1978-11-21 1980-05-27 Toshiba Corp Remote supervisory and controlling equipment
JPS57116455A (en) * 1981-01-09 1982-07-20 Mitsubishi Electric Corp Information transmitter
JPS63157537A (ja) * 1986-12-22 1988-06-30 Nec Corp 時分割多重送信方法およびその装置
JPS63157538A (ja) * 1986-12-22 1988-06-30 Nec Corp 時分割多重信号の受信方法およびその装置
JPH04291839A (ja) * 1991-03-20 1992-10-15 Fujitsu Ltd 時分割多重化信号の微分回路
JP2959448B2 (ja) * 1995-10-13 1999-10-06 日本電気株式会社 時分割多重ハイウェイのａｔｍインタフェース装置
EP1050824A3 (fr) * 1999-04-22 2004-01-28 Matsushita Electric Industrial Co., Ltd. Circuit de transmission bidirectionelle de signal et système de bus
KR100582577B1 (ko) * 2004-08-19 2006-05-23 삼성전자주식회사 Ｔｄｍ 인터페이스를 위한 클럭 보정 장치 및 방법
WO2006077621A1 (fr) * 2005-01-18 2006-07-27 Mitsubishi Denki Kabushiki Kaisha Appareil de multiplexage et appareil de réception
WO2010089974A1 (fr) * 2009-02-09 2010-08-12 日本電気株式会社 Système de transmission de signal et procédé de transmission de signal
US20110099407A1 (en) * 2009-10-28 2011-04-28 Ati Technologies Ulc Apparatus for High Speed Data Multiplexing in a Processor

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3772681A (en) * 1970-10-14 1973-11-13 Post Office Frequency synthesiser
US5446766A (en) * 1991-08-15 1995-08-29 Motorola Digital communication systems
US6150863A (en) * 1998-04-01 2000-11-21 Xilinx, Inc. User-controlled delay circuit for a programmable logic device
US6584535B1 (en) * 2000-01-31 2003-06-24 Cisco Technology, Inc. Configurable serial interconnection
US6747485B1 (en) * 2000-06-28 2004-06-08 Sun Microsystems, Inc. Sense amplifier type input receiver with improved clk to Q
US6735709B1 (en) * 2000-11-09 2004-05-11 Micron Technology, Inc. Method of timing calibration using slower data rate pattern
US20040122888A1 (en) * 2002-12-18 2004-06-24 Carmichael Ronnie Jerome Massively parallel computer network-utilizing multipoint parallel server (MPAS)
US7397792B1 (en) * 2003-10-09 2008-07-08 Nortel Networks Limited Virtual burst-switching networks
US20050213635A1 (en) * 2004-01-30 2005-09-29 Semiconductor Technology Academic Research Center Ultra-wideband receiver
US20070042721A1 (en) * 2005-08-17 2007-02-22 Teranetics, Inc Receiver ADC clock delay based on echo signals
US20110284727A1 (en) * 2010-05-20 2011-11-24 Panasonic Corporation Ccd charge transfer drive device
US8995912B2 (en) * 2012-12-03 2015-03-31 Broadcom Corporation Transmission line for an integrated circuit package

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160299869A1 (en) * 2013-12-26 2016-10-13 Intel Corporation Transition-minimized low speed data transfer
US10437769B2 (en) * 2013-12-26 2019-10-08 Intel Corporation Transition-minimized low speed data transfer
US20170293708A1 (en) * 2016-04-08 2017-10-12 Synopsys, Inc. Incrementally Distributing Logical Wires Onto Physical Sockets By Reducing Critical Path Delay
US10628625B2 (en) * 2016-04-08 2020-04-21 Synopsys, Inc. Incrementally distributing logical wires onto physical sockets by reducing critical path delay
US20230306169A1 (en) * 2020-08-20 2023-09-28 Siemens Industry Software Inc. Hybrid Switching Architecture For SerDes Communication Channels In Reconfigurable Hardware Modeling Circuits
US12481814B1 (en) * 2021-11-16 2025-11-25 Synopsys, Inc. Performing automatic sign-off for clock gating verification using toggle cover properties
CN114330191A (zh) * 2022-03-08 2022-04-12 上海国微思尔芯技术股份有限公司 一种信号复用传输的方法及装置

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JP2017505031A (ja) 2017-02-09
JP6277279B2 (ja) 2018-02-07
CN105794113B (zh) 2019-06-25
WO2015099799A1 (fr) 2015-07-02
EP3087676A4 (fr) 2018-01-24

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