US20160254696A1

US20160254696A1 - Wireless power transfer in-band communication system

Info

Publication number: US20160254696A1
Application number: US15/147,919
Authority: US
Inventors: William Plumb; Zhen Wang; Zoran Zvonar; Patrick Stanley Riehl; Anand Satyamoorthy; Philip Frank Tustin
Original assignee: MediaTek Singapore Pte Ltd
Current assignee: MediaTek Singapore Pte Ltd
Priority date: 2012-10-26
Filing date: 2016-05-06
Publication date: 2016-09-01
Also published as: US20140314170A1; CN107404159A; WO2014066707A2; US9363041B2; CN104904087B; EP2912748A4; EP2912748A2; CN104904087A; EP2912748B1; WO2014066707A3

Abstract

A transmitter module is used in a wireless charging system, and is used for performing in-band communication with a receiver module in the wireless charging system to provide a message to the receiver module. The transmitter module has a matching network, a rectifier and an impedance component. The matching network has at least one input terminal coupled to a coil of the transmitter module and at least one output terminal. The rectifier is coupled to the output terminal of the matching network. The impedance component is selectively coupled to the output terminal of the matching network to vary a reflected impedance of the transmitter module seen by the receiver module. By varying the reflected impedance of the transmitter module seen by the receiver module, the transmitter module communicates with the receiver module to provide power control commands, status and/or foreign object detection information.

Description

CROSS REFERENCE TO RELATED APPLICATION

This is a continuation of U.S. application Ser. No. 14/356,607 filed May 7, 2014, which is a National Stage Entry of PCT/US2013/066721 filed Oct. 25, 2013 and claiming priority from U.S. provisional application No. 61/718,943 filed Oct. 26, 2012. All of the related applications are incorporated herein by reference in their entirety.

BACKGROUND OF THE INVENTION

The invention is related to the field of wireless power transfer systems, and in particular a wireless power transfer in-band communication system that provides robust communications channel to be embedded in the case where energy is transferred from a Source to a Load without a physical connection.
Current wireless power transfer (also referred to as wireless charging) on the market (Qi) employs communication system based on a classic asynchronous serial communication interface with a start/stop bit or indication and little or no protection on the data transmitted. This serial communication is specified by the Wireless Power Consortium (WPC).

SUMMARY OF THE INVENTION

According to one aspect of the invention, there is provided a transmitter module. The transmitter module is used in a wireless charging system, and is used for performing in-band communication with a receiver module in the wireless charging system to provide a message to the receiver module. The transmitter module has a matching network, a rectifier and an impedance component. The matching network has at least one input terminal coupled to a coil of the transmitter module and at least one output terminal. The rectifier is coupled to the output terminal of the matching network. The impedance component is selectively coupled to the output terminal of the matching network to vary a reflected impedance of the transmitter module seen by the receiver module. By varying the reflected impedance of the transmitter module seen by the receiver module, the transmitter module communicates with the receiver module to provide power control commands, status and/or foreign object detection information.
According to another aspect of the invention, there is provided a receiver module. The receiver module is used in a wireless charging system, and is used for performing in-band communication with a transmitter module in the wireless charging system to receive a message from the transmitter module. The receiver module includes a matching network, an amplifier and an impedance sensing circuit. The matching network has at least one input terminal coupled to a coil of the receiver module and at least one output terminal. The amplifier is coupled to the output terminal of the matching network. The impedance sensing circuit is coupled to the amplifier, and is used for detecting changes in a reflected impedance of the transmitter module seen by the receiver module. By detecting changes in the reflected impedance of the transmitter module seen by the receiver module, the receiver module communicate with the transmitter module to receive power control commands, status and/or foreign object detection information.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram illustrating the charger system;

FIG. 2 is a schematic diagram illustrating the impedance variation for load to source communications;

FIG. 3 is a schematic diagram illustrating a wireless power system with load modulation used in accordance with the invention

FIG. 4 is a schematic diagram illustrating a charger and device orientation of current available wireless charging topologies;

FIG. 5 is a schematic block diagram of the TX communication path used in accordance with the invention;

FIG. 6 is a schematic diagram illustrating the preamble/message sequence used in accordance with the invention;

FIG. 7 is a schematic diagram illustrating the transmitter message encoding used in accordance with the invention

FIG. 8 is a graph illustrating the BER versus SNR for modulation coding methods;

FIG. 9 is a schematic diagram illustrating the RX communication path used in accordance with the invention;

FIG. 10 is a schematic diagram illustrating load impedance sense circuit used in accordance with the invention;

FIG. 11 is a schematic diagram illustrating an example of a cascade of filter sections;

FIG. 12 is a schematic diagram illustrating DC removal block used in accordance with the invention;

FIG. 13 is a graph illustrating the BER versus SNR for biphase signal before and after pulse shaping filtering with no channel coding;

FIG. 14 is a graph illustrating the impulse response of the floating point pulse shaping filter;

FIG. 15 is a schematic diagram illustrating the preamble correlator operation used in accordance with the invention;

FIG. 16 is a schematic diagram illustrating the preamble peak detector used in accordance with the invention;

FIG. 17 is a flow chart illustrating exemplary peak detection algorithm used in accordance with the invention;

FIG. 18 is a graph illustrating the autocorrelation of Barker and biphase encoded Barker sequence;

FIG. 19 is to able illustrating a 13 bit Barker code and its inverted version;

FIG. 20 is a table illustrating the Barker code preamble performance with AWGN channel;

FIG. 21 is a graph illustrating the autocorrelation of Hadamard sequence;

FIG. 22 is a table illustrating the Hadamard code preamble performance with AWGN channel;

FIG. 23 is a table illustrating the 2×8 bit Golay complementary sequence;

FIG. 24 is a graph illustrating the autocorrelation of Golay complementary sequence;

FIGS. 25A-25B are graphs illustrating the output waveforms after pulse shaping filtering including DC offset removal;

FIG. 26 is a graph illustrating the captured Golay complementary sequence after pulse shaping filtering including DC offset removal;

FIG. 27 is schematic diagram illustrating the preamble detector correlator;

FIG. 28 is a graph illustrating a biphase encoded signal;

FIG. 29 is a table illustrating the maximum likelihood biphase demodulation;

FIG. 30 is the maximum likelihood biphase demodulation pseudo code;

FIG. 31 is a table illustrating the steps for biphase decoding with error correction and DC offset compensation;

FIG. 32 is a graph illustrating an example of biphase decoding with error correction;

FIGS. 33A-33B are graphs illustrating the performance of the single device BER before and after channel decoding;

FIGS. 34A-34B are graphs illustrating the; and the performance of the dual device BER before and after channel decoding; and

FIGS. 35A-35B are graphs illustrating the performance of the three devices BER before and after channel decoding.

DETAILED DESCRIPTION OF THE INVENTION

This invention describes the feasibility of using the wireless power transfer medium to send messages from a charging device to the source. Wireless power transfer (also referred to as wireless charging) is when energy is transferred from a Source to a Load without a physical connection. A typical example in this case would be a pad that's sits on a flat surface acting as the Source and a mobile phone placed on or near the pad acting as the Load.
FIG. 1 shows a wireless power transfer system that includes an in-band communication system 2. In-band communication system 2 has the benefit of being a lower cost solution compared to out-of-band solution. In-band communication allows: (1) Foreign object detection; (2) Power matched to load (vs. full TX power); (3) Power allocation per load; (4) Charger status available on phone; and (5) provisioning/billing. Current wireless power transfer (also referred to as wireless charging) on the market (Qi) employs communication system based on a classic serial communication interface with a start/stop bit or indication and little or no protection on the data transmitted. This serial communication is specified by the Wireless Power Consortium (WPC).
The inventive wireless power transfer in-band communication system is different from systems currently on the market or proposed by other companies. In this topology the Load device 4 is required to communicate with the Source to provide power control commands, status and foreign object detection information. It is possible by varying the reflected impedance of the Load 4 seen by the Source to modulate a signal on the transmitted power waveform to facilitate communication between the Load and Source. FIG. 2 shows how the Load impedance 6 can be varied (Point A) to modulate the transmitted signal at the Source 8. The modulation component can be either capacitive or resistive. FIG. 3 shows a block diagram representation of load modulation.
Note that inductive wireless charging setups require that the device (Load) 4 is sitting flush with the charger Source 8, as shown in FIG. 4. For wireless charging to occur the device can only have a limited number of orientations. Both the close proximity and fixed orientation results in very benign wireless charger communication channel conditions—thus allowing a simple communications scheme
The inventive wireless charging system can utilize a larger form factor to allow multiple devices to charge simultaneously. The inventive wireless charging system can have multiple devices with arbitrary orientation. The devices do not need to be in close proximity or have a fixed orientation. The arbitrary offset and position of the device results in very hostile in-band wireless charger communication channel conditions. This makes communication between Load and Source difficult.
The in-band communication system used by the invention must have low complexity and be robust enough to ensure good communication between the Load (Transmitter) and the Source (Receiver). Complexity is an important factor as both the communication transmission and reception must be able to be implemented on relatively simple MCUs and/or low complexity dedicated hardware,
FIG. 5 shows the transmit portion of the in-band communication system includes: (1) Message formatting; (2) CRC calculation and attachment to message, for message error detection—43; (3) Channel encoding—BCH error correction encoder—44; (4) Modulation—biphase modulation for DC balanced signal—45; (5) Prepend message with synchronization sequence—Golay complementary code; (6) A wireless charging receiver coil used to convert energy in an electromagnetic field to electrical energy—7, as show in FIG. 2 and FIG. 3; (7) Active switching of a passive component—either resistive or capacitive—to change the reflected impedance of the Load seen by the Source—as shown in FIG. 2 as point A, and Zmod 42 of FIG. 3.
FIG. 6 shows the preamble 34 followed by the message 36 and FIG. 7 shows how the message is constructed before transmitting. Note that a gap between the preamble and message maybe used to allow timing adjustments done by the synchronization block in the receiver to take effect at the output of the digital front end filter in time for the message to be received.
Table 1 shows some typical values for the message encoding/decoding.

	TABLE 1

	Message coding element	Size/length

M message length	~8-200	bits
CRC
8	bits

	Channel coding rate	BCH (15.7) or Hamming (13.8)
	Modulation coding	Biphase modulation rate = 4 kHz

The CRC is used to determine if the message is received without errors. The CRC shall be attached to each message header—if used—and message body. Note that for a variable length communications system the header must indicate the length of the message and must also have a CRC attached to allow for the determination of correct detection. An eight bit CRC could be used with the following polynomial: poly(D)=D⁸+D⁷+D⁴+D³+D+1.
Two error correcting codes have been considered for the wireless charger application but the invention can use other known coding technologies. The first code is a (15,7) double-error-correcting BCH code and the second code is an enhanced (13,8) Hamming code which can correct single-bit errors as well as adjacent double-bit errors. For both codes, an implementation of the encoder and the straightforward implementation of the decoder based on lookup tables is used.
The following describes a possible encoder implementation of a (15,7) double-error-correcting BCH Code. A codeword can be written as c=(c₁,c₂, . . . ,c₁₅), where c₁, c₂, . . . ,c₇are information bits and c₈, c₉, . . . ,c₁₅are redundant bits. The parity check matrix of the code is
$H = [\begin{matrix} 1 & 1 & 0 & 1 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\ 0 & 1 & 1 & 0 & 1 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 \\ 0 & 0 & 1 & 1 & 0 & 1 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 \\ 0 & 0 & 0 & 1 & 1 & 0 & 1 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 \\ 1 & 1 & 0 & 1 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 \\ 0 & 1 & 1 & 0 & 1 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 \\ 1 & 1 & 1 & 0 & 0 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 \\ 1 & 0 & 1 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 \end{matrix}]$
The generator matrix of the code is
$G = [\begin{matrix} 1 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 1 & 0 & 1 & 1 \\ 0 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 0 & 0 & 1 & 1 & 1 & 0 \\ 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 0 & 0 & 1 & 1 & 1 \\ 0 & 0 & 0 & 1 & 0 & 0 & 0 & 1 & 0 & 1 & 1 & 1 & 0 & 0 & 0 \\ 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 1 & 0 & 1 & 1 & 1 & 0 & 0 \\ 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 1 & 0 & 1 & 1 & 1 & 0 \\ 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 1 & 0 & 1 & 1 & 1 \end{matrix}]$
The code can correct any double-bit errors. To simplify the error correcting algorithm, the error will be corrected only if the information bits of the codes are affected.
Given 7 information bits v, for encoding the 15-bit codeword can be computed by a modulo 2 matrix multiplication c=vG. The formulas for the 8 redundant bits are as follows, where + is the modulo 2 addition.
c ₈ =c ₁ +c ₂ +c ₄
c ₉ =c ₂ +c ₃ +c ₅
c ₁₀ =c ₃ +c ₄ +c ₆
c ₁₁ =c ₄ +c ₅ +c ₇
c ₁₂ =c ₁ +c ₂ +c ₄ +c ₅ +c ₆
c ₁₃ =c ₂ +c ₃ +c ₅ +c ₆ +c ₇
c ₁₄ =c ₁ +c ₂ +c ₃ +c ₆ +c ₇
c ₁₅ =c ₁ +c ₃ +c ₇
The following describes a possible encoder implementation of a (13,8) Enhanced Hamming code. The (13,8) Enhanced Hamming code can correct any single-bit errors and any adjacent double-bit errors. The total number of correctable error patterns is 26. For channel models where almost all of the double-bit errors occur to two adjacent bits, the code can provide nearly as good performance as a double-error-correcting BCH codes.
Given 8 information bits ν, the 13-bit codeword can be computed by a modulo 2 matrix multiplication c=νG. The formulas for the 5 redundant bits are as follows, where + is the modulo 2 addition.
c ₉ =c ₂ +c ₃ +c ₅ +c ₇
c ₁₀ =c ₁ +c ₃ +c ₄ +c ₆
c ₁₁ =c ₁ +c ₂ +c ₅ +c ₈
c ₁₂ =c ₁ +c ₂ +c ₃ +c ₅ +c ₆
c ₁₃ =c ₂ +c ₄ +c ₇ +c ₈
Specific consideration has been given to the modulation format. This is important for multiple reasons: to have suitable format for the medium that is dominated by large DC signals, to have good performance in terms of bit-error-rate (BER) and to have format that can be effectively produced by simple circuit realization.
FIG. 8 shows the BER performance of the different methods compared to the Non-Return Zero (NRZ) case with normalized throughput rates. From FIG. 8, it can be seen that the biphase modulation with error correction has slightly better performance than the DC balanced method. However it should be noted that there are a number of consecutive ones (up to 4) in the DC balanced code which is in violation of the number of consecutive “1”s that can be tolerated by the system.
In-band communication is accomplished by means of modulating the impedance of a Load and sensing a power change on the Source. One can detect this power change on the Source via a sensing circuit and provide this as an input to a micro-controller or low complexity hardware block. During communications, a “0” output from the “Load” has no effect on the “Source” coil's impedance. The impedance modulation may have the effect of decreasing the power available to the Load. In order to maintain a relatively constant rate of power transfer the coding scheme should have a relative consistent portion of “1”s and “0”s.
A transmission protocol such as biphase insures that a “1” state will only occur for one bit time before it will be normalized by a “0”state. This type of conditioning is best for the circuitry to minimize the effect on the “receivers” coil voltage. At worst only three consecutive “1”s should occur at the biphase rate (in the example of the system used to illustrate operation rate is 4 kHz). Due to this issue the DC balanced modulation 8b10b scheme investigated is not suitable for this application. Run length limited (RLL) codes were also investigated however due to the limitation on the number of consecutive ones the RLL codes had comparable performance to that of the biphase encoding. The modulation method recommended is biphase with error correction. FIG. 28 shows an example of a biphase encoded signal. The signal has a change of level at the boundary of every symbol. A binary “1” has a change of level in the middle of every symbol and a “0” maintains its level for the duration of a symbol.
The receiver portion of the in-band communication system includes: (1) Impedance sensing, to detect changes in the reflected impedance of the TD; (2) Front end filter, used for pulse shaping and noise rejection; (3) Preamble detection block—Golay complementary code correlator, used for message detection, synchronization, and equalization coefficient estimation; (4) Demodulation and equalization—biphase demodulation with error correction; (5) Channel decoding—BCH error correction decoder; (6) CRC calculation, check and removal, for message error detection.
FIG. 9 shows a block diagram of the in-band communications receiver 12. The front end includes load impedance sensing module followed by analog anti-aliasing filter and the analog-to-digital converter (ADC). FIG. 10 shows an exemplary embodiment of a Load impedance sense circuit 11 used in accordance circuit. This circuit 11 includes a current sense for load sensing that coupled to an amplifier and resonator amplifier 5, as shown in FIG. 3.
ADC typically operates at the clock rate that is an integer multiple of the data rate supported by in-band communication system. In one of the implementations of the receiver the received signal after ADC is 32x oversampled, with x being the supported data rate, and is down sampled digitally. The sample rate of the signal after downsampling is dependent on the signal processing function being used. For preamble detection the rate of oversampling used can 8x or 4x and for message reception the oversampling rate is 4x. A higher oversample rate used in the preamble detection results inbetter noise and DC offset estimation.
Following ADC is the digital RX front end filter 14 which can be implemented as a cascade of the filter sections 16 to reduce the amount of processing (MIPS) and increase the number of effective bits. The output of the pulse shaping filter is down sampled to the rate required by the preamble and message detection. In the current design the message detection has an input sample rate of 4x rate. The selection of which samples to filter is determined by the synchronization procedure. It should be noted that the pulse shaping filter could be implemented as a cascade of filter sections to reduce the amount of processing (MIPS) required. FIG. 11 shows an example of how the pulse shaping filter 28 could be broken into sections 30.
The received signal is a combination of wanted biphase modulated signal and unwanted DC offset. The DC offset can be removed within one of the following modules
Analog front-end

- pulse shaping filter or
- within synchronization and demodulation modules,
  or at several modules concurrently. It can be done as a separate DC offset removal block 24 shown in FIG. 12. Whether to use a separate DC offset removal or not is a design trade off. For example a course DC offset removal could be done by the analog front end and a fine DC offset done as part of the preamble detector (synchronization) and demodulation block. FIG. 9 shows a block diagram of the front end filters 16 where the DC offset removal is done as part of the preamble detector 18 and the demodulation block 20 using DC block removal block 24, FIG. 12.

The following pulse shaping filter was designed to remove the DC offset and attenuate the signal past the first main lobe of the biphase signal. FIG. 13 shows an example of the improvement in the performance when using the pulse shaping filter. FIG. 13 also shows there is a noise floor due to the distortion of the signal within the inband region. FIG. 14 shows the impulse response of the pulse shaping filter.
The preamble detector 18 (or syncronization) block contains: (1) Correlator with DC offset; (2) Peak detector; and (3) Timing estimation. The correlator can be done as either a sliding correlator or using the Enhanced Golay Correlator (EGC).
FIG. 15 shows a block diagram of the preamble correlator operating on the input data sequence. Every sample the correlator outputs a result and loads it into a circulator buffer 46 or a noise estimator circular buffer 48. FIG. 16 shows a diagram with the correlator 46 and noise circular buffer 48 in a linear topology. Note that the noise estimation is a moving average filter which should be set to at least the length of the correlator sequence m. Using a power of two will simplify the code implementation and negate the use of a divide operation. The samples used for the noise estimation [N₀ ². . . N_n−1 ²] should be taken before the sub window used for initial peak detection. FIG. 17 shows the flow chart of one possible implementation used to perform the peak detection.
In order for the Source (Receiver) to determine if the Load (Transmitter) is transmitting a message there needs to be an initial preamble for the Source to do the following: (1) Recognize there is going to be a message transmitted from the Load to the Source; (2) Synchronization of the symbol timing between the Load and the Source by setting which samples are feed into the pulse shaping filter; and (3) Calculation of equalizer coefficients and hence dispersiveness of the channel.
The Load system will have its frequency locked to the Source 6.78 MHz oscillator so the preamble synchronization sequence is only meant for the Source to determine the symbol timing.
FIG. 6 shows an example of a preamble/message sequence. Each message 36 should be accompanied with a preamble sequence 34. The preamble sequence 34 should have the following characteristics: (1) Short length; and (2) Good auto correlation characteristics.
The following codes were investigated: (1) Barker sequence; (2) Complementary Hadamard sequence, (3) length 32; M-sequence length, 32; (4) Complementary Golay sequence, length 16. Note other codes can also be used in accordance with the invention.
Of these synchronization codes investigated the Complementary Golay sequence had good characteristics and also the option of implementing the correlator using the Enhanced Golay Correlator (EGC) or a variant of this method. The EGC and variants are an efficient implementation of a circular correlator and can efficiently support DC offset estimation and removal. The synchronization can be done either using a sliding window time correlator or a circular correlator performed each sample.
It is important to be able to detect the preamble at SNR values that are lower than that expected for a reliable message decoding. From the current requirements with a modulation depth of 0.1 the lowest SNR value encountered is ˜0 dB. It is expected that the preamble detection and synchronization can work at <0 dB SNR value.
Biphase encoding a signal with good autocorrelation characteristics will make the autocorrelation characteristics poorer. FIG. 18 shows the characteristics of the 13 bit Barker sequence with and without biphase encoding. As can be seen from FIG. 18, it would be desirable to avoid using biphase encoding for the preamble sequence. FIG. 19 shows the 13 bit Barker code and its inverted version. Having the requirement that the number of consecutive “1”s per half bit is less than or equal to three then the inverted version of the Barker's code can be used directly without additional biphase encoding. Note that this means the Barker code will operate at 4 kHz which is twice the bit rate of the message (2 kHz). FIG. 20 shows the performance of the Barker code for Preamble detection.
The performance of the Barker code shown meets requirements for the AWGN case. The autocorrelation properties of several M-sequences and complementary Hadamard sequences of length 32 were also investigated and it was found that the Hadamard sequences had good auto correlation properties. The auto correlation of the Hadamard sequence is shown in FIG. 21. Even though the ratio of the peak to side lobe of the Hadamard autocorrelation is less than the Barker code the additional length of the Hadamard allows more averaging.
FIG. 22 shows the performance of the Hadamard sequence. The performance of the Hadamard sequence meets the requirements of the preamble detection.
Golay complementary sequences have good autocorrelation characteristics. FIG. 23 shows a 2×8 Golay complementary sequence. FIG. 24 shows the auto-correlation of the Golay complementary sequence.
FIG. 25A shows the Golay complementary sequence and a random biphase signal after pulse shaping filtering with DC offset removal. A can be seen in FIG. 25B, part of the wanted signal of the preamble is removed by the pulse shaping filter with DC offset removal. The synchronization procedure is robust but in conditions where the modulation depth of the signal is low then this method of DC offset removal may not be acceptable. FIG. 26 shows two preamble signals captured in the laboratory. Both preamble signals are distorted which reduces the probability of detection. For this reason it was decided to use the moving average DC offset removal.
To minimize the amount of processing required by the preamble detector the correlator 40 has been implemented as an Optimized Golay Correlator (OGC) with the noise estimation and DC offset estimation and removal built into the correlator block 40, as shown in FIG. 27. As shown in FIG. 27, the correlator block as the following relationships:
$\begin{matrix} a_{0}^{'} [k] - a [k] & Eq . 11 \\ b_{0}^{'} [k] - b [k] & Eq . 12 \\ a_{n}^{'} [k] = a_{n - 1}^{'} [k - D_{N - n - 1}] + b_{n - 1}^{'} [k - D_{N - n - 1}] & Eq . 13 \\ a_{n}^{'} [k] = W_{N - n - 1} (a_{n - 1}^{'} [k - D_{N - n - 1}] - b_{n - 1}^{'} [k - D_{N - n - 1}]) & Eq . 14 \\ a_{N}^{'} [k] + b_{N}^{'} [k] & Eq . 15 \\ Y [k] = a_{N}^{'} [k] + b_{N}^{'} [k] & Eq . 16 \\ MS Noise = \frac{1}{L} \sum_{l = 0}^{L - 1} {Y [l]}^{2} & Eq . 17 \end{matrix}$
where N=3, n=0,1,2, k=0, . . . , 7, L=7, a[k] and b[k] are the received signals, a′_i[k] and b′_i[k] are partial results, Y [k] is the correlation between the input signal and the Golay sequence, Y[7] is the correlator output, MS Noise is the mean square of the noise for the current correlator output.
The DC offset is calculated using the equation below:
$\begin{matrix} DC offset = \frac{1}{N} \sum_{n = 0}^{N - 1} S_{n} & Eq . 18 \end{matrix}$
where N is the number of samples in the preamble sequence.
After a peak is detected the timing alignment needs to be determined so that this can be feedback to the pulse shaping filter to adjust the input samples to give the best timing alignment. The timing alignment of the received signal can be obtained by using an interpolation filter on the down sampled correlation data used for the preamble detection. Due to the interpolation the data must be padded with zeros. Only five correlation values are required around the correlation peak (zn).
Z _m=(z _n−2,0,0,0,z _n−1,0,0,0,z _n,0,0,0,z _n+1,0,0,0,z _n+2,0,0,0).
The output of the interpolator and the data gives:
B(k)=b ₀ +b ₁ + . . . +b _k, where k=m+n−1
The location of the peak detected in the previous operation in the interpolated data set is at b₁₅. A search can be done around sample b₁₅of +/−3 samples to determine if there is a greater value.
To simplify the interpolation procedure the interpolation filter's tapped delay line can be pre-loaded and only seven operations of the interpolation filter is required. A more efficient implementation would be to avoid a filter structure and use seven dedicated operations. Table 2 shows simplified interpolation filtering and Table 3 shows the dedicated sub-operations for interpolations filtering.

TABLE 2

Interpolations
Coefficients	Tapped delay lines

−2	0		Z _n−2	0	0	0	Z_n−1
−3	0	Z _n−2	0	0	0	Z _n−1	0
−2	Z _n−2	0	0	0	Z _n−1	0	0
0	0	0	0	Z _n−1	0	0	0
9	0	0	Z _n−1	0	0	0	Z _n
18	0	Z _n−1	0	0	0	Z _n	0
26	Z _n−1	0	0	0	Z _n	0	0
31	0	0	0	Z _n	0	0	0
26	0	0	Z _n	0	0	0	Z _n+1
18	0	Z _n	0	0	0	Z _n+1	0
9	Z _n	0	0	0	Z _n+1	0	0
0	0	0	0	Z _n+1	0	0	0
−2	0	0	Z _n+1	0	0	0	Z_n+2
−3	0	Z _n+1	0	0	0	Z _n+2	0
−2	Z _n+1	0	0	0	Z _n+2	0	0
Filter output	b12	b13	b14	b15	b16	b17	b18

	TABLE 3

	Filter output	Operation

	b12	−2[(Zn − 2) + (Zn + 1)] + 26(Zn − 1) + 9*(Zn)
	b13	−3[(Zn − 2) + (Zn + 1)] + 18[(Zn − 1) + (Zn)]
	b14	−2[(Zn − 2) + (Zn + 1)] + 9(Zn − 1) + 26*(Zn)
	b15	31*(Zn)
	b16	−2[(Zn − 1) + (Zn + 2)] + 26(Zn) + 9*(Zn + 1)
	b17	−3[(Zn − 1) + (Zn + 2)] + 18[(Zn) + (Zn + 1)]
	b18	−2[(Zn − 1) + (Zn + 2)] + 9(Zn) + 26*(Zn + 1)

Following the synchronization the receiver performs demodulation by providing the functions of (optional) equalization, modulation decoding, channel decoding of the message and CRC check.
One of the items considered for the use in demodulation part of the receiver is equalizer. Experiments have determined that for the channel with time dispersion using the equalizer can be beneficial and it can be signaled by the flag from synchronization module.
The biphase with error correction method makes use of the soft bits, the characterisitics of biphase encoding and maximum likelihood (ML) correction. Looking at FIG. 28 it can be seen that a biphase encoded signal must change sign at the start of every bit. If the received signal does not change sign at the start of every bit then a comparison of the magnitude of the previous end of bit and the start of the current bit can be used to determine which bit's—end or start—sign is changed. FIG. 29 shows the ML biphase demodulation truth table and FIG. 30 shows pseudo code for ML biphase demodulation.
FIG. 31 shows the steps for biphase decoding with error correction. FIG. 32 shows an example of biphase decoding with error correction.
The invention produces BER results using a system configuration with the following: (1) Biphase modulation; (2) pulse shaping filter at the receiver; and (3) Channel coding BCH.
The following describes a possible decoder implementation of a (15,7) double-error-correcting BCH Code. After receiving a possibly distorted codeword {tilde over (c)}, compute the syndrome of the BCH code by a modulo 2 matrix multiplication s=H{tilde over (c)}, where s is an 8-bit binary vector. No error is detected if s=0. If s≠0, the syndrome and its corresponding error vector is shown in Table 3. If a nonzero s is not in Table 3, then the information bits of the codeword is not affected by the error. Table 3 shows the error pattern for different syndromes s for the regular (15,7) BCH Code

TABLE 3

s (Decimal Value of an 8-Bit Binary Vector)	Error Pattern

209	1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
115	0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
230	0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
29	0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
58	0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
116	0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
232	0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
1	0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
2	0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
4	0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
8	0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
16	0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
32	0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
64	0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
128	0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
208	1 0 0 0 0 0 0 1 0 0 0 0 0 0 0
211	1 0 0 0 0 0 0 0 1 0 0 0 0 0 0
213	1 0 0 0 0 0 0 0 0 1 0 0 0 0 0
217	1 0 0 0 0 0 0 0 0 0 1 0 0 0 0
193	1 0 0 0 0 0 0 0 0 0 0 1 0 0 0
241	1 0 0 0 0 0 0 0 0 0 0 0 1 0 0
145	1 0 0 0 0 0 0 0 0 0 0 0 0 1 0
81	1 0 0 0 0 0 0 0 0 0 0 0 0 0 1
114	0 1 0 0 0 0 0 1 0 0 0 0 0 0 0
113	0 1 0 0 0 0 0 0 1 0 0 0 0 0 0
119	0 1 0 0 0 0 0 0 0 1 0 0 0 0 0
123	0 1 0 0 0 0 0 0 0 0 1 0 0 0 0
99	0 1 0 0 0 0 0 0 0 0 0 1 0 0 0
83	0 1 0 0 0 0 0 0 0 0 0 0 1 0 0
51	0 1 0 0 0 0 0 0 0 0 0 0 0 1 0
243	0 1 0 0 0 0 0 0 0 0 0 0 0 0 1
231	0 0 1 0 0 0 0 1 0 0 0 0 0 0 0
228	0 0 1 0 0 0 0 0 1 0 0 0 0 0 0
226	0 0 1 0 0 0 0 0 0 1 0 0 0 0 0
238	0 0 1 0 0 0 0 0 0 0 1 0 0 0 0
246	0 0 1 0 0 0 0 0 0 0 0 1 0 0 0
198	0 0 1 0 0 0 0 0 0 0 0 0 1 0 0
166	0 0 1 0 0 0 0 0 0 0 0 0 0 1 0
102	0 0 1 0 0 0 0 0 0 0 0 0 0 0 1
28	0 0 0 1 0 0 0 1 0 0 0 0 0 0 0
31	0 0 0 1 0 0 0 0 1 0 0 0 0 0 0
25	0 0 0 1 0 0 0 0 0 1 0 0 0 0 0
21	0 0 0 1 0 0 0 0 0 0 1 0 0 0 0
13	0 0 0 1 0 0 0 0 0 0 0 1 0 0 0
61	0 0 0 1 0 0 0 0 0 0 0 0 1 0 0
93	0 0 0 1 0 0 0 0 0 0 0 0 0 1 0
157	0 0 0 1 0 0 0 0 0 0 0 0 0 0 1
59	0 0 0 0 1 0 0 1 0 0 0 0 0 0 0
56	0 0 0 0 1 0 0 0 1 0 0 0 0 0 0
62	0 0 0 0 1 0 0 0 0 1 0 0 0 0 0
50	0 0 0 0 1 0 0 0 0 0 1 0 0 0 0
42	0 0 0 0 1 0 0 0 0 0 0 1 0 0 0
26	0 0 0 0 1 0 0 0 0 0 0 0 1 0 0
122	0 0 0 0 1 0 0 0 0 0 0 0 0 1 0
186	0 0 0 0 1 0 0 0 0 0 0 0 0 0 1
117	0 0 0 0 0 1 0 1 0 0 0 0 0 0 0
118	0 0 0 0 0 1 0 0 1 0 0 0 0 0 0
112	0 0 0 0 0 1 0 0 0 1 0 0 0 0 0
124	0 0 0 0 0 1 0 0 0 0 1 0 0 0 0
100	0 0 0 0 0 1 0 0 0 0 0 1 0 0 0
84	0 0 0 0 0 1 0 0 0 0 0 0 1 0 0
52	0 0 0 0 0 1 0 0 0 0 0 0 0 1 0
244	0 0 0 0 0 1 0 0 0 0 0 0 0 0 1
233	0 0 0 0 0 0 1 1 0 0 0 0 0 0 0
234	0 0 0 0 0 0 1 0 1 0 0 0 0 0 0
236	0 0 0 0 0 0 1 0 0 1 0 0 0 0 0
224	0 0 0 0 0 0 1 0 0 0 1 0 0 0 0
248	0 0 0 0 0 0 1 0 0 0 0 1 0 0 0
200	0 0 0 0 0 0 1 0 0 0 0 0 1 0 0
168	0 0 0 0 0 0 1 0 0 0 0 0 0 1 0
104	0 0 0 0 0 0 1 0 0 0 0 0 0 0 1
162	1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
55	1 0 1 0 0 0 0 0 0 0 0 0 0 0 0
149	0 1 1 0 0 0 0 0 0 0 0 0 0 0 0
204	1 0 0 1 0 0 0 0 0 0 0 0 0 0 0
110	0 1 0 1 0 0 0 0 0 0 0 0 0 0 0
251	0 0 1 1 0 0 0 0 0 0 0 0 0 0 0
235	1 0 0 0 1 0 0 0 0 0 0 0 0 0 0
73	0 1 0 0 1 0 0 0 0 0 0 0 0 0 0
220	0 0 1 0 1 0 0 0 0 0 0 0 0 0 0
39	0 0 0 1 1 0 0 0 0 0 0 0 0 0 0
165	1 0 0 0 0 1 0 0 0 0 0 0 0 0 0
7	0 1 0 0 0 1 0 0 0 0 0 0 0 0 0
146	0 0 1 0 0 1 0 0 0 0 0 0 0 0 0
105	0 0 0 1 0 1 0 0 0 0 0 0 0 0 0
78	0 0 0 0 1 1 0 0 0 0 0 0 0 0 0
57	1 0 0 0 0 0 1 0 0 0 0 0 0 0 0
155	0 1 0 0 0 0 1 0 0 0 0 0 0 0 0
14	0 0 1 0 0 0 1 0 0 0 0 0 0 0 0
245	0 0 0 1 0 0 1 0 0 0 0 0 0 0 0
210	0 0 0 0 1 0 1 0 0 0 0 0 0 0 0
156	0 0 0 0 0 1 1 0 0 0 0 0 0 0 0

*Syndrome values not in the table correspond to a zero error vector.

The following describes a possible decoder implementation of a (13,8) enhanced Hamming code. After receiving a possibly distorted codeword {tilde over (c)}, compute the syndrome of the enchanced Hamming code by a modulo 2 matrix multiplication s=H{tilde over (c)}, where s is a 5-bit binary vector. Use s as the index to perform a (32×13) table lookup operation. The table of error patterns is described in Table 4. Table 4 shows the error pattern for different syndromes s for the (13,8) enhanced Hamming code

TABLE 4

s (Decimal Value of an 5-Bit Binary Vector)	Error Pattern e

0	0 0 0 0 0 0 0 0 0 0 0 0 0
1	0 0 0 0 0 0 0 0 1 0 0 0 0
2	0 0 0 0 0 0 0 0 0 1 0 0 0
3	0 0 0 0 0 0 0 0 1 1 0 0 0
4	0 0 0 0 0 0 0 0 0 0 1 0 0
5	0 0 0 0 0 0 1 1 0 0 0 0 0
6	0 0 0 0 0 0 0 0 0 1 1 0 0
7	0 0 0 0 1 1 0 0 0 0 0 0 0
8	0 0 0 0 0 0 0 0 0 0 0 1 0
9	0 0 0 0 0 0 0 0 0 0 0 0 0
10	0 0 0 0 0 1 0 0 0 0 0 0 0
11	0 0 1 0 0 0 0 0 0 0 0 0 0
12	0 0 0 0 0 0 0 0 0 0 1 1 0
13	0 0 0 0 1 0 0 0 0 0 0 0 0
14	1 0 0 0 0 0 0 0 0 0 0 0 0
15	0 0 0 0 0 0 0 0 0 0 0 0 0
16	0 0 0 0 0 0 0 0 0 0 0 0 1
17	0 0 0 0 0 0 1 0 0 0 0 0 0
18	0 0 0 1 0 0 0 0 0 0 0 0 0
19	1 1 0 0 0 0 0 0 0 0 0 0 0
20	0 0 0 0 0 0 0 1 0 0 0 0 0
21	0 0 0 0 0 0 0 1 1 0 0 0 0
22	0 1 1 0 0 0 0 0 0 0 0 0 0
23	0 0 0 0 0 0 0 0 0 0 0 0 0
24	0 0 0 0 0 0 0 0 0 0 0 1 1
25	0 0 1 1 0 0 0 0 0 0 0 0 0
26	0 0 0 0 0 0 0 0 0 0 0 0 0
27	0 0 0 0 0 1 1 0 0 0 0 0 0
28	0 0 0 0 0 0 0 0 0 0 0 0 0
29	0 1 0 0 0 0 0 0 0 0 0 0 0
30	1 0 0 0 0 0 0 0 0 0 0 0 1
31	0 0 0 1 1 0 0 0 0 0 0 0 0

After finding the error vector e, the original codeword can be computed as c={tilde over (c)}+e, where + is the modulo 2 addition. The first 8 bits in c are the original information bits.
FIGS. 33A-33B show the experimental results for single device case that the inventive receiver design meets the requirements of a BER<10⁻⁵at the operating points. FIGS. 34A-34B shows the results for a dual device case that the inventive receiver design meets the requirements of a BER<10⁻⁵at the operating points. While FIGS. 35A-35B shows the results for three device case that the inventive receiver design meets the requirements of a BER<10⁻⁵at the operating points.
Although the present invention has been shown and described with respect to several preferred embodiments thereof, various changes, omissions and additions to the form and detail thereof, may be made therein, without departing from the spirit and scope of the invention.

Claims

What is claimed is:

1. A transmitter module, used in a wireless charging system, for performing in-band communication with a receiver module in the wireless charging system to provide a message to the receiver module, the transmitter module comprising:

a matching network, having at least one input terminal coupled to a coil of the transmitter module and at least one output terminal;

a rectifier, coupled to the output terminal of the matching network; and

an impedance component, selectively coupled to the output terminal of the matching network to vary a reflected impedance of the transmitter module seen by the receiver module;

wherein by varying the reflected impedance of the transmitter module seen by the receiver module, the transmitter module communicate with the receiver module to provide power control commands, status and/or foreign object detection information.

2. The transmitter module of claim 1, further comprising a switch for coupling and decoupling the impedance component to and from the matching network.

3. The transmitter of claim 1, wherein the impedance component is capacitive or resistive.

4. The transmitter module of claim 1, wherein a signal on a transmitted power waveform is modulated to facilitate the communication between the transmitter module and the receiver module.

5. The transmitter module of claim 4, further comprising CRC calculation and attachment and channel encoding before the modulation.

6. A receiver module, used in a wireless charging system, for performing in-band communication with a transmitter module in the wireless charging system to receive a message from the transmitter module, the receiver module comprising:

a matching network, having at least one input terminal coupled to a coil of the receiver module and at least one output terminal;

an amplifier, coupled to the output terminal of the matching network; and

an impedance sensing circuit, coupled to the amplifier, for detecting changes in a reflected impedance of the transmitter module seen by the receiver module;

wherein by detecting changes in the reflected impedance of the transmitter module seen by the receiver module, the receiver module communicate with the transmitter module to receive power control commands, status and/or foreign object detection information.

7. The receiver module of claim 6, further comprising a front end filter, coupled to the impedance sensing circuit, for pulse shaping and noise rejection.

8. The receiver module of claim 7, wherein the front end filter comprises an analog anti-aliasing filter and an analog-to-digital converter (ADC).

9. The receiver module of claim 7, further comprising a preamble detection block, coupled to the front end filter, for message detection, synchronization, and equalization coefficient estimation.

10. The receiver module of claim 9, further comprising a decoding module, coupled to the preamble detection block and the front end filter, for equalization, demodulation, decoding and CRC check.

11. The receiver module of claim 6, wherein the impedance sensing circuit includes a current sensor for load sensing.