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US20160247879A1 - Trench semiconductor device layout configurations - Google Patents

Trench semiconductor device layout configurations Download PDF

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Publication number
US20160247879A1
US20160247879A1 US15/051,642 US201615051642A US2016247879A1 US 20160247879 A1 US20160247879 A1 US 20160247879A1 US 201615051642 A US201615051642 A US 201615051642A US 2016247879 A1 US2016247879 A1 US 2016247879A1
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United States
Prior art keywords
trench
interior
exterior
pattern
portions
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Abandoned
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US15/051,642
Inventor
Dosi Dosev
Don Rankila
Tatsuya Kamimura
Shunsuke Fukunaga
Steven Kosier
Peter West
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Sanken Electric Co Ltd
Polar Semiconductor LLC
Original Assignee
Sanken Electric Co Ltd
Polar Semiconductor LLC
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Application filed by Sanken Electric Co Ltd, Polar Semiconductor LLC filed Critical Sanken Electric Co Ltd
Priority to US15/051,642 priority Critical patent/US20160247879A1/en
Assigned to POLAR SEMICONDUCTOR, LLC, SANKEN ELECTRIC CO., LTD. reassignment POLAR SEMICONDUCTOR, LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: DOSEV, DOSI, KOSIER, STEVEN, RANKILA, DON, WEST, PETER, KAMIMURA, TATSUYA, FUKUNAGA, SHUNSUKE
Publication of US20160247879A1 publication Critical patent/US20160247879A1/en
Priority to US15/900,571 priority patent/US10580861B2/en
Priority to US16/724,862 priority patent/US11245006B2/en
Abandoned legal-status Critical Current

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    • H01L29/0661—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H01L29/0688—
    • H01L29/0692—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions

Definitions

  • the present invention relates to geometric layouts of trench semiconductor devices.
  • the device In many semiconductor devices, such as modern power MOSFET devices, it is desirable for the device to provide a high breakdown voltage that prevents reverse biasing and avalanche breakdown of the diode barriers of the device.
  • application of a reverse bias voltage across a diode barrier creates a depletion region in which the voltage gradient present there causes acceleration of charge carriers and the formation of electron-hole pairs by collisions between the charge carriers and dopant atoms.
  • the electron-hole pairs generally migrate to opposite sides of the depletion region; however, higher levels of reverse bias voltage create higher electric fields in the depletion region, which accelerate the electron-hole pairs to a degree that results in further collisions that form further electron-hole pairs.
  • This multiplication of charge carriers can eventually result in conduction of current in the reverse direction across the diode barrier, which is the condition known as avalanche breakdown of the device.
  • a trench semiconductor device consists of a plurality of parallel, interior MOS trenches formed in a semiconductor layer, with each trench being lined with dielectric material and then filled with a conductive material such as metal or doped polysilicon.
  • a conductive material such as metal or doped polysilicon.
  • an exterior trench is formed around an outside region of the device, having at least a portion generally perpendicular to the interior trenches. The gaps between the trenches effectively terminate the electric fields that tend to converge at the edges of the conductive legs formed in each trench, which results in a higher breakdown voltage.
  • U.S. Pat. No. 6,683,363 illustrates an example of a trench semiconductor device.
  • a trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern.
  • the exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern including a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material.
  • Various embodiments of the trench semiconductor device with unique trench patterns are disclosed. The various trench patterns provide configurations and/or performance characteristics that may be suitable for particular applications of the devices.
  • FIG. 1A is a top plan view of a MOSFET device formed as a trench semiconductor device according to an embodiment of the present invention.
  • FIG. 1B is a perspective view of the MOSFET device shown in FIG. 1A , sectioned at line B-B in FIG. 1A .
  • FIGS. 2-16 are top plan views of MOSFET devices formed as trench semiconductor devices according to various embodiments of the present invention.
  • FIG. 7A is a graph illustrating the measured breakdown voltages of a MOSFET device according to the embodiment of FIG. 7 for various dimensions of trench corner width and exterior trench gap length.
  • FIG. 8A is a graph illustrating the measured breakdown voltages of a MOSFET device according to the embodiment of FIG. 8 for various dimensions of gap distance and exterior trench length.
  • FIG. 1A is a top plan view of MOSFET device 10 formed as a trench semiconductor device according to an embodiment of the present invention.
  • FIG. 1B is a perspective view of MOSFET device 10 sectioned at line B-B in FIG. 1A .
  • MOSFET device 10 includes semiconductor layer 12 , a plurality of interior trenches 14 formed in semiconductor layer 12 , and exterior trench 16 formed in semiconductor layer 12 .
  • Interior trenches 14 and exterior trench 16 are lined with dielectric material 18 , such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon.
  • a metal layer (not shown) is formed over the entire structure, so that a metal/semiconductor barrier is formed where the metal layer adjoins the mesa regions of semiconductor layer 12 between interior trenches 14 .
  • interior trenches 14 are formed in a snake pattern enclosed by exterior trench 16 .
  • the legs of interior trenches 14 are separated from one another by interior gap distance G I .
  • Each leg of interior trenches 14 has a trench width W T , and interior trenches 14 are spaced from exterior trench 16 by gap distance G E .
  • gap distance G I may be about 2 micrometers (pm)
  • trench width W T may be about 1.4 ⁇ m
  • gap distance G E may be about 2 ⁇ m.
  • FIGS. 2-16 are top plan views of MOSFET devices formed as trench semiconductor devices with alternative trench patterns. Only top plan views of these embodiments are shown, for simplicity, as the nature of the perspective view of each embodiment (similar to that shown in FIG. 1B ) will be apparent to those skilled in the art based on the configuration illustrated in the corresponding top plan view.
  • a fill pattern is used in FIGS. 2-16 to illustrate the trench patterns, for ease of understanding.
  • FIG. 2 is a top plan view of MOSFET device 20 formed as a trench semiconductor device according to another embodiment of the present invention.
  • MOSFET device 20 includes semiconductor layer 12 , a plurality of interior trenches 14 formed in semiconductor layer 12 , and exterior trench 16 formed in semiconductor layer 12 .
  • Interior trenches 14 and exterior trench 16 are lined with dielectric material 18 , such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon.
  • Interior trenches 14 are formed in a pattern of closed rectangles, enclosed by exterior trench 16 . In the pattern shown, the sides of each closed rectangle formed by interior trenches 14 are separated from one another by interior gap distance G I .
  • Each interior trench 14 has a trench width W T , and interior trenches 14 are spaced from exterior trench 16 by gap distance G E .
  • gap distance G I may be about 2 ⁇ m
  • trench width W T may be about 1.4 ⁇ m
  • gap distance G E may be about 2 ⁇ m
  • FIG. 3 is a top plan view of MOSFET device 30 formed as a trench semiconductor device according to another embodiment of the present invention.
  • MOSFET device 30 includes semiconductor layer 12 , a plurality of interior trenches 14 formed in semiconductor layer 12 , intermediate trench 16 a formed in semiconductor layer 12 , and exterior trench 16 b formed in semiconductor layer 12 .
  • Interior trenches 14 , intermediate trench 16 a and exterior trench 16 b are lined with dielectric material 18 , such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon.
  • Interior trenches 14 are formed in a snake pattern enclosed by intermediate trench 16 a, and intermediate trench 16 a is enclosed by exterior trench 16 b.
  • each leg of interior trenches 14 has a trench width W T , and interior trenches 14 are spaced from intermediate trench 16 a by gap distance G E .
  • Intermediate trench 16 a is separated from exterior trench 16 b by gap distance G T .
  • gap distance G I may be about 2 ⁇ m
  • trench width W T may be about 1.4 ⁇ m
  • gap distance G E may be about 2 ⁇ m
  • gap distance G T may be about 2 ⁇ m.
  • FIG. 4 is a top plan view of MOSFET device 40 formed as a trench semiconductor device according to another embodiment of the present invention.
  • MOSFET device 40 includes semiconductor layer 12 , a plurality of interior trenches 14 formed in semiconductor layer 12 , and segmented exterior trench 16 having gaps 42 therein formed in semiconductor layer 12 .
  • Interior trenches 14 and exterior trench 16 are lined with dielectric material 18 , such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon.
  • Interior trenches 14 are formed in a snake pattern partially enclosed by segmented exterior trench 16 . In the snake pattern, the legs of interior trenches 14 are separated from one another by interior gap distance G I .
  • Each leg of interior trenches 14 has a trench width W T , and interior trenches 14 are spaced from exterior trench 16 by gap distance G E .
  • Gaps 42 in segmented exterior trench 16 have a gap length G O .
  • gap distance G I may be about 2 ⁇ m
  • trench width W T may be about 1.4 ⁇ m
  • gap distance G E may be about 2 ⁇ m
  • gap length G O may be about 2 ⁇ m.
  • FIG. 5 is a top plan view of MOSFET device 50 formed as a trench semiconductor device according to another embodiment of the present invention.
  • MOSFET device 50 includes semiconductor layer 12 , a plurality of interior trenches 14 formed in semiconductor layer 12 , and exterior trench 16 having notch features 52 formed in semiconductor layer 12 .
  • Interior trenches 14 and exterior trench 16 are lined with dielectric material 18 , such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon.
  • Interior trenches 14 are formed in a snake pattern enclosed by exterior trench 16 . In the snake pattern, the legs of interior trenches 14 are separated from one another by interior gap distance G I .
  • Each leg of interior trenches 14 has a trench width W T , and interior trenches 14 are spaced from exterior trench 16 by gap distance G E .
  • Notch features 52 in exterior trench 16 are formed adjacent to openings between the legs of the snake pattern of interior trench 14 , and each notch feature has an extending width W N .
  • gap distance G I may be about 2 ⁇ m
  • trench width W T may be about 1.4 ⁇ m
  • gap distance G E may be about 2 ⁇ m
  • extending width W N may be about 0.5 ⁇ m.
  • FIG. 6 is a top plan view of MOSFET device 60 formed as a trench semiconductor device according to another embodiment of the present invention.
  • MOSFET device 60 includes semiconductor layer 12 , a plurality of interior trenches 14 formed in semiconductor layer 12 , and exterior trench 16 formed in semiconductor layer 12 .
  • Interior trenches 14 and exterior trench 16 are lined with dielectric material 18 , such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon.
  • Interior trenches 14 are formed in a pattern having an outer frame and a plurality of vertical trench legs connecting the top and bottom horizontal segments of the outer frame. In the pattern shown, the vertical legs of interior trenches 14 are separated from one another by interior gap distance G I .
  • Interior trenches 14 have a trench width W T , and interior trenches 14 are spaced from exterior trench 16 by gap distance G E .
  • gap distance G I may be about 2 ⁇ m
  • trench width W T may be about 1.4 ⁇ m
  • gap distance G E may be about 2 ⁇ m
  • FIG. 7 is a top plan view of MOSFET device 70 formed as a trench semiconductor device according to another embodiment of the present invention.
  • MOSFET device 70 includes semiconductor layer 12 , a plurality of interior trenches 14 formed in semiconductor layer 12 , and segmented exterior trench 16 having gaps 72 therein formed in semiconductor layer 12 .
  • Interior trenches 14 and exterior trench 16 are lined with dielectric material 18 , such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon.
  • Interior trenches 14 are formed in a pattern of vertical trench legs. In the pattern shown, the vertical legs of interior trenches 14 are separated from one another by interior gap distance G I .
  • Interior trenches 14 have a trench width W T , and interior trenches 14 are spaced from exterior trench 16 by gap distance G E .
  • Gaps 72 in segmented exterior trench 16 have a gap length G O .
  • gap distance G I may be about 2 ⁇ m
  • trench width W T may be about 1.4 ⁇ m
  • gap distance G E may be about 2 ⁇ m
  • gap length G O may be about 1.7 ⁇ m
  • trench corner width W C may be about 1.5 ⁇ m.
  • FIG. 7A is a graph illustrating the measured breakdown voltages of MOSFET device 70 for various dimensions of trench corner width W C and exterior trench gap length G O .
  • the dimensions of trench corner width W C and exterior trench gap length G O affect the breakdown voltage of the device, and can be controlled in order to provide a desired breakdown voltage value.
  • FIG. 7A Specific examples are shown in FIG. 7A , illustrating that a breakdown voltage of 117 Volts was achieved for an embodiment with exterior trench gap length G O of 0.7 ⁇ m and a trench corner width W C of 2.5 ⁇ m. A similar breakdown voltage of 117 Volts was also achieved for an embodiment with an exterior trench gap length G O of 1.0 ⁇ m and a trench corner width W C of 2.2 ⁇ m. A breakdown voltage of 118 Volts was achieved for an embodiment with an exterior trench gap length G O of 1.25 ⁇ m and a trench corner width W C of 2.2 ⁇ m.
  • a breakdown voltage of 112 Volts was achieved for an embodiment with a trench corner width W C of 1.5 ⁇ m
  • a breakdown voltage of 117 Volts was achieved for an embodiment with a trench corner width W C of 2.0 ⁇ m
  • a breakdown voltage of 118 Volts was achieved for an embodiment with a trench corner width W C of 2.2 ⁇ m.
  • a breakdown voltage of 121 Volts was achieved for an embodiment with an exterior trench gap length G O of 2.0 ⁇ m and a trench corner width W C of 2.2 ⁇ m.
  • FIG. 8 is a top plan view of MOSFET device 80 formed as a trench semiconductor device according to another embodiment of the present invention.
  • MOSFET device 80 includes semiconductor layer 12 , a plurality of interior trenches 14 formed in semiconductor layer 12 , and segmented exterior trench 16 having gaps 82 therein formed in semiconductor layer 12 .
  • Interior trenches 14 and exterior trench 16 are lined with dielectric material 18 , such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon.
  • Interior trenches 14 are formed in a pattern of vertical trench legs. In the pattern shown, the vertical legs of interior trenches 14 are separated from one another by interior gap distance G I .
  • Interior trenches 14 have a trench width W T , and interior trenches 14 are spaced from exterior trench 16 by gap distance G E .
  • Gaps 82 in segmented exterior trench 16 have a gap length G O .
  • Exterior trench 16 is segmented in the embodiment shown in FIG. 8 so that the segments of exterior trench 16 line up with the legs of interior trench 14 .
  • gap distance G I may be about 2 ⁇ m
  • trench width W T may be about 1.4 ⁇ m
  • gap distance G E may be about 2 ⁇ m
  • exterior trench length L T may be about 2 ⁇ m.
  • these dimensions may be adjusted to control the breakdown voltage at the termination of MOSFET device 80 .
  • FIG. 8A is a graph illustrating the measured breakdown voltages of MOSFET device 80 for various dimensions of gap distance G E and exterior trench length L T . As can be seen in FIG. 8A , the dimensions of gap distance G E and exterior trench length L T affect the breakdown voltage of the device, and can be controlled in order to provide a desired breakdown voltage value.
  • FIG. 8A Specific examples are shown in FIG. 8A , illustrating that a breakdown voltage of 114 Volts was achieved for an embodiment with a gap distance G E of 1.0 ⁇ m and an exterior trench length L T of 2.5 ⁇ m. A similar breakdown voltage of 114 Volts was also achieved for an embodiment with a gap distance G E of 1.5 ⁇ m and an exterior trench length L T of 2.5 ⁇ m. At a gap distance G E of 2.0 ⁇ m, a breakdown voltage of 109 Volts was achieved for an embodiment with an exterior trench length L T of 3.5 ⁇ m, and a breakdown voltage of 111 Volts was achieved for an embodiment with an exterior trench length L T of 5.0 ⁇ m.
  • a breakdown voltage of 111 Volts was achieved for an embodiment with a gap distance G E of 2.5 ⁇ m and exterior trench length L T of 2.5 ⁇ m.
  • a breakdown voltage of 112 Volts was achieved for an embodiment with a gap distance G E of 3.0 ⁇ m and exterior trench length L T of 2.5 ⁇ m, and also for an embodiment with a gap distance G E of 3.5 ⁇ m and exterior trench length L T of 2.5 ⁇ m.
  • FIG. 9 is a top plan view of MOSFET device 90 formed as a trench semiconductor device according to another embodiment of the present invention.
  • MOSFET device 90 includes semiconductor layer 12 , a plurality of interior trenches 14 formed in semiconductor layer 12 , and exterior trench 16 formed in semiconductor layer 12 .
  • Interior trenches 14 and exterior trench 16 are lined with dielectric material 18 , such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon.
  • Interior trenches 14 are formed in a snake pattern enclosed by exterior trench 16 . The snake pattern is angled diagonally within exterior trench 16 as shown in FIG. 9 .
  • each leg of interior trenches 14 is separated from one another by interior gap distance G I .
  • Each leg of interior trenches 14 has a trench width W T , and interior trenches 14 are spaced from exterior trench 16 by a minimum gap distance G E .
  • gap distance G I may be about 2 ⁇ m
  • trench width W T may be about 1.4 ⁇ m
  • gap distance G E may be about 2 ⁇ m
  • FIG. 10 is a top plan view of MOSFET device 100 formed as a trench semiconductor device according to another embodiment of the present invention.
  • MOSFET device 100 includes semiconductor layer 12 , a plurality of interior trenches 14 formed in semiconductor layer 12 , and exterior trench 16 formed in semiconductor layer 12 .
  • Interior trenches 14 and exterior trench 16 are lined with dielectric material 18 , such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon.
  • Interior trenches 14 are formed in a grid pattern enclosed by exterior trench 16 . In the grid pattern, the legs of interior trenches 14 are separated from one another by interior gap distance G I .
  • Each leg of interior trenches 14 has a trench width W T , and interior trenches 14 are spaced from exterior trench 16 by gap distance G E .
  • gap distance G I may be about 4.5 ⁇ m
  • trench width W T may be about 1.4 ⁇ m
  • gap distance G E may be about 2 ⁇ m.
  • FIG. 11 is a top plan view of MOSFET device 110 formed as a trench semiconductor device according to another embodiment of the present invention.
  • MOSFET device 110 includes semiconductor layer 12 , a plurality of interior trenches 14 formed in semiconductor layer 12 , and exterior trench 16 formed in semiconductor layer 12 .
  • Interior trenches 14 and exterior trench 16 are lined with dielectric material 18 , such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon.
  • Interior trenches 14 are formed in a grid pattern enclosed by exterior trench 16 . In the grid pattern, the legs of interior trenches 14 are separated from one another by interior gap distance G I .
  • interior trenches 14 extend beyond a square/rectangular grid pattern at vertical trench extensions 112 .
  • Each leg of interior trenches 14 has a trench width W T , and interior trenches 14 are spaced from exterior trench 16 by gap distance G E .
  • gap distance G I may be about 4.5 ⁇ m
  • trench width W T may be about 1.4 ⁇ m
  • gap distance G E may be about 2 ⁇ m.
  • FIG. 12 is a top plan view of MOSFET device 120 formed as a trench semiconductor device according to another embodiment of the present invention.
  • MOSFET device 120 includes semiconductor layer 12 , a plurality of interior trenches 14 formed in semiconductor layer 12 , and exterior trench 16 formed in semiconductor layer 12 .
  • Interior trenches 14 and exterior trench 16 are lined with dielectric material 18 , such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon.
  • Interior trenches 14 are formed in a pattern of vertical trench legs. In the pattern shown, the vertical legs of interior trenches 14 are separated from one another by interior gap distance G I .
  • Interior trenches 14 have a trench width W T , and interior trenches 14 are spaced from exterior trench 16 by gap distance G E .
  • Exterior trench 16 has a trench width that is greater than the trench width W T of interior trenches 14 , such as twice the trench width W T in an exemplary embodiment.
  • gap distance G I may be about 2.0 ⁇ m
  • trench width W T may be about 1.4 ⁇ m
  • gap distance G E may be about 2 ⁇ m.
  • FIG. 13 is a top plan view of MOSFET device 130 formed as a trench semiconductor device according to another embodiment of the present invention.
  • MOSFET device 130 includes semiconductor layer 12 , a plurality of interior trenches 14 formed in semiconductor layer 12 , and exterior trench 16 formed in semiconductor layer 12 .
  • Middle dividing trench 136 is also formed in semiconductor layer 12 , dividing the interior region inside exterior trench 16 into two separate regions, each of which includes a plurality of interior trenches 14 .
  • Interior trenches 14 , exterior trench 16 and middle dividing trench 136 are lined with dielectric material 18 , such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon.
  • Interior trenches 14 are formed in a pattern of vertical trench legs. In the pattern shown, the vertical legs of interior trenches 14 are separated from one another by interior gap distance G I . Interior trenches 14 have a trench width W T , and interior trenches 14 are spaced from exterior trench 16 by gap distance G E .
  • gap distance G I may be about 2.0 ⁇ m
  • trench width W T may be about 1.4 ⁇ m
  • gap distance G E may be about 2 ⁇ m.
  • FIG. 14 is a top plan view of MOSFET device 140 formed as a trench semiconductor device according to another embodiment of the present invention.
  • MOSFET device 140 includes semiconductor layer 12 , a plurality of interior trenches 14 formed in semiconductor layer 12 , and exterior trench 16 formed in semiconductor layer 12 .
  • Interior trenches 14 and exterior trench 16 are lined with dielectric material 18 , such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon.
  • Interior trenches 14 are formed in an offset grid pattern enclosed by exterior trench 16 , as shown in FIG. 14 .
  • interior trenches 14 are separated from one another by interior gap distance G I , as are adjacent horizontal legs of interior trenches 14 .
  • Each leg of interior trenches 14 has a trench width W T , and interior trenches 14 are spaced from exterior trench 16 by gap distance G E .
  • gap distance G I may be about 4.5 ⁇ m
  • trench width W T may be about 1.4 ⁇ m
  • gap distance G E may be about 2 ⁇ m.
  • FIG. 15 is a top plan view of MOSFET device 150 formed as a trench semiconductor device according to another embodiment of the present invention.
  • MOSFET device 150 includes semiconductor layer 12 , a plurality of interior trenches 14 formed in semiconductor layer 12 , and exterior trench 16 formed in semiconductor layer 12 .
  • Interior trenches 14 and exterior trench 16 are lined with dielectric material 18 , such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon.
  • Interior trenches 14 are formed in a honeycomb pattern enclosed by exterior trench 16 , as shown in FIG. 15 . In the honeycomb pattern, adjacent vertical legs of interior trenches 14 are separated from one another by interior gap distance G I .
  • Each leg of interior trenches 14 has a trench width W T , and interior trenches 14 are spaced from exterior trench 16 by gap distance G E .
  • trench width W T may be about 1.4 ⁇ m
  • gap distance G E may be about 2 ⁇ m.
  • FIG. 16 is a top plan view of MOSFET device 160 formed as a trench semiconductor device according to another embodiment of the present invention.
  • MOSFET device 160 includes semiconductor layer 12 , a plurality of interior trenches 14 formed in semiconductor layer 12 , and exterior trench 16 formed in semiconductor layer 12 .
  • Interior trenches 14 and exterior trench 16 are lined with dielectric material 18 , such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon.
  • Interior trenches 14 are formed in a geometric trench pattern formed of six sided polygons and eight sided polygons enclosed by exterior trench 16 , as shown in FIG. 16 .
  • interior trenches 14 In the geometric trench pattern, adjacent vertical legs of interior trenches 14 are separated from one another by interior gap distance G I . Each leg of interior trenches 14 has a trench width W T , and interior trenches 14 are spaced from exterior trench 16 by gap distance G E .
  • trench width W T may be about 1.4 ⁇ m
  • gap distance G E may be about 2 ⁇ m.
  • inventions disclosed herein include geometric features that can be mixed and matched with any other disclosed embodiments.
  • segmented outer trench 16 shown in FIG. 7 may be used with the snake trench pattern shown in FIG. 1A in an alternative embodiment.
  • Other features may also be combined and modified to form additional alternative embodiments and configurations.
  • modifications of the dimensions of trenches or other features, as well as of gaps between trenches or other features, are able to be modified in order to adjust the performance of the device, such as the breakdown voltage of the device. Examples of such modifications and the resulting performance adjustments are discussed specifically with respect to the embodiments of FIGS. 7 and 8 , and modifications to others of the disclosed embodiments will also result in performance adjustments that may be selected and optimized for a particular application.

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Abstract

A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern including a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material.

Description

    CROSS-REFERENCE TO RELATED APPLICATION(S)
  • This application claims the benefit of U.S. Provisional Application No. 62/119,555 filed Feb. 23, 2015 for “Trench Semiconductor Device Layout Configurations” by D. Dosev et al.
    • Incorporation By Reference
  • U.S. Provisional Application No. 62/119,555 is hereby incorporated herein by reference in its entirety.
    • BACKGROUND
  • The present invention relates to geometric layouts of trench semiconductor devices.
  • In many semiconductor devices, such as modern power MOSFET devices, it is desirable for the device to provide a high breakdown voltage that prevents reverse biasing and avalanche breakdown of the diode barriers of the device. In these devices, application of a reverse bias voltage across a diode barrier creates a depletion region in which the voltage gradient present there causes acceleration of charge carriers and the formation of electron-hole pairs by collisions between the charge carriers and dopant atoms. The electron-hole pairs generally migrate to opposite sides of the depletion region; however, higher levels of reverse bias voltage create higher electric fields in the depletion region, which accelerate the electron-hole pairs to a degree that results in further collisions that form further electron-hole pairs. This multiplication of charge carriers can eventually result in conduction of current in the reverse direction across the diode barrier, which is the condition known as avalanche breakdown of the device.
  • One technique that has been successfully employed to increase the breakdown voltage of a MOSFET device is to form the device as a trench semiconductor device. A trench semiconductor device consists of a plurality of parallel, interior MOS trenches formed in a semiconductor layer, with each trench being lined with dielectric material and then filled with a conductive material such as metal or doped polysilicon. In addition, an exterior trench is formed around an outside region of the device, having at least a portion generally perpendicular to the interior trenches. The gaps between the trenches effectively terminate the electric fields that tend to converge at the edges of the conductive legs formed in each trench, which results in a higher breakdown voltage. U.S. Pat. No. 6,683,363 illustrates an example of a trench semiconductor device.
  • Further developments in the geometry of a trench semiconductor device can provide characteristics and results that advance the state of the art, such as in terms of performance, cost, space efficiency, or others, or to simply provide an alternative configuration that may be appropriate for selected applications.
    • SUMMARY
  • A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern including a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material. Various embodiments of the trench semiconductor device with unique trench patterns are disclosed. The various trench patterns provide configurations and/or performance characteristics that may be suitable for particular applications of the devices.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1A is a top plan view of a MOSFET device formed as a trench semiconductor device according to an embodiment of the present invention.
  • FIG. 1B is a perspective view of the MOSFET device shown in FIG. 1A, sectioned at line B-B in FIG. 1A.
  • FIGS. 2-16 are top plan views of MOSFET devices formed as trench semiconductor devices according to various embodiments of the present invention.
  • FIG. 7A is a graph illustrating the measured breakdown voltages of a MOSFET device according to the embodiment of FIG. 7 for various dimensions of trench corner width and exterior trench gap length.
  • FIG. 8A is a graph illustrating the measured breakdown voltages of a MOSFET device according to the embodiment of FIG. 8 for various dimensions of gap distance and exterior trench length.
    •  DETAILED DESCRIPTION
  • FIG. 1A is a top plan view of MOSFET device 10 formed as a trench semiconductor device according to an embodiment of the present invention. FIG. 1B is a perspective view of MOSFET device 10 sectioned at line B-B in FIG. 1A. As shown in FIGS. 1A and 1B, MOSFET device 10 includes semiconductor layer 12, a plurality of interior trenches 14 formed in semiconductor layer 12, and exterior trench 16 formed in semiconductor layer 12. Interior trenches 14 and exterior trench 16 are lined with dielectric material 18, such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon. A metal layer (not shown) is formed over the entire structure, so that a metal/semiconductor barrier is formed where the metal layer adjoins the mesa regions of semiconductor layer 12 between interior trenches 14.
  • As best illustrated in FIG. 1A, interior trenches 14 are formed in a snake pattern enclosed by exterior trench 16. In the snake pattern, the legs of interior trenches 14 are separated from one another by interior gap distance GI. Each leg of interior trenches 14 has a trench width WT, and interior trenches 14 are spaced from exterior trench 16 by gap distance GE.
  • In an exemplary embodiment, gap distance GI may be about 2 micrometers (pm), trench width WT may be about 1.4 μm, and gap distance GE may be about 2 μm.
  • FIGS. 2-16 are top plan views of MOSFET devices formed as trench semiconductor devices with alternative trench patterns. Only top plan views of these embodiments are shown, for simplicity, as the nature of the perspective view of each embodiment (similar to that shown in FIG. 1B) will be apparent to those skilled in the art based on the configuration illustrated in the corresponding top plan view. A fill pattern is used in FIGS. 2-16 to illustrate the trench patterns, for ease of understanding.
  • FIG. 2 is a top plan view of MOSFET device 20 formed as a trench semiconductor device according to another embodiment of the present invention. MOSFET device 20 includes semiconductor layer 12, a plurality of interior trenches 14 formed in semiconductor layer 12, and exterior trench 16 formed in semiconductor layer 12. Interior trenches 14 and exterior trench 16 are lined with dielectric material 18, such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon. Interior trenches 14 are formed in a pattern of closed rectangles, enclosed by exterior trench 16. In the pattern shown, the sides of each closed rectangle formed by interior trenches 14 are separated from one another by interior gap distance GI. Each interior trench 14 has a trench width WT, and interior trenches 14 are spaced from exterior trench 16 by gap distance GE.
  • In an exemplary embodiment, gap distance GI may be about 2 μm, trench width WT may be about 1.4 μm, and gap distance GE may be about 2 μm.
  • FIG. 3 is a top plan view of MOSFET device 30 formed as a trench semiconductor device according to another embodiment of the present invention. MOSFET device 30 includes semiconductor layer 12, a plurality of interior trenches 14 formed in semiconductor layer 12, intermediate trench 16 a formed in semiconductor layer 12, and exterior trench 16 b formed in semiconductor layer 12. Interior trenches 14, intermediate trench 16 a and exterior trench 16 b are lined with dielectric material 18, such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon. Interior trenches 14 are formed in a snake pattern enclosed by intermediate trench 16 a, and intermediate trench 16 a is enclosed by exterior trench 16 b. In the snake pattern, the legs of interior trenches 14 are separated from one another by interior gap distance GI. Each leg of interior trenches 14 has a trench width WT, and interior trenches 14 are spaced from intermediate trench 16 a by gap distance GE. Intermediate trench 16 a is separated from exterior trench 16 b by gap distance GT.
  • In an exemplary embodiment, gap distance GI may be about 2 μm, trench width WT may be about 1.4 μm, gap distance GE may be about 2 μm, and gap distance GT may be about 2 μm.
  • FIG. 4 is a top plan view of MOSFET device 40 formed as a trench semiconductor device according to another embodiment of the present invention. MOSFET device 40 includes semiconductor layer 12, a plurality of interior trenches 14 formed in semiconductor layer 12, and segmented exterior trench 16 having gaps 42 therein formed in semiconductor layer 12. Interior trenches 14 and exterior trench 16 are lined with dielectric material 18, such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon. Interior trenches 14 are formed in a snake pattern partially enclosed by segmented exterior trench 16. In the snake pattern, the legs of interior trenches 14 are separated from one another by interior gap distance GI. Each leg of interior trenches 14 has a trench width WT, and interior trenches 14 are spaced from exterior trench 16 by gap distance GE. Gaps 42 in segmented exterior trench 16 have a gap length GO.
  • In an exemplary embodiment, gap distance GI may be about 2 μm, trench width WT may be about 1.4 μm, gap distance GE may be about 2 μm, and gap length GO may be about 2 μm.
  • FIG. 5 is a top plan view of MOSFET device 50 formed as a trench semiconductor device according to another embodiment of the present invention. MOSFET device 50 includes semiconductor layer 12, a plurality of interior trenches 14 formed in semiconductor layer 12, and exterior trench 16 having notch features 52 formed in semiconductor layer 12. Interior trenches 14 and exterior trench 16 are lined with dielectric material 18, such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon. Interior trenches 14 are formed in a snake pattern enclosed by exterior trench 16. In the snake pattern, the legs of interior trenches 14 are separated from one another by interior gap distance GI. Each leg of interior trenches 14 has a trench width WT, and interior trenches 14 are spaced from exterior trench 16 by gap distance GE. Notch features 52 in exterior trench 16 are formed adjacent to openings between the legs of the snake pattern of interior trench 14, and each notch feature has an extending width WN.
  • In an exemplary embodiment, gap distance GI may be about 2 μm, trench width WT may be about 1.4 μm, gap distance GE may be about 2 μm, and extending width WN may be about 0.5 μm.
  • FIG. 6 is a top plan view of MOSFET device 60 formed as a trench semiconductor device according to another embodiment of the present invention. MOSFET device 60 includes semiconductor layer 12, a plurality of interior trenches 14 formed in semiconductor layer 12, and exterior trench 16 formed in semiconductor layer 12. Interior trenches 14 and exterior trench 16 are lined with dielectric material 18, such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon. Interior trenches 14 are formed in a pattern having an outer frame and a plurality of vertical trench legs connecting the top and bottom horizontal segments of the outer frame. In the pattern shown, the vertical legs of interior trenches 14 are separated from one another by interior gap distance GI. Interior trenches 14 have a trench width WT, and interior trenches 14 are spaced from exterior trench 16 by gap distance GE.
  • In an exemplary embodiment, gap distance GI may be about 2 μm, trench width WT may be about 1.4 μm, and gap distance GE may be about 2 μm.
  • FIG. 7 is a top plan view of MOSFET device 70 formed as a trench semiconductor device according to another embodiment of the present invention. MOSFET device 70 includes semiconductor layer 12, a plurality of interior trenches 14 formed in semiconductor layer 12, and segmented exterior trench 16 having gaps 72 therein formed in semiconductor layer 12. Interior trenches 14 and exterior trench 16 are lined with dielectric material 18, such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon. Interior trenches 14 are formed in a pattern of vertical trench legs. In the pattern shown, the vertical legs of interior trenches 14 are separated from one another by interior gap distance GI. Interior trenches 14 have a trench width WT, and interior trenches 14 are spaced from exterior trench 16 by gap distance GE. Gaps 72 in segmented exterior trench 16 have a gap length GO.
  • In an exemplary embodiment, gap distance GI may be about 2 μm, trench width WT may be about 1.4 μm, gap distance GE may be about 2 μm, gap length GO may be about 1.7 μm, and trench corner width WC may be about 1.5 μm. In other embodiments, these dimensions may be adjusted to control the breakdown voltage at the termination of MOSFET device 70. FIG. 7A is a graph illustrating the measured breakdown voltages of MOSFET device 70 for various dimensions of trench corner width WC and exterior trench gap length GO. As can be seen in FIG. 7A, the dimensions of trench corner width WC and exterior trench gap length GO affect the breakdown voltage of the device, and can be controlled in order to provide a desired breakdown voltage value.
  • Specific examples are shown in FIG. 7A, illustrating that a breakdown voltage of 117 Volts was achieved for an embodiment with exterior trench gap length GO of 0.7 μm and a trench corner width WC of 2.5 μm. A similar breakdown voltage of 117 Volts was also achieved for an embodiment with an exterior trench gap length GO of 1.0 μm and a trench corner width WC of 2.2 μm. A breakdown voltage of 118 Volts was achieved for an embodiment with an exterior trench gap length GO of 1.25 μm and a trench corner width WC of 2.2 μm. At an exterior trench gap length GO of 1.5 μm, a breakdown voltage of 112 Volts was achieved for an embodiment with a trench corner width WC of 1.5 μm, a breakdown voltage of 117 Volts was achieved for an embodiment with a trench corner width WC of 2.0 μm, and a breakdown voltage of 118 Volts was achieved for an embodiment with a trench corner width WC of 2.2 μm. A breakdown voltage of 121 Volts was achieved for an embodiment with an exterior trench gap length GO of 2.0 μm and a trench corner width WC of 2.2 μm.
  • FIG. 8 is a top plan view of MOSFET device 80 formed as a trench semiconductor device according to another embodiment of the present invention. MOSFET device 80 includes semiconductor layer 12, a plurality of interior trenches 14 formed in semiconductor layer 12, and segmented exterior trench 16 having gaps 82 therein formed in semiconductor layer 12. Interior trenches 14 and exterior trench 16 are lined with dielectric material 18, such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon. Interior trenches 14 are formed in a pattern of vertical trench legs. In the pattern shown, the vertical legs of interior trenches 14 are separated from one another by interior gap distance GI. Interior trenches 14 have a trench width WT, and interior trenches 14 are spaced from exterior trench 16 by gap distance GE. Gaps 82 in segmented exterior trench 16 have a gap length GO. Exterior trench 16 is segmented in the embodiment shown in FIG. 8 so that the segments of exterior trench 16 line up with the legs of interior trench 14.
  • In an exemplary embodiment, gap distance GI may be about 2 μm, trench width WT may be about 1.4 μm, gap distance GE may be about 2 μm, and exterior trench length LT may be about 2 μm. In other embodiments, these dimensions may be adjusted to control the breakdown voltage at the termination of MOSFET device 80. FIG. 8A is a graph illustrating the measured breakdown voltages of MOSFET device 80 for various dimensions of gap distance GE and exterior trench length LT. As can be seen in FIG. 8A, the dimensions of gap distance GE and exterior trench length LT affect the breakdown voltage of the device, and can be controlled in order to provide a desired breakdown voltage value.
  • Specific examples are shown in FIG. 8A, illustrating that a breakdown voltage of 114 Volts was achieved for an embodiment with a gap distance GE of 1.0 μm and an exterior trench length LT of 2.5 μm. A similar breakdown voltage of 114 Volts was also achieved for an embodiment with a gap distance GE of 1.5 μm and an exterior trench length LT of 2.5 μm. At a gap distance GE of 2.0 μm, a breakdown voltage of 109 Volts was achieved for an embodiment with an exterior trench length LT of 3.5 μm, and a breakdown voltage of 111 Volts was achieved for an embodiment with an exterior trench length LT of 5.0 μm. A breakdown voltage of 111 Volts was achieved for an embodiment with a gap distance GE of 2.5 μm and exterior trench length LT of 2.5 μm. A breakdown voltage of 112 Volts was achieved for an embodiment with a gap distance GE of 3.0 μm and exterior trench length LT of 2.5 μm, and also for an embodiment with a gap distance GE of 3.5 μm and exterior trench length LT of 2.5 μm.
  • FIG. 9 is a top plan view of MOSFET device 90 formed as a trench semiconductor device according to another embodiment of the present invention. MOSFET device 90 includes semiconductor layer 12, a plurality of interior trenches 14 formed in semiconductor layer 12, and exterior trench 16 formed in semiconductor layer 12. Interior trenches 14 and exterior trench 16 are lined with dielectric material 18, such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon. Interior trenches 14 are formed in a snake pattern enclosed by exterior trench 16. The snake pattern is angled diagonally within exterior trench 16 as shown in FIG. 9. In the snake pattern, the legs of interior trenches 14 are separated from one another by interior gap distance GI. Each leg of interior trenches 14 has a trench width WT, and interior trenches 14 are spaced from exterior trench 16 by a minimum gap distance GE.
  • In an exemplary embodiment, gap distance GI may be about 2 μm, trench width WT may be about 1.4 μm, and gap distance GE may be about 2 μm.
  • FIG. 10 is a top plan view of MOSFET device 100 formed as a trench semiconductor device according to another embodiment of the present invention. MOSFET device 100 includes semiconductor layer 12, a plurality of interior trenches 14 formed in semiconductor layer 12, and exterior trench 16 formed in semiconductor layer 12. Interior trenches 14 and exterior trench 16 are lined with dielectric material 18, such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon. Interior trenches 14 are formed in a grid pattern enclosed by exterior trench 16. In the grid pattern, the legs of interior trenches 14 are separated from one another by interior gap distance GI. Each leg of interior trenches 14 has a trench width WT, and interior trenches 14 are spaced from exterior trench 16 by gap distance GE.
  • In an exemplary embodiment, gap distance GI may be about 4.5 μm, trench width WT may be about 1.4 μm, and gap distance GE may be about 2 μm.
  • FIG. 11 is a top plan view of MOSFET device 110 formed as a trench semiconductor device according to another embodiment of the present invention. MOSFET device 110 includes semiconductor layer 12, a plurality of interior trenches 14 formed in semiconductor layer 12, and exterior trench 16 formed in semiconductor layer 12. Interior trenches 14 and exterior trench 16 are lined with dielectric material 18, such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon. Interior trenches 14 are formed in a grid pattern enclosed by exterior trench 16. In the grid pattern, the legs of interior trenches 14 are separated from one another by interior gap distance GI. The vertical legs of interior trenches 14 extend beyond a square/rectangular grid pattern at vertical trench extensions 112. Each leg of interior trenches 14 has a trench width WT, and interior trenches 14 are spaced from exterior trench 16 by gap distance GE.
  • In an exemplary embodiment, gap distance GI may be about 4.5 μm, trench width WT may be about 1.4 μm, and gap distance GE may be about 2 μm.
  • FIG. 12 is a top plan view of MOSFET device 120 formed as a trench semiconductor device according to another embodiment of the present invention. MOSFET device 120 includes semiconductor layer 12, a plurality of interior trenches 14 formed in semiconductor layer 12, and exterior trench 16 formed in semiconductor layer 12. Interior trenches 14 and exterior trench 16 are lined with dielectric material 18, such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon. Interior trenches 14 are formed in a pattern of vertical trench legs. In the pattern shown, the vertical legs of interior trenches 14 are separated from one another by interior gap distance GI. Interior trenches 14 have a trench width WT, and interior trenches 14 are spaced from exterior trench 16 by gap distance GE. Exterior trench 16 has a trench width that is greater than the trench width WT of interior trenches 14, such as twice the trench width WT in an exemplary embodiment.
  • In an exemplary embodiment, gap distance GI may be about 2.0 μm, trench width WT may be about 1.4 μm, and gap distance GE may be about 2 μm.
  • FIG. 13 is a top plan view of MOSFET device 130 formed as a trench semiconductor device according to another embodiment of the present invention. MOSFET device 130 includes semiconductor layer 12, a plurality of interior trenches 14 formed in semiconductor layer 12, and exterior trench 16 formed in semiconductor layer 12. Middle dividing trench 136 is also formed in semiconductor layer 12, dividing the interior region inside exterior trench 16 into two separate regions, each of which includes a plurality of interior trenches 14. Interior trenches 14, exterior trench 16 and middle dividing trench 136 are lined with dielectric material 18, such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon. Interior trenches 14 are formed in a pattern of vertical trench legs. In the pattern shown, the vertical legs of interior trenches 14 are separated from one another by interior gap distance GI. Interior trenches 14 have a trench width WT, and interior trenches 14 are spaced from exterior trench 16 by gap distance GE.
  • In an exemplary embodiment, gap distance GI may be about 2.0 μm, trench width WT may be about 1.4 μm, and gap distance GE may be about 2 μm.
  • FIG. 14 is a top plan view of MOSFET device 140 formed as a trench semiconductor device according to another embodiment of the present invention. MOSFET device 140 includes semiconductor layer 12, a plurality of interior trenches 14 formed in semiconductor layer 12, and exterior trench 16 formed in semiconductor layer 12. Interior trenches 14 and exterior trench 16 are lined with dielectric material 18, such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon. Interior trenches 14 are formed in an offset grid pattern enclosed by exterior trench 16, as shown in FIG. 14. In the grid pattern, the vertical legs of interior trenches 14 are separated from one another by interior gap distance GI, as are adjacent horizontal legs of interior trenches 14. Each leg of interior trenches 14 has a trench width WT, and interior trenches 14 are spaced from exterior trench 16 by gap distance GE.
  • In an exemplary embodiment, gap distance GI may be about 4.5 μm, trench width WT may be about 1.4 μm, and gap distance GE may be about 2 μm.
  • FIG. 15 is a top plan view of MOSFET device 150 formed as a trench semiconductor device according to another embodiment of the present invention. MOSFET device 150 includes semiconductor layer 12, a plurality of interior trenches 14 formed in semiconductor layer 12, and exterior trench 16 formed in semiconductor layer 12. Interior trenches 14 and exterior trench 16 are lined with dielectric material 18, such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon. Interior trenches 14 are formed in a honeycomb pattern enclosed by exterior trench 16, as shown in FIG. 15. In the honeycomb pattern, adjacent vertical legs of interior trenches 14 are separated from one another by interior gap distance GI. Each leg of interior trenches 14 has a trench width WT, and interior trenches 14 are spaced from exterior trench 16 by gap distance GE.
  • In an exemplary embodiment, trench width WT may be about 1.4 μm, and gap distance GE may be about 2 μm.
  • FIG. 16 is a top plan view of MOSFET device 160 formed as a trench semiconductor device according to another embodiment of the present invention. MOSFET device 160 includes semiconductor layer 12, a plurality of interior trenches 14 formed in semiconductor layer 12, and exterior trench 16 formed in semiconductor layer 12. Interior trenches 14 and exterior trench 16 are lined with dielectric material 18, such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon. Interior trenches 14 are formed in a geometric trench pattern formed of six sided polygons and eight sided polygons enclosed by exterior trench 16, as shown in FIG. 16. In the geometric trench pattern, adjacent vertical legs of interior trenches 14 are separated from one another by interior gap distance GI. Each leg of interior trenches 14 has a trench width WT, and interior trenches 14 are spaced from exterior trench 16 by gap distance GE.
  • In an exemplary embodiment, trench width WT may be about 1.4 μm, and gap distance GE may be about 2 μm.
  • The embodiments of the present invention disclosed herein include geometric features that can be mixed and matched with any other disclosed embodiments. For example, the segmented outer trench 16 shown in FIG. 7 may be used with the snake trench pattern shown in FIG. 1A in an alternative embodiment. Other features may also be combined and modified to form additional alternative embodiments and configurations.
  • In many of the embodiments disclosed herein, modifications of the dimensions of trenches or other features, as well as of gaps between trenches or other features, are able to be modified in order to adjust the performance of the device, such as the breakdown voltage of the device. Examples of such modifications and the resulting performance adjustments are discussed specifically with respect to the embodiments of FIGS. 7 and 8, and modifications to others of the disclosed embodiments will also result in performance adjustments that may be selected and optimized for a particular application.
  • While the invention has been described with reference to an exemplary embodiment(s), it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment(s) disclosed, but that the invention will include all embodiments falling within the scope of the description herein.

Claims (14)

1. A trench semiconductor device comprising:
a layer of semiconductor material;
an exterior trench pattern formed in the layer of semiconductor material, the exterior trench pattern including a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material; and
an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern, the interior trench pattern including a plurality of first interior trench portions and a plurality of second interior trench portions that are each lined with dielectric material and filled with conductive material, the plurality of first interior trench portions being arranged perpendicular to the plurality of second interior trench portions with each of the plurality of first interior trench portions being connected to at least one of the plurality of second interior trench portions.
2. The trench semiconductor device of claim 1, wherein the plurality of first interior trench portions and the plurality of second interior trench portions are connected to each other to form a snake pattern.
3. The trench semiconductor device of claim 2, further comprising a plurality of intermediate trench portions between the exterior trench pattern and the interior trench pattern, the plurality of intermediate trench portions at least partially surrounding the interior trench pattern.
4. The trench semiconductor device of claim 2, wherein the exterior trench pattern is formed with the plurality of exterior trench portions separated from one another by gaps therebetween.
5. The trench semiconductor device of claim 2, wherein the exterior trench pattern is formed with at least one notch feature located adjacent to openings between legs of the snake pattern formed by the plurality of first interior trench portions and the plurality of second interior trench portions.
6. The trench semiconductor device of claim 1, wherein the plurality of first interior trench portions and the plurality of second interior trench portions are connected to each other to form a plurality of separated closed rectangles.
7. The trench semiconductor device of claim 1, wherein the plurality of first interior trench portions and the plurality of second interior trench portions are connected to each other to form a pattern having an outer frame and a plurality of vertical trench legs connecting top and bottom horizontal segments of the outer frame.
8. The trench semiconductor device of claim 1, wherein the plurality of first interior trench portions and the plurality of second interior trench portions are connected to each other to form a grid pattern.
9. The trench semiconductor device of claim 8, wherein the plurality of first interior trench portions and the plurality of second interior trench portions are connected to each other to form the grid pattern with the plurality of first interior trench portions including extensions that extend beyond an outer rectangular perimeter of the grid pattern.
10. The trench semiconductor device of claim 8, wherein the plurality of first interior trench portions and the plurality of second interior trench portions are connected to each other to form the grid pattern with an offset such successive columns of horizontal legs of the grid pattern formed by the plurality of second interior trench portions connecting adjacent vertical legs of the grid pattern formed by the plurality of first interior trench portions are offset from one another.
11. A trench semiconductor device comprising:
a layer of semiconductor material;
an exterior trench pattern formed in the layer of semiconductor material, the exterior trench pattern including a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material; and
an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern, the interior trench pattern including a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material, arranged at angles to each other and connected to each other to form a plurality of six sided polygons.
12. The trench semiconductor device of claim 11, wherein the six sided polygons are arranged in a honeycomb pattern.
13. The trench semiconductor device of claim 11, wherein the plurality of interior trench portions are arranged at angles to each other and connected to each other to form a geometric pattern including plurality of six sided polygons and at least one eight sided polygon.
14. A trench semiconductor device comprising:
a layer of semiconductor material;
an exterior trench pattern formed in the layer of semiconductor material, the exterior trench pattern including a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, the plurality of exterior trench portions being formed as a plurality of separated exterior trench segments; and
an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern, the interior trench pattern including a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material, the plurality of interior trench portions being formed as a plurality of parallel vertical trench legs.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180175146A1 (en) * 2015-02-23 2018-06-21 Polar Semiconductor, Llc Trench semiconductor device layout configurations
CN110574154A (en) * 2017-05-16 2019-12-13 株式会社村田制作所 Capacitor and method of making the same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4113623A1 (en) * 2021-07-01 2023-01-04 Infineon Technologies Austria AG Transistor device

Citations (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4796070A (en) * 1987-01-15 1989-01-03 General Electric Company Lateral charge control semiconductor device and method of fabrication
US4974059A (en) * 1982-12-21 1990-11-27 International Rectifier Corporation Semiconductor high-power mosfet device
US5597765A (en) * 1995-01-10 1997-01-28 Siliconix Incorporated Method for making termination structure for power MOSFET
US5977609A (en) * 1997-03-26 1999-11-02 Telefonaktiebolaget Lm Ericsson Method and apparatus for insulating material using trenches
US6057558A (en) * 1997-03-05 2000-05-02 Denson Corporation Silicon carbide semiconductor device and manufacturing method thereof
US6060747A (en) * 1997-09-30 2000-05-09 Kabushiki Kaisha Toshiba Semiconductor device
US6104054A (en) * 1998-05-13 2000-08-15 Texas Instruments Incorporated Space-efficient layout method to reduce the effect of substrate capacitance in dielectrically isolated process technologies
US20020071086A1 (en) * 2000-12-13 2002-06-13 Lg. Philips Lcd Co., Ltd. Liquid crystal display panel and method for manufacturing the same
US6429481B1 (en) * 1997-11-14 2002-08-06 Fairchild Semiconductor Corporation Field effect transistor and method of its manufacture
US20020167071A1 (en) * 2001-05-10 2002-11-14 Mu-Chun Wang Guard ring for protecting integrated circuits
US6683363B2 (en) * 2001-07-03 2004-01-27 Fairchild Semiconductor Corporation Trench structure for semiconductor devices
US20040021195A1 (en) * 2002-06-28 2004-02-05 Shindengen Electric Manufacturing Co., Ltd. Semiconductor device
US20050006700A1 (en) * 2003-06-11 2005-01-13 International Rectifier Corporation Low on resistance power MOSFET with variably spaced trenches and offset contacts
US20050032287A1 (en) * 2003-08-04 2005-02-10 Renesas Technology Corp. Semiconductor device and a method of manufacturing the same
US20050161735A1 (en) * 2002-08-22 2005-07-28 Denso Corporation Method of producing a semiconductor device
US20050167742A1 (en) * 2001-01-30 2005-08-04 Fairchild Semiconductor Corp. Power semiconductor devices and methods of manufacture
US20060044487A1 (en) * 2004-09-01 2006-03-02 Sharp Kabushiki Kaisha Active-matrix substrate and display device including the substrate
US20060214221A1 (en) * 2003-05-20 2006-09-28 Ashok Challa Power semiconductor devices and methods of manufacture
US20060267044A1 (en) * 2005-05-24 2006-11-30 Yang Robert K DMOS transistor with a poly-filled deep trench for improved performance
US20090230561A1 (en) * 2008-03-12 2009-09-17 Infineon Technologies Ag Semiconductor device
US7595542B2 (en) * 2006-03-13 2009-09-29 Fairchild Semiconductor Corporation Periphery design for charge balance power devices
US20100155879A1 (en) * 2008-03-12 2010-06-24 Infineon Technologies Ag Semiconductor device
US7772673B1 (en) * 2007-03-16 2010-08-10 Newport Fab, Llc Deep trench isolation and method for forming same
US20100224932A1 (en) * 2006-03-08 2010-09-09 Hidefumi Takaya Insulated Gate-Type Semiconductor Device and Manufacturing Method Thereof
US7795137B2 (en) * 2005-08-26 2010-09-14 Hitachi, Ltd. Manufacturing method of semiconductor device
US8084865B2 (en) * 2007-04-30 2011-12-27 Infineon Technologies Ag Anchoring structure and intermeshing structure
US8138575B2 (en) * 2006-03-22 2012-03-20 Infineon Technologies Ag Integrated circuit including a reverse current complex
US8148749B2 (en) * 2009-02-19 2012-04-03 Fairchild Semiconductor Corporation Trench-shielded semiconductor device
US8174067B2 (en) * 2008-12-08 2012-05-08 Fairchild Semiconductor Corporation Trench-based power semiconductor devices with increased breakdown voltage characteristics
US8304829B2 (en) * 2008-12-08 2012-11-06 Fairchild Semiconductor Corporation Trench-based power semiconductor devices with increased breakdown voltage characteristics
US8330247B2 (en) * 2007-02-20 2012-12-11 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Semiconductor arrangement with trench capacitor and method for production thereof
US8354730B2 (en) * 2005-08-26 2013-01-15 Hitachi, Ltd. Manufacturing method of semiconductor device and semiconductor device
US20130181252A1 (en) * 2010-09-30 2013-07-18 Hiroomi Eguchi Semiconductor device
US20130193502A1 (en) * 2012-02-01 2013-08-01 Texas Instruments Incorporated Medium voltage mosfet device
US20140035102A1 (en) * 2012-07-31 2014-02-06 I/O Semiconductor Inc. Power device integration on a common substrate
US20140035032A1 (en) * 2012-07-31 2014-02-06 Io Semiconductor Inc. Power device integration on a common substrate
US20140035047A1 (en) * 2012-07-31 2014-02-06 I/O Semiconductor Inc. Power device integration on a common substrate
US20140034999A1 (en) * 2012-07-31 2014-02-06 Azure Silicon LLC Power device integration on a common substrate
US8722502B2 (en) * 2007-03-30 2014-05-13 Shiro Uchiyama Chip-stacked semiconductor device and manufacturing method thereof
US20140284701A1 (en) * 2012-07-31 2014-09-25 Azure Silicon LLC Power device integration on a common substrate
US8872278B2 (en) * 2011-10-25 2014-10-28 Fairchild Semiconductor Corporation Integrated gate runner and field implant termination for trench devices
US20140361349A1 (en) * 2013-06-06 2014-12-11 United Silicon Carbide, Inc. Trench shield connected jfet
US8928077B2 (en) * 2007-09-21 2015-01-06 Fairchild Semiconductor Corporation Superjunction structures for power devices
US9397213B2 (en) * 2014-08-29 2016-07-19 Freescale Semiconductor, Inc. Trench gate FET with self-aligned source contact

Family Cites Families (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4868631A (en) * 1985-11-18 1989-09-19 Texas Instruments Incorporated Bipolar transistor with shallow junctions and capable of high packing density
US5104816A (en) * 1986-01-30 1992-04-14 Texas Instruments Incorporated Polysilicon self-aligned bipolar device including trench isolation and process of manufacturing same
US5622890A (en) * 1994-07-22 1997-04-22 Harris Corporation Method of making contact regions for narrow trenches in semiconductor devices
US7462910B1 (en) * 1998-10-14 2008-12-09 International Rectifier Corporation P-channel trench MOSFET structure
US5998833A (en) 1998-10-26 1999-12-07 North Carolina State University Power semiconductor devices having improved high frequency switching and breakdown characteristics
JP3344381B2 (en) * 1999-08-23 2002-11-11 日本電気株式会社 Semiconductor device and manufacturing method thereof
US6838735B1 (en) * 2000-02-24 2005-01-04 International Rectifier Corporation Trench FET with non overlapping poly and remote contact therefor
US6392290B1 (en) * 2000-04-07 2002-05-21 Siliconix Incorporated Vertical structure for semiconductor wafer-level chip scale packages
US6822288B2 (en) * 2001-11-20 2004-11-23 General Semiconductor, Inc. Trench MOSFET device with polycrystalline silicon source contact structure
DE10212144B4 (en) 2002-03-19 2005-10-06 Infineon Technologies Ag Transistor arrangement having a structure for electrically contacting electrodes of a trench transistor cell
TWI248136B (en) 2002-03-19 2006-01-21 Infineon Technologies Ag Method for fabricating a transistor arrangement having trench transistor cells having a field electrode
US6838722B2 (en) * 2002-03-22 2005-01-04 Siliconix Incorporated Structures of and methods of fabricating trench-gated MIS devices
JP4274771B2 (en) * 2002-10-04 2009-06-10 新電元工業株式会社 Semiconductor device
EP1557888A4 (en) * 2002-10-04 2009-11-04 Shindengen Electric Mfg SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE DEVICE
DE10353387B4 (en) * 2003-11-14 2008-07-24 Infineon Technologies Ag Method for producing a power transistor arrangement and power transistor arrangement
US7352036B2 (en) * 2004-08-03 2008-04-01 Fairchild Semiconductor Corporation Semiconductor power device having a top-side drain using a sinker trench
JP2006237455A (en) * 2005-02-28 2006-09-07 Toshiba Corp Semiconductor device and manufacturing method thereof
JP2006237448A (en) * 2005-02-28 2006-09-07 Nec Electronics Corp Method of manufacturing complementary field effect transistor
JP4577687B2 (en) * 2005-03-17 2010-11-10 エルピーダメモリ株式会社 Semiconductor device
JP4890780B2 (en) * 2005-04-11 2012-03-07 ルネサスエレクトロニクス株式会社 Field effect transistor
US8084815B2 (en) * 2005-06-29 2011-12-27 Fairchild Korea Semiconductor Ltd. Superjunction semiconductor device
KR20070015309A (en) * 2005-07-30 2007-02-02 페어차일드코리아반도체 주식회사 High voltage semiconductor device
US9252251B2 (en) * 2006-08-03 2016-02-02 Infineon Technologies Austria Ag Semiconductor component with a space saving edge structure
JP2008277352A (en) * 2007-04-25 2008-11-13 Matsushita Electric Ind Co Ltd Semiconductor device
US7842969B2 (en) * 2008-07-10 2010-11-30 Semiconductor Components Industries, Llc Low clamp voltage ESD device and method therefor
US20120273916A1 (en) * 2011-04-27 2012-11-01 Yedinak Joseph A Superjunction Structures for Power Devices and Methods of Manufacture
JP4945594B2 (en) * 2009-03-16 2012-06-06 株式会社東芝 Power semiconductor device
US20160372542A9 (en) * 2011-07-19 2016-12-22 Yeeheng Lee Termination of high voltage (hv) devices with new configurations and methods
US8680645B2 (en) * 2011-08-09 2014-03-25 Infineon Technologies Austria Ag Semiconductor device and a method for forming a semiconductor device
CN102627252B (en) * 2012-04-19 2014-12-10 西北工业大学 Novel trench isolation groove for filling trench
CN103426738B (en) * 2012-05-17 2018-05-18 恩智浦美国有限公司 Trench semiconductor device and its manufacturing method with edge termination structures
JP5812029B2 (en) * 2012-06-13 2015-11-11 株式会社デンソー Silicon carbide semiconductor device and manufacturing method thereof
US8994117B2 (en) * 2012-12-18 2015-03-31 International Business Machines Corporation Moat construction to reduce noise coupling to a quiet supply
JP6160477B2 (en) * 2013-12-25 2017-07-12 トヨタ自動車株式会社 Semiconductor device
US9929140B2 (en) * 2014-05-22 2018-03-27 Texas Instruments Incorporated Isolation structure for IC with EPI regions sharing the same tank
US9252263B1 (en) * 2014-07-31 2016-02-02 Infineon Technologies Austria Ag Multiple semiconductor device trenches per cell pitch
CN104183634B (en) * 2014-09-16 2017-07-21 株洲南车时代电气股份有限公司 A kind of trench gate igbt chip
JP6478316B2 (en) * 2014-11-10 2019-03-06 ローム株式会社 Semiconductor device having trench gate structure and manufacturing method thereof
US9673084B2 (en) * 2014-12-04 2017-06-06 Globalfoundries Singapore Pte. Ltd. Isolation scheme for high voltage device
US9496250B2 (en) * 2014-12-08 2016-11-15 Globalfoundries Inc. Tunable scaling of current gain in bipolar junction transistors
JP2016152335A (en) * 2015-02-18 2016-08-22 株式会社デンソー Semiconductor device
US20160247879A1 (en) * 2015-02-23 2016-08-25 Polar Semiconductor, Llc Trench semiconductor device layout configurations
US9391135B1 (en) * 2015-03-23 2016-07-12 Semiconductor Components Industries, Llc Semiconductor device
US9680003B2 (en) * 2015-03-27 2017-06-13 Nxp Usa, Inc. Trench MOSFET shield poly contact
US11031281B2 (en) * 2019-06-04 2021-06-08 Globalfoundries Singapore Pte. Ltd. Semiconductor devices and methods of fabricating a deep trench isolation structure

Patent Citations (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4974059A (en) * 1982-12-21 1990-11-27 International Rectifier Corporation Semiconductor high-power mosfet device
US4796070A (en) * 1987-01-15 1989-01-03 General Electric Company Lateral charge control semiconductor device and method of fabrication
US5597765A (en) * 1995-01-10 1997-01-28 Siliconix Incorporated Method for making termination structure for power MOSFET
US6057558A (en) * 1997-03-05 2000-05-02 Denson Corporation Silicon carbide semiconductor device and manufacturing method thereof
US5977609A (en) * 1997-03-26 1999-11-02 Telefonaktiebolaget Lm Ericsson Method and apparatus for insulating material using trenches
US6060747A (en) * 1997-09-30 2000-05-09 Kabushiki Kaisha Toshiba Semiconductor device
US6429481B1 (en) * 1997-11-14 2002-08-06 Fairchild Semiconductor Corporation Field effect transistor and method of its manufacture
US6104054A (en) * 1998-05-13 2000-08-15 Texas Instruments Incorporated Space-efficient layout method to reduce the effect of substrate capacitance in dielectrically isolated process technologies
US20020071086A1 (en) * 2000-12-13 2002-06-13 Lg. Philips Lcd Co., Ltd. Liquid crystal display panel and method for manufacturing the same
US20050167742A1 (en) * 2001-01-30 2005-08-04 Fairchild Semiconductor Corp. Power semiconductor devices and methods of manufacture
US20020167071A1 (en) * 2001-05-10 2002-11-14 Mu-Chun Wang Guard ring for protecting integrated circuits
US6683363B2 (en) * 2001-07-03 2004-01-27 Fairchild Semiconductor Corporation Trench structure for semiconductor devices
US20040021195A1 (en) * 2002-06-28 2004-02-05 Shindengen Electric Manufacturing Co., Ltd. Semiconductor device
US20050161735A1 (en) * 2002-08-22 2005-07-28 Denso Corporation Method of producing a semiconductor device
US7348244B2 (en) * 2002-08-22 2008-03-25 Denso Corporation Method of producing a semiconductor device
US7652326B2 (en) * 2003-05-20 2010-01-26 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
US8786045B2 (en) * 2003-05-20 2014-07-22 Fairchild Semiconductor Corporation Power semiconductor devices having termination structures
US20060214221A1 (en) * 2003-05-20 2006-09-28 Ashok Challa Power semiconductor devices and methods of manufacture
US20050006700A1 (en) * 2003-06-11 2005-01-13 International Rectifier Corporation Low on resistance power MOSFET with variably spaced trenches and offset contacts
US20050032287A1 (en) * 2003-08-04 2005-02-10 Renesas Technology Corp. Semiconductor device and a method of manufacturing the same
US20060044487A1 (en) * 2004-09-01 2006-03-02 Sharp Kabushiki Kaisha Active-matrix substrate and display device including the substrate
US20060267044A1 (en) * 2005-05-24 2006-11-30 Yang Robert K DMOS transistor with a poly-filled deep trench for improved performance
US7535057B2 (en) * 2005-05-24 2009-05-19 Robert Kuo-Chang Yang DMOS transistor with a poly-filled deep trench for improved performance
US8354730B2 (en) * 2005-08-26 2013-01-15 Hitachi, Ltd. Manufacturing method of semiconductor device and semiconductor device
US7795137B2 (en) * 2005-08-26 2010-09-14 Hitachi, Ltd. Manufacturing method of semiconductor device
US7999312B2 (en) * 2006-03-08 2011-08-16 Toyota Jidosha Kabushiki Kaisha Insulated gate-type semiconductor device having a low concentration diffusion region
US20100224932A1 (en) * 2006-03-08 2010-09-09 Hidefumi Takaya Insulated Gate-Type Semiconductor Device and Manufacturing Method Thereof
US7595542B2 (en) * 2006-03-13 2009-09-29 Fairchild Semiconductor Corporation Periphery design for charge balance power devices
US8138575B2 (en) * 2006-03-22 2012-03-20 Infineon Technologies Ag Integrated circuit including a reverse current complex
US8330247B2 (en) * 2007-02-20 2012-12-11 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Semiconductor arrangement with trench capacitor and method for production thereof
US7772673B1 (en) * 2007-03-16 2010-08-10 Newport Fab, Llc Deep trench isolation and method for forming same
US8722502B2 (en) * 2007-03-30 2014-05-13 Shiro Uchiyama Chip-stacked semiconductor device and manufacturing method thereof
US8084865B2 (en) * 2007-04-30 2011-12-27 Infineon Technologies Ag Anchoring structure and intermeshing structure
US8928077B2 (en) * 2007-09-21 2015-01-06 Fairchild Semiconductor Corporation Superjunction structures for power devices
US20090230561A1 (en) * 2008-03-12 2009-09-17 Infineon Technologies Ag Semiconductor device
US20100155879A1 (en) * 2008-03-12 2010-06-24 Infineon Technologies Ag Semiconductor device
US8304829B2 (en) * 2008-12-08 2012-11-06 Fairchild Semiconductor Corporation Trench-based power semiconductor devices with increased breakdown voltage characteristics
US8174067B2 (en) * 2008-12-08 2012-05-08 Fairchild Semiconductor Corporation Trench-based power semiconductor devices with increased breakdown voltage characteristics
US8148749B2 (en) * 2009-02-19 2012-04-03 Fairchild Semiconductor Corporation Trench-shielded semiconductor device
US20130181252A1 (en) * 2010-09-30 2013-07-18 Hiroomi Eguchi Semiconductor device
US9048107B2 (en) * 2010-09-30 2015-06-02 Toyota Jidosha Kabushiki Kaisha Semiconductor device
US8872278B2 (en) * 2011-10-25 2014-10-28 Fairchild Semiconductor Corporation Integrated gate runner and field implant termination for trench devices
US20160240653A1 (en) * 2012-02-01 2016-08-18 Texas Instruments Incorporated Medium High Voltage MOSFET Device
US9356133B2 (en) * 2012-02-01 2016-05-31 Texas Instruments Incorporated Medium voltage MOSFET device
US20160240667A1 (en) * 2012-02-01 2016-08-18 Texas Instruments Incorporated Medium High Voltage MOSFET Device
US20130193502A1 (en) * 2012-02-01 2013-08-01 Texas Instruments Incorporated Medium voltage mosfet device
US20140035047A1 (en) * 2012-07-31 2014-02-06 I/O Semiconductor Inc. Power device integration on a common substrate
US20140284701A1 (en) * 2012-07-31 2014-09-25 Azure Silicon LLC Power device integration on a common substrate
US8674440B2 (en) * 2012-07-31 2014-03-18 Io Semiconductor Inc. Power device integration on a common substrate
US20140034999A1 (en) * 2012-07-31 2014-02-06 Azure Silicon LLC Power device integration on a common substrate
US20140035032A1 (en) * 2012-07-31 2014-02-06 Io Semiconductor Inc. Power device integration on a common substrate
US20140035102A1 (en) * 2012-07-31 2014-02-06 I/O Semiconductor Inc. Power device integration on a common substrate
US20160343802A1 (en) * 2012-07-31 2016-11-24 Silanna Asia Pte Ltd Power device integration on a common substrate
US20140361349A1 (en) * 2013-06-06 2014-12-11 United Silicon Carbide, Inc. Trench shield connected jfet
US9087911B2 (en) * 2013-06-06 2015-07-21 United Silicon Carbide, Inc. Trench shield connected JFET
US9397213B2 (en) * 2014-08-29 2016-07-19 Freescale Semiconductor, Inc. Trench gate FET with self-aligned source contact

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180175146A1 (en) * 2015-02-23 2018-06-21 Polar Semiconductor, Llc Trench semiconductor device layout configurations
US10580861B2 (en) * 2015-02-23 2020-03-03 Polar Semiconductor, Llc Trench semiconductor device layout configurations
US11245006B2 (en) * 2015-02-23 2022-02-08 Polar Semiconductor, Llc Trench semiconductor device layout configurations
CN110574154A (en) * 2017-05-16 2019-12-13 株式会社村田制作所 Capacitor and method of making the same
US11145711B2 (en) * 2017-05-16 2021-10-12 Murata Manufacturing Co., Ltd. Capacitor and method for manufacturing capacitor

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