US20140264507A1

US20140264507A1 - Fluorine Passivation in CMOS Image Sensors

Info

Publication number: US20140264507A1
Application number: US14/137,866
Authority: US
Inventors: Mankoo Lee; Sergey Barabash; Tony P. Chiang; Dipankar Pramanik
Original assignee: Intermolecular Inc
Current assignee: Intermolecular Inc
Priority date: 2013-03-13
Filing date: 2013-12-20
Publication date: 2014-09-18
Also published as: US8987143B2; US20150255332A1; US20140273525A1; US9076641B2; US20140273493A1; WO2014160467A1; US20140264825A1; US20140273404A1; WO2014160460A1; US20140264281A1

Abstract

CMOS imaging sensors having fluorine-passivated structures to reduce dark current are disclosed together with methods of making thereof. The CIS comprises an array of pixels on a substrate, each pixel comprising a pinned photodiode, an isolation trench adjacent to the pinned photodiode, and a plurality of transistors. Methods of preparing a CIS comprise providing a source of fluorine (F) atoms, and annealing in the presence of the source of F atoms. After the annealing, at least one silicon-containing surface or region in the CIS comprises Si—F bonds and is fluorine passivated.

Description

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from U.S. Provisional Patent Application No. 61/779,740, filed on Mar. 13, 2013, which is incorporated by reference herein in its entirety for all purposes.

FIELD OF THE INVENTION

One or more embodiments of the present invention relate to CMOS image sensors and methods of making thereof.

BACKGROUND

As the pixel size is scaled for higher image resolution and/or higher density of integration in advanced CMOS image sensor (CIS) technology, dark current reduction is one of the main problems that limits signal to noise ratio (SNR). The dark current comes from several sources, including minority carrier diffusion current in the photodiode, surface recombination centers and/or traps (N_st) at the trench sidewall liner and the top p-layer interfaces in contact with bulk silicon, the transfer gate interfacial SiO₂/Si interface (D_it), and bulk metallic contamination sites (Cu, Mo, Au, etc.) in the silicon within the space charge region (SCR) that exists in an electric field.
FIG. 1A shows a typical schematic of a four-transistor CIS pixel and FIG. 1B shows a sample pixel layout. The transistor (or gate input) labels provide controls for transfer (TX), reset (RST), select, and source follower (SF). A large area pinned photodiode (PPD) 102 can be seen with an area much larger than that of the transfer transistor 104.
Four important dark current sources are identified in the cross section of a single pixel shown in FIG. 2: a space charge region 202 (“region 1”) in the PPD, the top surface 204 (“regions 2”) of the PPD, the sidewall 206 (“regions 3”) of the isolation trench between pixels, and the interfacial oxide 208 (“region 4”) at each of the four transistor gates. Only the transfer transistor is shown in FIG. 2. Note that FIG. 2 shows both deep trench isolation (DTI) and shallow trench isolation (STI), although typically only one option is used. The notation “PSTI” in FIG. 2 indicates that the STI is implemented in the illustrated embodiment with polycrystalline silicon.
Evidence for the top diode surface as a source of dark current can be found in Carrère et al. (“New Mechanism of Plasma Induced Damage on CMOS Image Sensor: Analysis and Process Optimization,” Solid State Electronics, 65-66, 51-56, 2011). The “damage” was found to be caused by a plasma used to etch two cavities in the dielectric above the pixel diode using reactive ion etching (RIE). The damage was reduced by optimizing the RIE process and increasing the p-doping level above the diode.
Hydrogen (H₂) passivation is commonly used to reduce the dark current, although the reduction may be insufficient as the pixel size is reduced. The goal of any passivation process is to reduce dangling bonds at the interface between bulk silicon and an interfacial SiO₂layer. Both H₂and D₂(deuterium) have been used (Kwon et al., “The Effects of Deuterium Annealing on the Reduction of Dark Currents in the CMOS APS,” IEEE Trans. on Electron Devices, 51, 1346-49, 2004). H₂appears to give better performance, although it is not clear why.
Fluorine can also be used for passivation. It is well known that the bonding energy for a single Si—F bond can be about 5.8 eV, which is much larger than that for a single Si—H bond (3.6 eV). Fluorine has previously been applied using an ion implantation process. However, the ion implantation process can create additional defects requiring subsequent thermal annealing steps at the high temperature to reduce the additional defects.
Co-pending U.S. patent application Ser. No. 13/728,957, filed Dec. 27, 2012, and incorporated herein by reference herein, discloses a method of fluorine passivation where the F atoms are introduced in a donor material such as WSi_x:F (i.e., fluorine doped tungsten silicide) deposited as a nearby layer. The F atoms are then allowed to migrate to the Si/SiO₂interface during a subsequent annealing step.
Wu et al. (“Fluorinated HfO₂Gate Dielectrics Engineering for CMOS by pre- and post-CF₄Plasma Passivation,” IEEE, Electron Devices Meeting 2008, 1-4, doi: 10.1109/IEDM.2008.4796706) disclose a method of using CF₄plasmas before and after the formation of the gate dielectric to passivate both the HfO₂/SiO₂interface and the SiO₂/Si interface in a CMOS transistor gate stack.
Hsieh et al. (“Improved performance and reliability for metal-oxide-semiconductor field-effect-transistor with fluorinated silicate glass passivation layer” Appl. Phys. Let. 96, 022905, 2010) disclose fluorine passivation of a HfO₂/SiON interface where the F atoms are introduced from a donor layer of fluorinated silicate glass (FSG) deposited by plasma-enhanced chemical vapor deposition (PECVD).

SUMMARY OF THE INVENTION

Embodiments of the present invention include fluorine-passivated CMOS imaging sensors (CIS) and methods of making a fluorine-passivated CIS. Fluorine (F) atoms are introduced to passivate some or all of the four regions of a CIS identified as sources of dark current in FIG. 2 and described in the Background section above. Methods of fluorine-passivating a CMOS imaging sensor (CIS) are disclosed. An array of pixels is formed on a substrate, each pixel comprising a pinned photodiode, an isolation trench adjacent to the pinned photodiode, and a plurality of transistors. The method further comprises performing an annealing step in the presence of a source of fluorine (F) atoms. The annealing conditions are such that F atoms form covalent bonds with dangling Si (or Ge) atoms in at least one of the pinned photodiode, the isolation trench, or one of the plurality of transistors. After the annealing, at least one surface or region in the CIS is fluorine-passivated.
In some embodiments, the source of F atoms can be a fluorine-containing gas in the annealing atmosphere; for example, the fluorine-containing gas can be F₂, NF₃, CF₄, or a fluoride of xenon, or the like. In some embodiments, the method further comprises depositing a fluorine-containing SiO₂layer by chemical vapor deposition (CVD), wherein the CVD atmosphere comprises a fluoride of xenon. The fluorine-containing SiO₂layer provides a source of F atoms.
In some embodiments, the fluorine-containing SiO₂layer is deposited in the isolation trench.
In some embodiments, the method further comprises depositing a layer of fluorinated silicate glass (FSG) on an area of the CIS. The FSG provides a source of F atoms. In some embodiments, the method further comprises depositing polycrystalline silicon doped with BF₃in the isolation trench. The doped polycrystalline silicon provides a source of F atoms. In some embodiments, the method further comprises forming a WSi_x:F layer in at least one of the plurality of transistors. The WSi_x:F layer provides a source of F atoms.
Embodiments of CMOS imaging sensors include fluorine-passivated CIS made using the methods described above. The CIS comprise a pinned photodiode, an isolation trench, and a plurality of transistors, wherein at least one of the pinned photodiode, isolation trench, or one of the plurality of transistors comprises fluorine. The fluorine can be in the form of Si—F bonds (or Ge—F bonds) to passivate Si containing materials in the CIS; for example, dangling Si— bonds in polycrystalline Si can be passivated using F atoms, and dangling Si— bonds in SiO₂or silicate glass can be passivated using F atoms. In particular, dangling Si— bonds present at or near Si—SiO₂interfaces or in the space charge region of the pinned photodiode can be passivated in order to reduce dark current in the CIS. In some embodiments, the fluorine passivates a space charge region in the pinned photodiode. In some embodiments, the fluorine passivates a surface of the pinned photodiode. In some embodiments, the fluorine passivates a layer on the sidewall of the isolation trench. In some embodiments, the fluorine passivates an interfacial layer of at least one of the plurality of transistors. In some embodiments, the interfacial layer is adjacent to a gate dielectric.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and B show a typical circuit and layout for one pixel of a CIS.

FIG. 2 shows the location of four important sources of dark current in a cross-sectional view of one pixel of a CIS

FIG. 3 shows a cross-sectional view of a CIS and the fluorine passivation conditions.

FIG. 4 shows a conventional CIS process flow and the fluorine passivation steps according to some embodiments of the invention.

DETAILED DESCRIPTION

It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of the present invention.
It must be noted that as used herein and in the claims, the singular forms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a layer” includes two or more layers, and so forth.
Where a range of values is provided, it is understood that each intervening value, to the tenth of the unit of the lower limit unless the context clearly dictates otherwise, between the upper and lower limits of that range, and any other stated or intervening value in that stated range, is encompassed within the invention. The upper and lower limits of these smaller ranges may independently be included in the smaller ranges, and are also encompassed within the invention, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included in the invention. Where the modifier “about” or “approximately” is used, the stated quantity can vary by up to 10%. Where the modifier “substantially equal to” is used, the two quantities may vary from each other by no more than 5%.
As used herein, the term “passivate” will be understood to refer to the process in which chemically and electrically active broken bonds are saturated, and therefore become less active, by reaction with a selected element. Typically, the selected element forms a stable bond with the chemically and electrically active broken bond.
The present Specification discloses fluorine-passivated CIS devices and methods of making fluorine-passivated CIS devices. Fluorine (F) atoms are introduced to passivate some or all of the four regions of a CIS identified as sources of dark current in FIG. 2 and described in the Background section above. Each region can be advantageously fluorine-passivated by one or more methods as described below. F atoms can provide more effective passivation than passivation with H atoms or D atoms. The fluorine in the fluorine-passivated CIS can be in the form of Si—F bonds or Ge—F bonds to passivate Si containing materials in the CIS; for example, dangling Si— bonds in polycrystalline Si can be passivated using F atoms, and dangling Si— bonds in SiO₂or silicate glass can be passivated using F atoms. In particular, dangling Si— bonds present at or near Si/SiO₂interfaces or in the space charge region of the pinned photodiode can be passivated in order to reduce dark current in the CIS. The fluorine passivation further serves to reduce metal migration and contamination of the pinned photodiode.
Embodiments of fluorine passivated CMOS imaging sensors comprise a pinned photodiode, an isolation trench, and a plurality of transistors, wherein at least one of the pinned photodiode, isolation trench, or one of the plurality of transistors comprises fluorine. In some embodiments, the pinned photodiode comprises fluorine in an amount sufficient to passivate a space charge region in the pinned photodiode. In some embodiments, the pinned photodiode comprises fluorine in an amount sufficient to passivate a surface of the pinned photodiode. In some embodiments, a layer on a sidewall of the isolation trench comprises fluorine in an amount sufficient to passivate a surface of the layer. In some embodiments, one or more of the plurality of transistors comprises an interfacial layer, the interfacial layer comprising fluorine in an amount sufficient to passivate a surface of the interfacial layer. In some embodiments, the transfer transistor comprises a fluorine-passivated interfacial layer. In some embodiments, the interfacial layer is adjacent to a gate dielectric.
Methods of fabricating a CMOS imaging sensor (CIS) comprise forming an array of pixels on a substrate, each pixel comprising a pinned photodiode, an isolation trench adjacent to the pinned photodiode, and a plurality of transistors, and performing at least one annealing step in the presence of a source of F atoms. The annealing is performed such that dangling Si or Ge atoms (i.e., Si or Ge without a full complement of covalent bonds to other Si or Ge or O atoms) react with F to form covalent bonds. In some embodiments, the annealing is performed such that F atoms can migrate to at least one of the pinned photodiode, the isolation trench, or one of the plurality of transistors. The fluorine can form Si—F bonds to passivate Si-containing materials in the CIS. After the annealing, at least one surface or region in the CIS is fluorine passivated.
In some embodiments, the source of F atoms can be a fluorine-containing gas in the annealing atmosphere, for example, the fluorine-containing gas can be F₂, NF₃, CF₄, or a fluoride of xenon, or the like. In some embodiments, the method further comprises depositing a fluorine-containing SiO₂layer by chemical vapor deposition (CVD), wherein the CVD atmosphere comprises a fluoride of xenon. The fluorine-containing SiO₂layer provides a source of F atoms. In some embodiments, the fluorine-containing SiO₂layer is deposited in the isolation trench.
In some embodiments, the method further comprises depositing a layer of fluorinated silicate glass (FSG) on an area of the CIS. The FSG provides a source of F atoms. In some embodiments, the method further comprises depositing polycrystalline silicon doped with BF₃in the isolation trench. The doped polycrystalline silicon provides a source of F atoms. In some embodiments, the method further comprises forming a WSi_x:F layer in at least one of the plurality of transistors. The WSi_x:F layer provides a source of F atoms. In some embodiments, the transfer transistor comprises a fluorine-passivated interfacial layer. In some embodiments, the interfacial layer is adjacent to a gate dielectric.
Referring again to FIG. 2, it can be seen that locations 202, 204, and 206 (regions 1-3) are all closely associated with the diode structure. Location 208 (region 4) is associated with the gate structure of the transfer transistor. Accordingly, passivation of region 4can be considered separately from passivation of regions 1-3. Alternative passivation techniques are described for each location. It is convenient to describe these techniques as they would be implemented in process-step order. These steps are further illustrated in the device illustration of FIG. 3 and the flowchart of FIG. 4.
In some embodiments, fluorine passivation of region 3 as indicated in FIG. 3 (process step 402 in FIG. 4) can be provided. Either deep trench isolation (DTI) or shallow trench isolation (STI) can be used to provide isolation between pixels to prevent charge leakage. DTI typically comprises an SiO₂“liner” applied to the silicon walls of the trench combined with a poly-crystalline silicon (“poly”) filler in the trench. Passivation is useful on both sides of the liner where there are Si/SiO₂interfaces. In some embodiments, the SiO₂liner can be formed using a chemical vapor deposition (CVD) process in the presence of a fluorine-containing gas such as XeF₆. It will be understood that while the use of XeF₆is exemplary herein, other fluorides of Xe such as XeF₂or XeF₄can be substituted. The SiO₂layer is effectively doped with F atoms during the deposition process. In some embodiments, the filler poly material can be doped with BF₃to further incorporate F atoms during the poly-fill processing step. Subsequent annealing can cause atomic migration to concentrate the F atoms at the Si/SiO₂interfaces where the fluorine atoms react with dangling Si atoms. Fluorine-containing gas and fluorine-doped poly can be used individually or in combination to passivate the SiO₂liner surfaces in DTI. Since STI typically does not include a poly-crystalline silicon filler, fluorine can be incorporated into an STI using a fluorine-containing gas during CVD deposition of SiO₂.
In some embodiments, fluorine passivation of region 4 as indicated in FIG. 3 (process step 404 in FIG. 4) can be provided by introducing fluorine to the interfacial SiO₂/Si interface in the transfer FET by adding NF₃to the atmosphere during the high density plasma (HDP) process used to form the sidewalls. In some embodiments, an added layer of WSi_x:F can be deposited in the FET, for example, as described in co-pending U.S. patent application Ser. No. 13/728,957. In some embodiments, XeF₆gas can be provided to region 4 in the time between oxide and nitride sidewall formation. This process can be shared with a similar process step for passivating region 2 (i.e., the same exposure to XeF₆gas can passivate both regions simultaneously).
In some embodiments, fluorine passivation of region 2 as indicated in FIG. 3 (process step 406 in FIG. 4) can be provided. Some passivation can be a byproduct of one of the two processes described above to passivate regions 3 and 4. In some embodiments, further passivation can be achieved by depositing fluorinated silicate glass (FSG) onto the silicide block oxide 210, which can be seen in FIG. 2 as the outer layer above the PPD and a nitride layer. FSG can be deposited by CVD by including a fluorine-containing precursor gas such as CF₄in the CVD atmosphere in addition to suitable silicate glass precursors. Subsequent annealing can allow migration of F atoms to the PPD surface. The passivation of the PPD surface can serve to reduce dark current directly, and can also provide a protective role against plasma damage during the subsequent RIE process that forms cavities in the silicide block oxide as described in Carrère et al. (op. cit.).
In some embodiments, fluorine passivation of region 1 as indicated in FIG. 3 (process step 408 in FIG. 2) and the space charge region in the bulk of the PPD (and incidentally to at least regions 2 and 3 as well) can be performed by a final post-metal-deposition annealing
(PMA). In some embodiments, this step can be performed after opening the cavities (212, 214 in FIG. 2) in the silicide block oxide. An atmosphere comprising a fluorine-containing gas such as F₂can be provided during the PMA for a time sufficient to allow F atoms to migrate through the oxide and nitride layers and into the depth of the PPD. Nitrides tend to be less permeable to F migration, and in some embodiments, the nitride layer comprises less than about 7 nm of TaN.
The amount of dark current reduction can be assessed using conventional methods. The dark current exhibited by conventionally prepared CIS is determined and compared to the dark current determined for embodiments of the fluorine-passivated CIS prepared as described above. Annealing times and temperatures to achieve fluorine reaction, migration and subsequent passivation to reduce one or more of the various sources of dark current in the CIS can be experimentally determined. Similarly, the fluorine-doping sources can be experimentally varied (concentration, precursor choice, processing conditions, etc.) for each of the fluorine doping methods described above in order to minimize the dark current from any particular dark current source in the CIS.
It will be understood that the descriptions of one or more embodiments of the present invention do not limit the various alternative, modified and equivalent embodiments which may be included within the spirit and scope of the present invention as defined by the appended claims. Furthermore, in the detailed description above, numerous specific details are set forth to provide an understanding of various embodiments of the present invention. However, one or more embodiments of the present invention may be practiced without these specific details. In other instances, well known methods, procedures, and components have not been described in detail so as not to unnecessarily obscure aspects of the present embodiments.

Claims

What is claimed is:

1. A method of fluorine passivating a CMOS imaging sensor (CIS), the method comprising

forming an array of pixels on a substrate, each pixel comprising a pinned photodiode, an isolation trench adjacent to the pinned photodiode, and a plurality of transistors, and

annealing the CIS in the presence of a source of fluorine (F) atoms.

2. The method of claim 1, wherein the source of F atoms is a fluorine-containing gas in the annealing atmosphere.

3. The method of claim 2, wherein the fluorine-containing gas is at least one of F₂, NF₃, CF₄, or a fluoride of xenon.

4. The method of claim 1, further comprising depositing an SiO₂layer by chemical vapor deposition (CVD),

wherein the CVD atmosphere comprises a fluoride of xenon, and

wherein the source of F atoms comprises the SiO₂layer.

5. The method of claim 4, wherein the depositing is performed in the isolation trench.

6. The method of claim 1, further comprising depositing a layer of fluorinated silicate glass (FSG) on an area of the CIS, wherein the source of F atoms comprises the layer of FSG.

7. The method of claim 1, further comprising depositing polycrystalline silicon doped with BF₃in the isolation trench, wherein the source of F atoms comprises the doped polycrystalline silicon.

8. The method of claim 1, further comprising forming a WSi_x:F layer in at least one of the plurality of transistors, wherein the source of F atoms comprises the WSi_x:F layer.

9. A fluorine-passivated CIS made by the method of claim 1.

10. A CIS comprising an array of pixels, each pixel comprising a pinned photodiode, an isolation trench, and a plurality of transistors, wherein at least one of the pinned photodiode, isolation trench, or one of the plurality of transistors comprises fluorine.

11. The CIS of claim 10, wherein the pinned photodiode comprises fluorine in an amount sufficient to passivate a space charge region in the pinned photodiode.

12. The CIS of claim 10, wherein the pinned photodiode comprises fluorine in an amount sufficient to passivate a surface of the pinned photodiode.

13. The CIS of claim 10, wherein a layer on a sidewall of the isolation trench comprises fluorine in an amount sufficient to passivate a surface of the layer.

14. The CIS of claim 10, wherein one or more of the plurality of transistors comprises an interfacial layer, the interfacial layer comprising fluorine in an amount sufficient to passivate a surface of the interfacial layer.

15. The CIS of claim 14, wherein the interfacial layer is adjacent to a gate dielectric.

16. The CIS of claim 10, wherein the CIS comprises fluorine in an amount sufficient to reduce the dark current of a pixel of the CIS relative to the dark current in a substantially identical pixel without fluorine.

17. The CIS of claim 10, wherein the fluorine passivates a silicon-containing surface or region by forming Si—F bonds.