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US20140056075A1 - Semiconductor memory device and method of operating the same - Google Patents

Semiconductor memory device and method of operating the same Download PDF

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Publication number
US20140056075A1
US20140056075A1 US13/718,784 US201213718784A US2014056075A1 US 20140056075 A1 US20140056075 A1 US 20140056075A1 US 201213718784 A US201213718784 A US 201213718784A US 2014056075 A1 US2014056075 A1 US 2014056075A1
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US
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Prior art keywords
memory cell
soft program
voltage
erase
threshold voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US13/718,784
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English (en)
Inventor
Yoon Soo JANG
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
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SK Hynix Inc
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Filing date
Publication date
Application filed by SK Hynix Inc filed Critical SK Hynix Inc
Assigned to SK Hynix Inc. reassignment SK Hynix Inc. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: JANG, YOON SOO
Publication of US20140056075A1 publication Critical patent/US20140056075A1/en
Priority to US14/683,720 priority Critical patent/US9564230B2/en
Abandoned legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells

Definitions

  • the present invention generally relates to a semiconductor memory device and method of operating the same, more particularly relates to a semiconductor memory device for performing a soft program operation after an erase operation is performed and method of operating the same.
  • a semiconductor memory device is a memory device for enabling to store and read data.
  • the semiconductor memory device is divided into a random access memory RAM and a read only memory ROM. Data stored in the RAM becomes lost if power is not supplied. This memory is referred to as a volatile memory. However, data stored in ROM is not lost though the power is not supplied. This memory is referred to as non-volatile memory.
  • a memory cell is programmed though an FN tunneling method when a program operation of the semiconductor memory device is performed.
  • high voltage is applied to a control gate of the memory cell in the program operation, electrons are charged in a floating gate of the memory cell.
  • threshold voltage of the memory cell varied according to amount of the electrons charged in the floating gate is detected, and read data is determined according to level of the detected threshold voltage.
  • An erase operation of the semiconductor memory cell may be performed in the unit of selected block.
  • the erase operation may be performed by applying a ground voltage, e.g. 0V to every word line included in the selected block and providing an erase voltage, e.g. 20V to a well of the block.
  • threshold voltage distribution of memory cells of which an erase operation is finished is generally wide, a time taken for the program operation performed after the erase operation may increase. For example, in case that a memory cell having lowest threshold voltage and a memory cell having greatest threshold voltage of the erased memory cells are programmed simultaneously, velocity difference of the program operation between two memory cells occurs.
  • a soft program operation is performed after the erase operation is finished.
  • FIG. 1 is a view illustrating circuit diagram of a string in a memory cell array of a semiconductor memory device.
  • FIG. 2 is a view illustrating a graph showing threshold voltage (i.e., Vt) distribution according to a conventional soft program operation (i.e., No).
  • Vt threshold voltage
  • a ground voltage is applied to bit lines BL, and a supply voltage is provided to a drain select line DSL and a ground voltage is applied to a source select line SSL under the condition that a source line SL may be connected to the supply voltage.
  • Every memory cell MC0 to MCn are soft-programmed simultaneously by applying simultaneously a soft program voltage to word lines WL ⁇ 0:n> so as to have one or more memory cells having threshold voltages higher than a soft program verification voltage SEV. That is, the soft program operation is performed by using a program operation through the FN tunneling method similar to common program operation method (i.e., FN PGM).
  • threshold voltage of every memory cell increases, and so effect of reducing width of the threshold voltage distribution is inadequate.
  • the threshold voltage distribution B of the memory cells for which the soft program operation is finished increases comparing to threshold voltage distribution A (where the target threshold voltage is indicated by HEV) of the memory cells before the soft program operation is not performed, but the width of the threshold voltage distribution does not reduce.
  • Various embodiments are provided for a semiconductor memory device for improving threshold voltage distribution of memory cells after an erase operation of the semiconductor memory device is performed and a method of operating the same.
  • a semiconductor memory device includes a memory cell array configured to include memory cells; a peripheral circuit configured to perform an erase operation and a soft program operation; and a control circuit configured to control the peripheral circuit so that the memory cells are programmed though a hot carrier injection HCI method when the soft program operation is performed.
  • a method of operating a semiconductor memory device includes increasing threshold voltage of memory cells corresponding to erase state by performing a soft program operation after an erase operation is finished, the soft program operation using a hot carrier injection HCI method; verifying through a soft program verifying operation whether or not the threshold voltage of the memory cells is higher than a target threshold voltage; and performing again the soft program operation and following step in case that it is determined that the threshold voltage of the memory cells is smaller than the target threshold voltage according to the soft program verifying operation.
  • a method of operating a semiconductor memory device includes erasing memory cells by applying an erase voltage to a semiconductor substrate on which a memory cell array including the memory cells is formed; performing an erase verifying operation about the memory cells; and performing a soft program operation through a hot carrier injection HCI method in case that it is determined that threshold voltage of the memory cells is smaller than a target threshold voltage according to the erase verifying operation.
  • a method of operating a semiconductor memory device includes applying a control voltage to a memory cell adjacent to a memory cell selected as a cell to be programmed in the direction of a drain select transistor, thereby turning off the adjacent memory cell; boosting a channel by providing a pass voltage to memory cells not selected except the adjacent memory cell and the selected memory cell; and injecting hot carrier in a semiconductor substrate on which the adjacent memory cell is formed to a electric charge storage layer of the selected memory cell according to electric field due to the pass voltage provided to the selected memory cell, thereby programming the selected memory cell.
  • threshold voltage distribution of memory cells after an erase operation of the semiconductor memory device may be performed may be improved.
  • FIG. 1 is a view illustrating circuit diagram of a string in a memory cell array of a semiconductor memory device
  • FIG. 2 is a view illustrating a graph showing threshold voltage distribution according to a conventional soft program operation
  • FIG. 3 is a block diagram illustrating a semiconductor memory device according to an embodiment
  • FIG. 4 is a view illustrating circuit diagram of a memory cell array in FIG. 3 ;
  • FIG. 5 is a flow chart illustrating a method of operating a semiconductor memory device according to an embodiment.
  • FIG. 6 is a view illustrating a graph showing change of threshold voltage distribution according to the soft program operation of the various embodiments.
  • FIG. 3 is a block diagram illustrating a semiconductor memory device according to an embodiment.
  • the semiconductor memory device 100 may include a memory cell array 110 , a page buffer 120 , an X decoder 130 , a voltage provision section 140 and a control circuit 150 .
  • the memory cell array 110 may include memory cells. Detailed constitution of the memory cell array will be described below.
  • the page buffer 120 may be connected to bit lines BL of the memory cell array 110 .
  • the page buffer 120 senses the potentials of the bit lines BL in response to page buffer control signals PB_signals outputted from the control circuit 150 when an erase verifying operation and a soft program verifying operation are performed, thereby verifying erase state of memory cells.
  • the X decoder 130 may apply operation voltages generated from the voltage provision section 140 to word lines WL, a drain select line DSL and a source select line SSL according to a row address RADD outputted from the control circuit 150 .
  • the voltage provision section 140 may generate an erase voltage Verase applied to a p-well of a semiconductor substrate on which the memory cell array 110 is formed in response to voltage provision section control signals VC_signals outputted from the control circuit 150 , and may generate a verifying voltage Vverify for the erase verifying operation and the soft program verifying operation. Additionally, the voltage provision section 140 may generate operation voltages including a control voltage Vsoc and a pass voltage Vpass so that memory cells of the memory cell array 110 are programmed through hot carrier injection in the soft program operation. The operation voltages for the soft program operation will be described below.
  • the control circuit 150 may output the control signals VC_signals so that the voltage provision section 140 may generate the erase voltage Verase in the erase operation, output the control signals VC_signals so that the voltage provision section 140 may generate the control voltage Vsoc and the pass voltage Vpass in the soft program operation, and may output the control signals VC_signals so that the voltage provision section 140 generates the verifying voltage Vverify in the erase verifying operation and the soft program verifying operation.
  • control circuit 150 may output the page buffer control signals PB_signals so that the page buffer 120 detects the pass/fail of the erase verifying operation and the soft program verifying operation by sensing potential of the bit lines BL in the erase verifying operation and the soft program verifying operation.
  • control circuit 150 may set target threshold voltages of selected memory cells in the memory cell array 110 to have the same value when the erase verifying operation and the soft program verifying operation may be performed.
  • FIG. 4 is a view illustrating the circuit diagram of a memory cell array in FIG. 3 .
  • the memory cell array 110 may include strings ST0 to STk. Since the strings ST0 to STk have a similar structure, their operation will be described through one string ST0 as a representative thereof.
  • the string ST0 may include a source select transistor SST, a first dummy cell DMC0, memory cells MC0 to MCn, a second dummy cell DMC1 and a drain select transistor DST connected between a source line SL and a bit line BL0.
  • the string ST0 may include a first dummy transistor and a second dummy transistor instead of the first dummy cell DMC0 and the second dummy cell DMC1, and may include two first dummy cells DMC0 and two second dummy cells DMC1.
  • the gate of the source select transistor SST and the gate of the drain select transistor DST may be connected to the source select line SSL and the drain select line DSL, respectively.
  • Gates of the first and the second dummy cells DMC0 and DMC1 may be connected to a first dummy line DWL ⁇ 0> and a second dummy line DWL ⁇ 1>, and word lines WL ⁇ n:0> may be connected to the memory cells MC0 to MCn.
  • Memory cells connected to the same word line may be defined as one page. That is, the memory cell array 110 may include pages.
  • FIG. 5 is a flow chart illustrating a method of operating a semiconductor memory device according to one example embodiment.
  • the method of operating the semiconductor memory device with reference to FIG. 3 to FIG. 5 is as follows.
  • the voltage provision section 140 may generate the erase voltage Verase in response to voltage provision section control signals outputted from the control circuit 150 .
  • the generated erase voltage Verase may be applied to a p-well of a semiconductor substrate on which the memory cell array 110 is formed.
  • 0V may be applied to word lines of the memory cell array 110 .
  • step S 510 it may be verified whether or not the memory cells in the memory cell array 110 are lower than a target threshold voltage HEV by using the page buffer 120 connected to the bit lines BL of the memory cell array 110 .
  • voltages applied to the bit line and the p-well increase by a core voltage, e.g. 1V when the threshold voltage of the memory cells are sensed, and then the increased voltages are provided.
  • the threshold voltage of the memory cell is negative voltage, e.g. ⁇ 1V
  • a voltage increased by the core voltage Vcore may be sensed as the threshold voltage.
  • the erase verifying operation is passed (i.e., yes) if the threshold voltage of every memory cell is lower than the target threshold voltage HEV according to the step S 520 , and it may be determined that the erase verifying operation is failed (i.e., No) if the threshold voltage of one or more memory cell is higher than the target threshold voltage HEV.
  • the erase voltage Verase used in the step S 510 may increase by a step voltage, the increased erase voltage Verase is set as new erase voltage Verase, and then the step S 510 and following steps may again performed using the new erase voltage Verase.
  • the voltage provision section 140 may increase the erase voltage
  • a soft program operation may be performed.
  • the HCI program method may be as follows.
  • the voltage provision section 140 generates a pass voltage Vpass, e.g. approximately 7.5V, operation voltage, e.g. about 4.5V applied to the drain select line DSL and the source select line SSL, and the control voltage Vsoc, e.g. 0V or negative voltage in response to the voltage provision section control signals outputted from the control circuit 150 .
  • Vpass e.g. approximately 7.5V
  • operation voltage e.g. about 4.5V applied to the drain select line DSL and the source select line SSL
  • Vsoc e.g. 0V or negative voltage
  • the X decoder 130 may apply the control voltage Vsoc generated from the voltage provision section 140 to a word line WL ⁇ n> adjacent to a selected word line, e.g. WL ⁇ n ⁇ 1> in a direction of the drain select transistor DST in response to the row address RADD to perform the soft program operation.
  • the X decoder 130 may apply the pass voltage Vpass generated from the voltage provision section 140 to the other word lines WL ⁇ 0> to WL ⁇ n ⁇ 1>, DWL ⁇ 1:0> in response to the row address RADD.
  • a channel boosting phenomenon occurs to a channel of the semiconductor substrate on which the memory cells MC0 to MCn ⁇ 1 and the dummy memory cells DMC0, DMC1, to which the pass voltage
  • the memory cell MCn connected to the word line WL ⁇ n> adjacent in a direction of the drain select transistor DST may be turned off according to the control voltage Vsoc, and so a channel is not formed.
  • Hot carrier in the semiconductor substrate, on which the memory cell MCn is formed may be injected to the floating gate of the memory cell MCn ⁇ 1 by electric field due to the pass voltage Vpass applied to the adjacent memory cell MCn ⁇ 1.
  • the memory cell MCn ⁇ 1 is programmed, and thus threshold voltage of the memory cell MCn ⁇ 1 increases.
  • a ground voltage may be applied to the bit line BL and the source line SL.
  • the above HCI program method may be performed in the unit of memory cells connected to the word line of the memory cells MC0 to MCn in the memory cell array 110 , i.e. the unit of the page.
  • the soft program verifying operation may be performed after the step S 550 is finished.
  • the soft program verifying operation may sense the threshold voltage of the programmed memory cells using the page buffer, and detect whether or not memory cell having threshold voltage higher than the target threshold voltage HEV of the programmed memory cells exists.
  • the soft program verifying operation may be desirable to sense and verify the threshold voltage of the memory cells using the virtual negative read VNR method.
  • Step S 570 Determination of the Soft Program Verifying Operation in Step S 570
  • the soft program verifying operation is passed (i.e., Yes) if one or more programmed memory cell having the threshold voltage higher than the target threshold voltage HEV exists according to the step S 560 . Then, the page address may be changed, and the soft program operation in the step S 550 and the soft program verifying operation in the step S 560 are again performed about memory cells corresponding to the changed page address. In addition, in case that the step S 550 and the step S 560 are performed about every page, operation of the semiconductor memory device is finished.
  • the soft program operation in the step S 550 may again be performed.
  • cycling number by which the steps S 550 and S 560 are repetitively performed is counted.
  • the counted cycling number is more than preset number, it is determined that operation of the memory cell array 110 is failed, and so the corresponding block may be regarded as a bad block.
  • Every memory cell MC0 to MCn in the memory cell array 110 has the threshold voltage of below 0V, i.e. threshold voltage corresponding to erase state according to the soft program operation. That is, the soft program operation is not an operation of storing data, and it is performed for increasing the threshold voltage of the memory cells up to approximately 0V and reducing width of the threshold voltage distribution.
  • the semiconductor memory device for which the soft program operation is finished, may perform a program operation for storing data, the program operation being performed by using the FN tunneling method.
  • FIG. 6 is a view illustrating a graph showing change of threshold voltage (i.e., Vt) distribution according to the soft program operation of the present invention (i.e., No).
  • width of threshold voltage distribution B of the memory cells becomes smaller than that of the threshold voltage distribution A (where the target threshold voltage is indicated by HEV) of the memory cells after the erase operation is performed.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
US13/718,784 2012-08-24 2012-12-18 Semiconductor memory device and method of operating the same Abandoned US20140056075A1 (en)

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KR10-2012-0093161 2012-08-24

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US10424381B2 (en) 2017-03-16 2019-09-24 Samsung Electronics Co., Ltd. Nonvolatile memory device and program method of the same

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KR20160021654A (ko) * 2014-08-18 2016-02-26 에스케이하이닉스 주식회사 반도체 메모리 장치 및 이의 동작방법
JP6470146B2 (ja) * 2015-08-27 2019-02-13 東芝メモリ株式会社 半導体記憶装置
KR102384959B1 (ko) * 2015-10-30 2022-04-11 에스케이하이닉스 주식회사 저장 장치, 이를 포함하는 메모리 시스템 및 이의 동작 방법
KR102461726B1 (ko) * 2016-07-19 2022-11-02 에스케이하이닉스 주식회사 메모리 장치 및 이의 동작 방법

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TWI587301B (zh) 2017-06-11
KR20140026141A (ko) 2014-03-05
CN103632719A (zh) 2014-03-12
CN103632719B (zh) 2018-09-28
US9564230B2 (en) 2017-02-07
TW201409473A (zh) 2014-03-01
US20150213902A1 (en) 2015-07-30

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