US20130277765A1

US20130277765A1 - Semiconductor device including graded gate stack, related method and design structure

Info

Publication number: US20130277765A1
Application number: US13/453,131
Authority: US
Inventors: Michael P. Chudzik; Min Dai; Jinping Liu; Joseph F. Shepard, Jr.; Keith Kwong Hon Wong
Original assignee: GlobalFoundries Inc; International Business Machines Corp
Current assignee: GlobalFoundries Inc
Priority date: 2012-04-23
Filing date: 2012-04-23
Publication date: 2013-10-24
Also published as: US9257519B2; US20140070334A1

Abstract

A semiconductor device is disclosed. The semiconductor device includes a substrate; and a gate structure disposed directly on the substrate, the gate structure including: a graded region with a varied material concentration profile; and a metal layer disposed on the graded region.

Description

TECHNICAL FIELD

Embodiments of this disclosure relate generally to semiconductor devices and, more particularly, to a semiconductor device including a graded metal and/or graded high dielectric constant (high-K) gate stack, a related method and design structure.

BACKGROUND

In semiconductor devices, graded regions (e.g., regions with a varying composition of silicon, silicates, metals, etc.) are frequently included adjacent to or as a part of gate elements to decrease device size and increase device performance. The use and effectiveness of these graded regions in devices may be impacted by the composition, scaling, and/or gradation of the graded regions themselves. Traditionally, graded regions (e.g., dielectric materials) may be formed by a high temperature anneal which generates a material concentration variation within the graded region. However, in these methods, the high temperature anneal may complicate the process flow, require additional process chambers for the anneal, fail to create a fully graded region, and/or damage other components in the semiconductor device. Further, this high temperature annealing may diminish film quality and be unable to control the profile of the graded region, limiting profile design and future scaling options for the semiconductor devices. To accommodate this high temperature anneal, some methods include an interface layer disposed between the dielectric and the substrate. The inclusion of an additional interface in the semiconductor devices may increase fixed charges and limit mobility.

BRIEF SUMMARY

A first aspect of the disclosure provides a semiconductor device including: a substrate; and a gate structure disposed directly on the substrate, the gate structure including: a graded region with a varied material concentration profile; and a metal layer disposed on the graded region.
A second aspect of the disclosure provides a method of forming a semiconductor device, the method including: providing a substrate; forming a graded region directly upon a portion of the substrate, the graded region including a varied material concentration profile; and introducing nitrogen into the graded region to control the varied material concentration profile.
A third aspect of the disclosure provides a design structure tangibly embodied in a machine readable medium for design, manufacturing, or testing a semiconductor device, the design structure including: a substrate; and a gate structure disposed directly on the substrate, the gate structure including: a graded region with a varied material concentration profile; and a metal layer disposed on the graded region.
These and other aspects, advantages and salient features of the invention will become apparent from the following detailed description, which, when taken in conjunction with the annexed drawings, where like parts are designated by like reference characters throughout the drawings, disclose embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects, features and advantages of the invention will be better understood by reading the following more particular description of the invention in conjunction with the accompanying drawings.

FIG. 1 is a demonstrative illustration of a portion of a semiconductor device according to an embodiment of the invention.

FIG. 2 is a demonstrative illustration of a graphical representation of a profile of a portion of a semiconductor device according to an embodiment of the invention.

FIG. 3 is a demonstrative illustration of a graphical representation of a profile of a portion of a semiconductor device according to an embodiment of the invention.

FIG. 4 is a demonstrative illustration of a portion of a semiconductor device according to an embodiment of the invention.

FIGS. 5-8 are demonstrative illustrations of a method of forming a semiconductor device according to embodiments of the invention.

FIGS. 9-14 are demonstrative illustrations of a method of forming a semiconductor device according to embodiments of the invention.

FIG. 15 is a demonstrative illustration of a portion of a semiconductor device according to an embodiment of the invention.

FIG. 16 is a demonstrative illustration of a flow diagram of a design process used in semiconductor design, manufacture, and/or test according to embodiments of the invention.

It is noted that the drawings of the disclosure are not necessarily to scale. The drawings are merely schematic representations, not intended to portray specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention, and therefore should not be considered as limiting the scope of the invention. It is understood that in embodiments shown and described in the drawings, like numbering may represent like elements and that redundant explanation of these elements has been omitted for clarity. Finally, it is understood that the components of the drawings and their accompanying descriptions may be applied to any embodiment described herein.

DETAILED DESCRIPTION

FIG. 1 is a demonstrative illustration of a cross sectional view of a portion of a semiconductor device 100 according to embodiments of the invention. Semiconductor device 100 may include a substrate 140, with a graded region 120 defined and/or formed thereon. Graded region 120 may include a plurality of materials and have a chemical concentration of material(s) which varies within the region to form a varied material concentration profile ‘G.’ A metal layer 170 may be disposed on graded region 120 forming a metal gate 172.
Graded region 120 may include a first portion 122 in contact with substrate 140, and a second portion 124 disposed above substrate 140 and first portion 122. In one embodiment, graded region 120 may include a high dielectric constant (high-K dielectric) region (e.g., a region with a high degree of permittivity relative other materials in semiconductor device 100). A concentration of the material(s) which comprise graded region 120 may vary gradually, linearly, incrementally, or exponentially between first portion 122 and second portion 124. In one embodiment, composition of graded region 120 at first portion 122 may be substantially silicon and composition of graded region 120 at second portion 124 may be substantially metal. In contrast to conventional techniques, graded region 120 may be deposited and/or formed directly on substrate 140 without an interface layer. In one embodiment, graded region 120 may form a gate structure 126. Silicates, metals and/or metal oxides may be deposited as part of graded region 120. As used herein, the term “depositing” may include any now known or later developed techniques appropriate for the material to be deposited including but are not limited to, for example: chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), semi-atmosphere CVD (SACVD) and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metalorganic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser-assisted deposition, thermal oxidation, thermal nitridation, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation, etc.
In any event, graded region 120 may be formed as a set of films (shown in FIG. 15) with a composition which is manipulated to generate a varied material concentration profile ‘G’ for graded region 120. Graded region 120 may have a material concentration profile G which is defined by Equation 1 below, where the material composition at a given point of graded region 120 is determined by:
Material Composition=M_XSi_1-XO_y Eq. 1
Where M is the metal composition (e.g., Aluminum, Magnesium, etc.) of graded region 120 at a given point ‘X’, Si the silicon composition of graded region 120 at given point X, and O_ythe oxide composition of graded region 120 at given point X. In one embodiment, graded region 120 may include (e.g., contain) at least one of: aluminum (Al), magnesium (Mg), lanthanum (La), aluminum oxide (Al₂O₃), lanthanum oxide (La₂O₃), and zirconium oxide (Zr₂O₃). It is understood that while specific material examples for graded region 120 are described herein, graded region 120 may include any combination of now known or later developed materials which provide the features described herein. For instance, metal composition M may include a plurality of metals (e.g., Aluminum, Hafnium Oxide (HfO₂), Magnesium, etc.).
Further, graded region 120 may include any commonly used dielectric and/or gate material including but not limited to polysilicon or high melting point refractory metals, such as W, Ti, Ta, Mo, Nb, Re, Ru and their binary or ternary metallic derivatives, e.g., WN, TiN, TaN, MoN, MoO2, TaSiN. Further, graded region 120 may comprise a gate structure 126 on semiconductor substrate 140. Graded region 120 may comprise any commonly used gate dielectric material including but not limited to oxide, nitride, oxynitride, and high-k materials such as hafnium silicate, zirconium silicate, hafnium dioxide, and zirconium dioxide. Further, graded region 120 may include silicon dioxide (SiO₂), silicon nitride (SiN), or any other material now known or later developed. Any number of dielectric regions may be located over the substrate, as many other layers included in semiconductor chips now known or later developed. In one embodiment, graded region 120 may include silicon dioxide (SiO₂) for its insulating, mechanical and optical qualities. Graded region 120 may also include, but is not limited to: silicon nitride (Si₃N₄), fluorinated SiO₂(FSG), hydrogenated silicon oxycarbide (SiCOH), porous SiCOH, boro-phosho-silicate glass (BPSG), silsesquioxanes, carbon (C) doped oxides (i.e., organosilicates) that include atoms of silicon (Si), carbon (C), oxygen (O), and/or hydrogen (H), thermosetting polyarylene ethers, SiLK (a polyarylene ether available from Dow Chemical Corporation), a spin-on silicon-carbon containing polymer material available from JSR Corporation, other low dielectric constant (<3.9) material, or layers thereof.
In an embodiment, graded region 120 may be formed via a low temperature process which decreases the thermal budget of semiconductor device 100 and eliminates the need for an interface layer to thermally insulate substrate 140, thereby making semiconductor device 100 replacement metal gate (RMG) compatible. Graded region 120 may include a first portion 122 adjacent substrate 140 which is substantially dielectric and a second portion 124 which is substantially metal. The controllable composition profile engineering provided by graded region 120 may enable linear and/or exponential gradation and variation of material concentration between first portion 122 at substrate 140 and second portion 124. Use of graded region 120 may form a natural film stack between substrate 140 and the top of metal gate 172, eliminating the interface formed by an interface layer. In one embodiment, graded region 120 may be formed via an in-situ process (e.g., in the same process chamber used to perform other processes of forming semiconductor device 100) as a portion of the formation of semiconductor device 100. Graded region 120 may be used to scale the leakage current and equivalent oxide thickness (EOT) of semiconductor device 100 via optimization, design and control of the material concentration profile G of semiconductor device 100. Further, through material compositions control and scaling, graded region 120 may be engineered to reduce the fixed charge and improve mobility via reduction of layer interfaces in semiconductor device 100. The transitory material concentration profile G of graded region 120 reduces the number of interfaces between layers of semiconductor device 100, providing a gradual transition between substrate 140 and metal layer 172.
In one embodiment, nitrogen plasma and/or a rapid thermal (RT) ammonia (NH₃) anneal may be used to introduce Nitrogen into graded region 120 with desired profiles. This introduction may be included as a part of a nitridation process for graded region 120. During an NH₃anneal, the material concentration profile G of graded region 120 may be controlled by manipulating at least one of a temperature, a pressure, and a duration of the NH₃anneal. For a plasma nitridation process, the material concentration profile G of graded region 120 may be controlled by manipulating at least one of a power, a pressure, and a temperature of the plasma process. Further, a post anneal may be used following the plasma process for additional Nitrogen profile engineering. In one embodiment, the material concentration profile G may be controlled by performing a series of nitridation and deposition processes with varying Nitrogen contents (e.g., separating nitrogen deposition into several stages of deposition divided by nitridation processes).
Substrate 140 can comprise any commonly used substrate material including but not limited to silicon, germanium, silicon germanium, silicon carbide, and those consisting essentially of one or more Group III-V compound semiconductors having a composition defined by the formula Al_X1Ga_X2In_X3As_Y1P_Y2N_Y3Sb_Y4, where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions, each greater than or equal to zero and X1+X2+X3+Y1+Y2+Y3+Y4=1 (1 being the total relative mole quantity). Substrate 140 may also be comprised of Group II-VI compound semiconductors having a composition Zn_A1Cd_A2Se_B1Te_B2, where A1, A2, B1, and B2 are relative proportions each greater than or equal to zero and A1+A2+B1+B2=1 (1 being a total mole quantity). The processes to provide substrate 140, as illustrated and described, are well known in the art and thus, no further description is necessary.
Turning to FIG. 2, a demonstrative illustration of a graphical representation of a material concentration profile of a graded region 120 is shown according to embodiments of the invention. In this embodiment, graded region 120 includes a material concentration profile which is Silicon (Si) rich at a proximity to substrate 140 (e.g., first portion 122) and becomes Hafnium (Hf) rich proximate an extremity of graded region 120 opposite substrate 140 (e.g., second portion 124). The material profile of graded region 120 may be represented by equation 2 below:
Material Composition=Hf_XSi_1-XO_y Eq. 2
As can be seen in FIG. 2, as the amount of Hf in graded region 120 increases the percentage of Si decreases. During the formation of this graded HfO₂dielectric (e.g., graded region 120), varying the material deposition composition relative a position ‘X’ in graded region 120, results in deposition of a controlled graded film with scaled equivalent oxide thickness (EOT). Turning to FIG. 3, a graphical representation of a material concentration profile of a graded region 120 is shown according to embodiments of the invention. In this embodiment, graded material includes a non-linear material concentration profile which is Si rich proximate first portion 122, and varies exponentially between first portion 122 and second portion 124, becoming Hf rich proximate an extremity of graded region 120 opposite substrate 140.
Turning to FIG. 4, a demonstrative illustration of a cross sectional view of a portion of a semiconductor device 102 is shown according to embodiments of the invention. In this embodiment, semiconductor device 102 includes an interface layer 130 disposed between substrate 140 and graded region 120.
FIGS. 5-8 are demonstrative illustrations of a device undergoing a method according to embodiments of the invention. Although FIGS. 5-8 show the method of forming a portion of semiconductor device 100 in FIG. 1, it is understood that a similar method may be employed to form semiconductor device 102 of FIG. 4, or any other like semiconductor device.
Turning to FIG. 5, a demonstrative illustration of a substrate 140 in semiconductor device 100 is shown in preparation for deposition of layers. Substrate 140 may include silicon or any other material commonly known and may be chemically cleaned. In one embodiment, a trench 152 (shown in phantom) may be etched in substrate 140. Trench 152 may be etched using any now known or later developed etching techniques. In one embodiment, etching of substrate 140 may be performed using a reactive ion etch (RIE). As is known in the art of semiconductor fabrication, RIE uses chemically reactive plasma to remove material deposited on wafers/substrates. Differences in width between these openings may allow for utilizing a phenomenon known as inverse RIE lag. Inverse RIE lag, as is known in the art of semiconductor fabrication, causes a faster etch rate in narrower openings (higher aspect ratios) than in openings having larger widths (lower aspect ratios). Inverse RIE lag may be induced under any conditions characterized by high polymerization and high wafer self-bias voltages. In one embodiment, conditions characterized by high polymerization, may include general chemistries such as CxHyFz (Carbon-Hydrogen-Flourine) with high oxide-to-nitride selectivity (where the blanket etch rate ratio is greater than approximately 20:1). In another embodiment, conditions characterized by high polymerization may include O₂(oxygen), a dilutant, and one or more of: C₄F₆, C₅F₈, or C₄F₈. In this case, the dilutant may be, for example, Argon (Ar). High wafer self-bias voltages may, for example, be voltages greater than approximately 500 volts. While specific conditions for facilitating inverse RIE lag are described herein, those conditions are merely illustrative. Inverse RIE lag may be induced under other conditions not specifically described herein.
Next, in FIG. 6, a demonstrative illustration of graded region 120 is shown deposited on substrate 140. In one embodiment, graded region 120 may be deposited as a set of films on substrate 140, the films having a varied material composition relative to desired material concentration profile G. For example, composition of graded region 120 at first portion 122 may be substantially silicon and composition of graded region 120 at second portion 124 may be substantially metal. Graded region 120 having a varied chemical composition between first portion 122 and second portion 124 based on a relative position to material concentration profile G, this variation including varying amounts of silicon and metal. In any event, following deposition of graded region 120, semiconductor device 100 may be polished to develop the surfaces.
Next, in FIG. 7, a demonstrative illustration is shown where graded region 120 may optionally be subjected to Nitrogen (N) plasma and/or RT NH₃annealing 180 to introduce desired N profiles in graded region 120 and semiconductor device 100. This optional introduction of N further engineers material concentration profile G.
Turning now to FIG. 8, following the N introduction, a thermal anneal 182 may optionally be applied to semiconductor device 100 to stabilize the films that comprise graded region 120. Stabilization of the films may produce semiconductor device 100 of FIG. 1 which includes a gate structure 126 formed by graded region 120. Gate structure 126 may include a first portion 122 contacting substrate 140 and comprising substantially silicon (e.g., about 100% silicon), and a second portion 124 forming the top of gate structure 126 and comprising substantially metal (e.g., about 100% aluminum). Transition of material concentration/composition through graded region 120 between first portion 122 and second portion 124 may be linear (e.g., natural, gradual or incremental as shown in FIG. 2), exponential (e.g., irregular or varying as shown in FIG. 3), or any other form of gradation or transition known.
FIGS. 9-14 are demonstrative illustrations of a semiconductor device 102 (FIG. 4) undergoing processes according to a method in accordance with another embodiment of the invention. In this method an interface layer 130 is formed as a layer of semiconductor device 102. Although FIGS. 9-14 are demonstrative illustrations of the method of forming a portion of semiconductor device 102 in FIG. 4, it is understood that a similar method may be employed to form semiconductor device 100 of FIG. 1, or any other like semiconductor device.
Returning to FIG. 9, a demonstrative illustration of a cross-sectional view of semiconductor device 102 undergoing a process according to embodiments is shown. In one embodiment, a trench 152 (shown in phantom) may be etched in substrate 140. As discussed herein, trench 152 may be etched using any now known or later developed etching techniques.
Next, in FIG. 10, a demonstrative illustration is shown of an interface layer 130 being deposited on substrate 140 to form an interface between substrate 140 and graded region 120. Following deposition of interface layer 130, in FIG. 11, graded region 120 is deposited on substrate 140. Graded region 120 may be deposited via PVD, ALD, CVD or any other known deposition techniques. In one embodiment, graded region 120 may be deposited as a set of films on substrate 140, the set of films having a varied material composition relative one another and being deposited in accordance with material concentration profile G. Following deposition of graded region 120, semiconductor device 100 may be polished to develop the surfaces. After deposition of graded region 120, as can be seen in FIG. 12, graded region 120 may optionally be subjected to N plasma and/or RT NH₃annealing 180 to introduce desired N profiles in graded region 120 and semiconductor device 100.
Turning now to FIG. 13, following the N introduction, a thermal anneal 182 may optionally be applied to semiconductor device 100 to stabilize the films that comprise graded region 120. Stabilization of the films may produce semiconductor device 102 of FIG. 14 which includes a trench 152 disposed beneath gate structure 126 formed by graded region 120. Gate structure 126 may include a first portion 128 contacting interface layer 130 and comprising substantially silicon (e.g., about 100% silicon), and a second portion 124 forming the top of the gate and comprising substantially metal (e.g., about 100% aluminum). Transition of material concentration/composition through graded region 120 between first portion 128 and second portion 124 may be linear (e.g., gradual or incremental as shown in FIG. 2), exponential (e.g., irregular or varying as shown in FIG. 3), or any other form of gradation or transition known.
Turning to FIG. 15, a demonstrative illustration of a cross sectional view of a portion of a semiconductor device 108 is shown according to embodiments of the invention. In this embodiment, graded region 127 of semiconductor device 108 includes a plurality of films 186 to 186+n disposed upon substrate 140. Each film 186 to 186+n in the plurality of films may comprise a varied material composition (e.g., specific proportions of silicon, metals, oxides, Nitrogen, etc.). Films 186 to 186+n may be disposed upon substrate according to desired profile characteristics represented by material concentration profile G, defining the material composition profile of graded region 120. For example, in one embodiment, film 186 may be deposited at first portion 122 with a composition of substantially silicon, then a film 186+1 may be deposited on film 186 with a composition of about 95% to about 99% silicon, and about 1% to about 5% silicate (e.g., hafnium). As multiple layers are deposited on substrate 140 the proportions of silicon hafnium and any number of other materials and chemicals may be varied to control the material concentration profile of graded region 120. In one embodiment, film 186+n may include hafnium nitride, thereby forming a high-K metal gate 172.
FIG. 16 is a demonstrative illustration of a flow diagram of an exemplary design flow 900 used for example, in semiconductor IC logic design, simulation, test, layout, and manufacture. Design flow 900 includes processes, machines and/or mechanisms for processing design structures or devices to generate logically or otherwise functionally equivalent representations of the design structures and/or devices described above and shown in FIG. 1. The design structures processed and/or generated by design flow 900 may be encoded on machine-readable transmission or storage media to include data and/or instructions that when executed or otherwise processed on a data processing system generate a logically, structurally, mechanically, or otherwise functionally equivalent representation of hardware components, circuits, devices, or systems. Machines include, but are not limited to, any machine used in an IC design process, such as designing, manufacturing, or simulating a circuit, component, device, or system. For example, machines may include: lithography machines, machines and/or equipment for generating masks (e.g. e-beam writers), computers or equipment for simulating design structures, any apparatus used in the manufacturing or test process, or any machines for programming functionally equivalent representations of the design structures into any medium (e.g. a machine for programming a programmable gate array).
Design flow 900 may vary depending on the type of representation being designed. For example, a design flow 900 for building an application specific IC (ASIC) may differ from a design flow 900 for designing a standard component or from a design flow 900 for instantiating the design into a programmable array, for example a programmable gate array (PGA) or a field programmable gate array (FPGA).
FIG. 16 illustrates multiple such design structures including an input design structure 920 that is preferably processed by a design process 910. Design structure 920 may be a logical simulation design structure generated and processed by design process 910 to produce a logically equivalent functional representation of a hardware device. Design structure 920 may also or alternatively comprise data and/or program instructions that when processed by design process 910, generate a functional representation of the physical structure of a hardware device. Whether representing functional and/or structural design features, design structure 920 may be generated using electronic computer-aided design (ECAD) such as implemented by a core developer/designer. When encoded on a machine-readable data transmission, gate array, or storage medium, design structure 920 may be accessed and processed by one or more hardware and/or software modules within design process 910 to simulate or otherwise functionally represent an electronic component, circuit, electronic or logic module, apparatus, device, or system such as those shown in FIG. 1. As such, design structure 920 may comprise files or other data structures including human and/or machine-readable source code, compiled structures, and computer-executable code structures that when processed by a design or simulation data processing system, functionally simulate or otherwise represent circuits or other levels of hardware logic design. Such data structures may include hardware-description language (HDL) design entities or other data structures conforming to and/or compatible with lower-level HDL design languages such as Verilog and VHDL, and/or higher level design languages such as C or C++.
Design process 910 preferably employs and incorporates hardware and/or software modules for synthesizing, translating, or otherwise processing a design/simulation functional equivalent of the components, circuits, devices, or logic structures shown in FIG. 1 to generate a netlist 980 which may contain design structures such as design structure 920. Netlist 980 may comprise, for example, compiled or otherwise processed data structures representing a list of wires, discrete components, logic gates, control circuits, I/O devices, models, etc. that describes the connections to other elements and circuits in an integrated circuit design. Netlist 980 may be synthesized using an iterative process in which netlist 980 is resynthesized one or more times depending on design specifications and parameters for the device. As with other design structure types described herein, netlist 980 may be recorded on a machine-readable data storage medium or programmed into a programmable gate array. The medium may be a non-volatile storage medium such as a magnetic or optical disk drive, a programmable gate array, a compact flash, or other flash memory. Additionally, or in the alternative, the medium may be a system or cache memory, buffer space, or electrically or optically conductive devices and materials on which data packets may be transmitted and intermediately stored via the Internet, or other networking suitable means.
Design process 910 may include hardware and software modules for processing a variety of input data structure types including netlist 980. Such data structure types may reside, for example, within library elements 930 and include a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.). The data structure types may further include design specifications 940, characterization data 950, verification data 960, design rules 970, and test data files 985 which may include input test patterns, output test results, and other testing information. Design process 910 may further include, for example, standard mechanical design processes such as stress analysis, thermal analysis, mechanical event simulation, process simulation for operations such as casting, molding, and die press forming, etc. One of ordinary skill in the art of mechanical design can appreciate the extent of possible mechanical design tools and applications used in design process 910 without deviating from the scope and spirit of the invention. Design process 910 may also include modules for performing standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc.
Design process 910 employs and incorporates logic and physical design tools such as HDL compilers and simulation model build tools to process design structure 920 together with some or all of the depicted supporting data structures along with any additional mechanical design or data (if applicable), to generate a second design structure 990. Design structure 990 resides on a storage medium or programmable gate array in a data format used for the exchange of data of mechanical devices and structures (e.g. information stored in a IGES, DXF, Parasolid XT, JT, DRG, or any other suitable format for storing or rendering such mechanical design structures). Similar to design structure 920, design structure 990 preferably comprises one or more files, data structures, or other computer-encoded data or instructions that reside on transmission or data storage media and that when processed by an ECAD system generate a logically or otherwise functionally equivalent form of one or more of the embodiments of the invention shown in FIG. 1. In one embodiment, design structure 990 may comprise a compiled, executable HDL simulation model that functionally simulates the devices shown in FIG. 1.
Design structure 990 may also employ a data format used for the exchange of layout data of integrated circuits and/or symbolic data format (e.g. information stored in a GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design data structures). Design structure 990 may comprise information such as, for example, symbolic data, map files, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a manufacturer or other designer/developer to produce a device or structure as described above and shown in FIG. 1. Design structure 990 may then proceed to a stage 995 where, for example, design structure 990: proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, etc.
The circuit as described above is part of the design for an integrated circuit chip. The chip design is created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer transmits the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.
The method as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
While various embodiments are described herein, it will be appreciated from the specification that various combinations of elements, variations or improvements therein may be made by those skilled in the art, and are within the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope of the appended claims.

Claims

What is claimed is:

1. A semiconductor device comprising:

a substrate; and

a gate structure disposed directly on the substrate, the gate structure including:

a graded region with a varied material concentration profile; and

a metal layer disposed on the graded region.

2. The semiconductor device of claim 1, wherein the graded region includes a first portion proximate the substrate and a second portion proximate the metal layer, the first portion comprising substantially silicon and the second portion comprising substantially metal.

3. The semiconductor device of claim 1, wherein the graded region contains at least one of aluminum (Al), magnesium (Mg), lanthanum (La), aluminum oxide (Al₂O₃), lanthanum oxide (La₂O₃), and zirconium oxide (Zr₂O₃).

4. The semiconductor device of claim 1, wherein a concentration of each material in the graded region varies linearly.

5. The semiconductor device of claim 1, wherein a concentration of each material in the graded region varies exponentially.

6. The semiconductor device of claim 1, wherein the graded region includes a plurality of films, the plurality of films having a varied material composition relative one another.

7. A method of forming a semiconductor device, the method comprising:

providing a substrate; and

forming a graded region directly upon a portion of the substrate, the forming including introducing nitrogen into the graded region to control a varied material concentration profile of the graded region.

8. The method of claim 7, wherein forming the graded region includes:

forming a first portion proximate the substrate, the first portion containing substantially silicon; and

forming a second portion above the first portion and the substrate, the second portion containing substantially metal.

9. The method of claim 7, wherein forming the graded region includes depositing the graded region in-situ.

10. The method of claim 7, wherein forming the graded region includes:

depositing a plurality of films on the substrate, the plurality of films having a varied material composition relative one another; and

patterning the plurality of films to form a gate stack.

11. The method of claim 7, wherein the graded region includes at least one of aluminum (Al), magnesium (Mg), lanthanum (La), aluminum oxide (Al₂O₃), lanthanum oxide (La₂O₃), and zirconium oxide (Zr₂O₃).

12. The method of claim 7, further comprising annealing the substrate and the graded region to stabilize the graded region.

13. The method of claim 7, wherein forming the graded region includes performing a nitrogen plasma process on the graded region.

14. The method of claim 13, further comprising controlling the varied material concentration profile of the graded region by manipulating at least one of: a temperature of the nitrogen plasma process, a pressure of the nitrogen plasma process, and a duration of the nitrogen plasma process.

15. The method of claim 7, wherein forming the graded region includes performing a rapid thermal ammonia (NH₃) annealing process on the graded region.

16. The method of claim 15, further comprising controlling the varied material concentration profile of the graded region by manipulating at least one of: a temperature of the rapid thermal ammonia (NH₃) annealing process, a pressure of the rapid thermal ammonia (NH₃) annealing process, and a duration of the rapid thermal ammonia (NH₃) annealing process.

17. A design structure tangibly embodied in a machine readable medium for design, manufacturing, or testing a semiconductor device, the design structure comprising:

a substrate; and

a graded region with a varied material concentration profile; and

a metal layer disposed on the graded region.

18. The design structure of claim 17, wherein the graded region includes a first portion proximate the substrate and a second portion proximate the metal layer, the first portion comprising substantially silicon and the second portion comprising substantially metal.

19. The design structure of claim 17, wherein the graded region contains at least one of aluminum (Al), magnesium (Mg), lanthanum (La), aluminum oxide (Al₂O₃), lanthanum oxide (La₂O₃), and zirconium oxide (Zr₂O₃).

20. The design structure of claim 17, wherein the graded region includes a plurality of films, the plurality of films having a varied material composition relative one another.