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US20130147544A1 - Reference voltage generation circuit and internal volatage generation circuit using the same - Google Patents

Reference voltage generation circuit and internal volatage generation circuit using the same Download PDF

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Publication number
US20130147544A1
US20130147544A1 US13/451,473 US201213451473A US2013147544A1 US 20130147544 A1 US20130147544 A1 US 20130147544A1 US 201213451473 A US201213451473 A US 201213451473A US 2013147544 A1 US2013147544 A1 US 2013147544A1
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reference voltage
internal
voltage
resistor
generation circuit
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US13/451,473
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Young Joo Kim
Jong Ho Son
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SK Hynix Inc
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Hynix Semiconductor Inc
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Assigned to HYNIX SEMICONDUCTOR INC. reassignment HYNIX SEMICONDUCTOR INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KIM, YOUNG JOO, SON, JONG HO
Publication of US20130147544A1 publication Critical patent/US20130147544A1/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is DC
    • G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage

Definitions

  • a semiconductor memory device receives power supply voltage VDD and ground voltage VSS from an outside source, and generates and uses internal voltages required for internal operations.
  • the internal voltages required for internal operations of the semiconductor memory device may include a core voltage VCORE supplied to a memory core area, a boosting voltage VPP used for driving or overdriving a word line, and a back bias voltage VBB supplied as a bulk voltage of an NMOS transistor of a memory core area.
  • the core voltage VCORE may be supplied by lowering the power supply voltage VDD inputted from outside to a predetermined level.
  • the boosting voltage VPP has a higher level than the power supply voltage VDD inputted from outside, and the back bias voltage VBB maintains a lower level than the ground voltage VSS inputted from outside. Therefore, charge pump circuits are needed to supply charges for the boosting voltage VPP and the back bias voltage VBB.
  • internal voltages are generated by using a reference voltage.
  • the internal voltage is driven by a power supply voltage or generated by pumping the internal voltage.
  • a temperature characteristic change of the reference voltage may have an effect upon the internal voltage, thereby causing an error in an operation of an internal circuit receiving the internal voltage.
  • An embodiment of the present invention relates to an internal voltage generation circuit capable of constantly maintaining the temperature characteristic of a reference voltage according to an internal temperature change by controlling the level of the reference voltage, thereby preventing an error from occurring in an operation of an internal circuit receiving an internal voltage, and an internal voltage generation circuit using the same.
  • a reference voltage generation circuit configured to generate a reference voltage level that is compensated for based on an internal temperature change, where the reference voltage level is adjusted based on a resistance value controlled in response to a control signal.
  • an internal voltage generation circuit includes: a reference voltage generation unit configured to control the level of a reference voltage in response to a control signal; a pad configured to monitor the reference voltage or apply a voltage to the reference voltage; and an internal voltage trimming unit configured to receive the reference voltage and generate first and second internal voltages trimmed at different levels.
  • an internal voltage generation circuit includes: a reference voltage generation unit configured to control the level of a first reference voltage in response to a control signal; a buffer unit configured to buffer the first reference voltage and generate a second reference voltage; a pad configured to monitor the second reference voltage or apply a voltage to the second reference voltage; and an internal voltage trimming unit configured to receive the second reference voltage and generate first and second internal voltages trimmed at different levels.
  • FIG. 1 is a block diagram illustrating a configuration of an internal voltage generation circuit in accordance with an embodiment of the present invention
  • FIG. 2 is a circuit diagram of a reference voltage generation circuit included in an internal voltage generation circuit illustrated in FIG. 1 ;
  • FIG. 3 is a circuit diagram of an internal voltage trimming unit included in the internal voltage generation circuit illustrated in FIG. 1 ;
  • FIG. 4 is a graph showing characteristic changes of a reference voltage generated by the reference voltage generation circuit of FIG. 2 depending on an internal temperature change of the reference voltage;
  • FIG. 5 is a block diagram illustrating a configuration of an internal voltage generation circuit in accordance with another embodiment of the present invention.
  • FIG. 1 is a block diagram illustrating a configuration of an internal voltage generation circuit in accordance with an embodiment of the present invention.
  • the internal voltage generation circuit in accordance with an embodiment of the present invention includes a reference voltage generation unit 1 , a pad 2 , and an internal voltage trimming unit 3 .
  • the reference voltage generation unit 1 is configured to control a level of a reference voltage VREF in response to first and second control signals CNT ⁇ 1:2>.
  • the pad 2 is configured to output the reference voltage VREF for monitoring, and applying a voltage to the reference voltage VREF.
  • the internal voltage trimming unit 3 is configured to receive the reference voltage VREF, and generate first and second internal voltages VINT 1 and VINT 2 trimmed at different levels.
  • FIGS. 2 and 3 configurations of the reference voltage generation unit 1 , the pad 2 , and the internal voltage generation unit 3 will be described in more detail as follows.
  • the reference voltage generation unit 1 includes a current source 11 , a first resistor section 12 , and a second resistor section 13 .
  • the current source 11 may be implemented with a Widlar-type current source which includes MOS transistors and resistors having reverse current characteristics depending on an internal temperature change, and the current source 11 may generate a current I.
  • the current I is outputted to a node nd 11 from which the reference voltage VREF is outputted.
  • the first resistor section 12 includes a plurality of diodes coupled between the first node nd 11 and a ground voltage.
  • the second resistor section 13 includes a resistor R 11 , an NMOS transistor N 11 , a resistor R 12 , and an NMOS transistor N 12 .
  • the resistor R 11 is coupled between the node nd 11 and a node nd 12 .
  • the NMOS transistor N 11 operates as a switch element which is turned on to short the nodes nd 11 and nd 12 in response to the first control signal CNT ⁇ 1>.
  • the resistor R 12 is coupled between the node nd 12 and the ground voltage.
  • the NMOS transistor N 12 operates as a switch element which is turned on to short the node nd 12 to the ground voltage in response to the second control signal CNT ⁇ 2>.
  • the level of the reference voltage VREF generated by the reference voltage generation unit 1 configured in such a manner decreases when the resistance value of the second resistor section 13 is increased according to the first and second control signals CNT ⁇ 1:2>, and increases when the resistance value of the second resistor section 13 is decreased.
  • the internal voltage trimming unit 3 includes a PMOS transistor P 31 , a resistor R 31 , a resistor R 32 , a resistor R 33 , and a comparator 31 .
  • the PMOS transistor P 31 operates as a driver configured to drive a node nd 31 in response to a pull-up signal PU.
  • the resistor R 31 is coupled between the node nd 31 and a node nd 32 from which the first internal voltage VINT 1 is outputted.
  • the resistor R 32 is coupled between the node nd 32 and a node nd 33 from which the second internal voltage VINT 2 is outputted.
  • the resistor R 33 is coupled between the node nd 33 and a ground voltage.
  • the comparator 31 is configured to generate a pull-up signal PU which is enabled to a logic low level when the second internal voltage VINT 2 has a lower level than the reference voltage VREF.
  • the internal voltage trimming unit 3 configured in such a manner generates the first and second internal voltages VINT 1 and VINT 2 having levels that are controlled according to the reference voltage VREF. That is, the voltage levels of the first and second internal voltages VINT 1 and VINT 2 increase when the voltage level of the reference voltage VREF is increased, and voltage levels of the first and second internal voltages VINT 1 and VINT 2 decrease when the voltage level of the reference voltage VREF is decreased.
  • FIG. 4 illustrates a graph showing characteristic changes of a reference voltage generated by the reference voltage generation circuit of FIG. 2 depending on an internal temperature change of the reference voltage.
  • a PVT variation may cause a reference voltage VREF increase from a level V 1 to a level V 2 , which may cause a change in the temperature characteristic of the reference voltage VREF. That is, when the reference voltage VREF corresponds to level V 1 , the amount of the current I at a high temperature T 1 is smaller than at a low temperature T 2 . However, when the reference voltage VREF corresponds to the level V 2 , the amount of the current I at the high temperature T 1 is larger than at the low temperature T 2 .
  • the internal voltage generation circuit in accordance with an embodiment of the present invention decreases the voltage level of the reference voltage VREF by increasing the resistance value of the second resistor section 13 according to the first and second control signals CNT ⁇ 1:2>.
  • the temperature characteristic of the reference voltage VREF is changed. That is, when the reference voltage VREF corresponds to the level V 2 , the amount of the current I at the high temperature T 1 is larger than at the low temperature T 2 , but when the reference voltage VREF corresponds to the level V 1 , the amount of the current I at the high temperature T 1 is smaller than the low temperature T 2 .
  • the temperature characteristic changes of the reference voltage VREF are reflected in the first and second internal voltages VINT 1 and VINT 2 , thereby causing an operation error of the internal circuit.
  • the internal voltage generation circuit in accordance with an embodiment of the present invention increases a level of the reference voltage VREF by reducing the resistance value of the second resistor section 13 according to the first and second control signals CNT ⁇ 1:2> to maintain a reference voltage substantially near the zero temperature coefficient point (ZTC).
  • the internal voltage generation circuit in accordance with an embodiment of the present invention may control a level of the reference voltage VREF according to the first and second control signals CNT ⁇ 1:2> and maintain and/or adjust the temperature characteristic of the reference voltage depending on the internal voltage change. Therefore, temperature characteristics of the first and second internal voltages VINT 1 and VINT 2 may be maintained to substantially prevent an error in the operations of the internal circuits.
  • FIG. 5 is a block diagram illustrating the configuration of an internal voltage generation circuit in accordance with another embodiment of the present invention.
  • the internal voltage generation circuit in accordance with an embodiment of the present invention includes a reference voltage generation unit 4 , a buffer unit 5 , a pad 6 , and an internal voltage trimming unit 7 .
  • the internal voltage generation circuit in accordance with an embodiment of the present invention may include the buffer unit 5 , which is not included in the reference voltage generation unit depicted in FIG. 1 .
  • the buffer unit 5 may be configured to buffer a first reference voltage VREF 1 generated by the reference voltage generation unit 4 and generate a second reference voltage VREF 2 .
  • the pad 6 outputs the second reference voltage VREF 2 buffered through the buffer unit 5 . Therefore, monitoring accuracy further increases.
  • a levels of the reference voltages are controlled to constantly maintain temperature characteristics of the reference voltages depending on the internal temperature change, which makes it possible to substantially prevent an error from occurring in the operations of the internal circuits receiving the internal voltage.

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Abstract

A reference voltage generation circuit configured to generate a reference voltage level that is compensated for based on an internal temperature change, where the reference voltage level is adjusted based on a resistance value controlled in response to a control signal.

Description

    CROSS-REFERENCES TO RELATED APPLICATIONS
  • The present application claims priority under 35 U.S.C. 119(a) to Korean Application No. 10-2011-0131649, filed on Dec. 9, 2011, in the Korean intellectual property Office, which is incorporated herein by reference in its entirety set forth in full.
    • BACKGROUND
  • Typically, a semiconductor memory device receives power supply voltage VDD and ground voltage VSS from an outside source, and generates and uses internal voltages required for internal operations. The internal voltages required for internal operations of the semiconductor memory device may include a core voltage VCORE supplied to a memory core area, a boosting voltage VPP used for driving or overdriving a word line, and a back bias voltage VBB supplied as a bulk voltage of an NMOS transistor of a memory core area.
  • Here, the core voltage VCORE may be supplied by lowering the power supply voltage VDD inputted from outside to a predetermined level. However, the boosting voltage VPP has a higher level than the power supply voltage VDD inputted from outside, and the back bias voltage VBB maintains a lower level than the ground voltage VSS inputted from outside. Therefore, charge pump circuits are needed to supply charges for the boosting voltage VPP and the back bias voltage VBB.
  • In general, internal voltages are generated by using a reference voltage. When an internal voltage has a lower level than the reference voltage, the internal voltage is driven by a power supply voltage or generated by pumping the internal voltage.
  • However, when the level of the reference voltage is changed by a PVT (Process, Voltage, Temperature) variation, temperature characteristics of the reference voltage may be changed according to an internal temperature change. Therefore, a temperature characteristic change of the reference voltage may have an effect upon the internal voltage, thereby causing an error in an operation of an internal circuit receiving the internal voltage.
    • SUMMARY
  • An embodiment of the present invention relates to an internal voltage generation circuit capable of constantly maintaining the temperature characteristic of a reference voltage according to an internal temperature change by controlling the level of the reference voltage, thereby preventing an error from occurring in an operation of an internal circuit receiving an internal voltage, and an internal voltage generation circuit using the same.
  • In one embodiment, a reference voltage generation circuit configured to generate a reference voltage level that is compensated for based on an internal temperature change, where the reference voltage level is adjusted based on a resistance value controlled in response to a control signal.
  • In another embodiment, an internal voltage generation circuit includes: a reference voltage generation unit configured to control the level of a reference voltage in response to a control signal; a pad configured to monitor the reference voltage or apply a voltage to the reference voltage; and an internal voltage trimming unit configured to receive the reference voltage and generate first and second internal voltages trimmed at different levels.
  • In another embodiment, an internal voltage generation circuit includes: a reference voltage generation unit configured to control the level of a first reference voltage in response to a control signal; a buffer unit configured to buffer the first reference voltage and generate a second reference voltage; a pad configured to monitor the second reference voltage or apply a voltage to the second reference voltage; and an internal voltage trimming unit configured to receive the second reference voltage and generate first and second internal voltages trimmed at different levels.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The above and other aspects, features and other advantages will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
  • FIG. 1 is a block diagram illustrating a configuration of an internal voltage generation circuit in accordance with an embodiment of the present invention;
  • FIG. 2 is a circuit diagram of a reference voltage generation circuit included in an internal voltage generation circuit illustrated in FIG. 1;
  • FIG. 3 is a circuit diagram of an internal voltage trimming unit included in the internal voltage generation circuit illustrated in FIG. 1;
  • FIG. 4 is a graph showing characteristic changes of a reference voltage generated by the reference voltage generation circuit of FIG. 2 depending on an internal temperature change of the reference voltage; and
  • FIG. 5 is a block diagram illustrating a configuration of an internal voltage generation circuit in accordance with another embodiment of the present invention.
    •  DESCRIPTION OF SPECIFIC EMBODIMENTS
  • Hereinafter, embodiments of the present invention will be described with reference to accompanying drawings. However, the embodiments are for illustrative purposes only and are not intended to limit the scope of the invention.
  • FIG. 1 is a block diagram illustrating a configuration of an internal voltage generation circuit in accordance with an embodiment of the present invention.
  • Referring to FIG. 1, the internal voltage generation circuit in accordance with an embodiment of the present invention includes a reference voltage generation unit 1, a pad 2, and an internal voltage trimming unit 3. The reference voltage generation unit 1 is configured to control a level of a reference voltage VREF in response to first and second control signals CNT<1:2>. The pad 2 is configured to output the reference voltage VREF for monitoring, and applying a voltage to the reference voltage VREF. The internal voltage trimming unit 3 is configured to receive the reference voltage VREF, and generate first and second internal voltages VINT1 and VINT2 trimmed at different levels. Hereafter, referring to FIGS. 2 and 3, configurations of the reference voltage generation unit 1, the pad 2, and the internal voltage generation unit 3 will be described in more detail as follows.
  • Referring to FIG. 2, the reference voltage generation unit 1 includes a current source 11, a first resistor section 12, and a second resistor section 13. The current source 11 may be implemented with a Widlar-type current source which includes MOS transistors and resistors having reverse current characteristics depending on an internal temperature change, and the current source 11 may generate a current I. The current I is outputted to a node nd11 from which the reference voltage VREF is outputted. The first resistor section 12 includes a plurality of diodes coupled between the first node nd11 and a ground voltage. The second resistor section 13 includes a resistor R11, an NMOS transistor N11, a resistor R12, and an NMOS transistor N12. The resistor R11 is coupled between the node nd11 and a node nd12. The NMOS transistor N11 operates as a switch element which is turned on to short the nodes nd11 and nd12 in response to the first control signal CNT<1>. The resistor R12 is coupled between the node nd12 and the ground voltage. The NMOS transistor N12 operates as a switch element which is turned on to short the node nd12 to the ground voltage in response to the second control signal CNT<2>.
  • The level of the reference voltage VREF generated by the reference voltage generation unit 1 configured in such a manner decreases when the resistance value of the second resistor section 13 is increased according to the first and second control signals CNT<1:2>, and increases when the resistance value of the second resistor section 13 is decreased.
  • Referring to FIG. 3, the internal voltage trimming unit 3 includes a PMOS transistor P31, a resistor R31, a resistor R32, a resistor R33, and a comparator 31. The PMOS transistor P31 operates as a driver configured to drive a node nd31 in response to a pull-up signal PU. The resistor R31 is coupled between the node nd31 and a node nd32 from which the first internal voltage VINT1 is outputted. The resistor R32 is coupled between the node nd32 and a node nd33 from which the second internal voltage VINT2 is outputted. The resistor R33 is coupled between the node nd33 and a ground voltage. The comparator 31 is configured to generate a pull-up signal PU which is enabled to a logic low level when the second internal voltage VINT2 has a lower level than the reference voltage VREF.
  • The internal voltage trimming unit 3 configured in such a manner generates the first and second internal voltages VINT1 and VINT2 having levels that are controlled according to the reference voltage VREF. That is, the voltage levels of the first and second internal voltages VINT1 and VINT2 increase when the voltage level of the reference voltage VREF is increased, and voltage levels of the first and second internal voltages VINT1 and VINT2 decrease when the voltage level of the reference voltage VREF is decreased.
  • Operation of the internal voltage generation circuit configured in such a manner will be described as follows with reference to FIG. 4.
  • Turning now to FIG. 4, which illustrates a graph showing characteristic changes of a reference voltage generated by the reference voltage generation circuit of FIG. 2 depending on an internal temperature change of the reference voltage. First, a PVT variation may cause a reference voltage VREF increase from a level V1 to a level V2, which may cause a change in the temperature characteristic of the reference voltage VREF. That is, when the reference voltage VREF corresponds to level V1, the amount of the current I at a high temperature T1 is smaller than at a low temperature T2. However, when the reference voltage VREF corresponds to the level V2, the amount of the current I at the high temperature T1 is larger than at the low temperature T2. The temperature characteristic changes of the reference voltage VREF are reflected in the first and second internal voltages VINT1 and VINT2, thereby causing an operation error of the internal circuit. Therefore, the internal voltage generation circuit in accordance with an embodiment of the present invention decreases the voltage level of the reference voltage VREF by increasing the resistance value of the second resistor section 13 according to the first and second control signals CNT<1:2>.
  • Accordingly, when a PVT variation causes the reference voltage VREF to decrease from the level V2 to the level V1, the temperature characteristic of the reference voltage VREF is changed. That is, when the reference voltage VREF corresponds to the level V2, the amount of the current I at the high temperature T1 is larger than at the low temperature T2, but when the reference voltage VREF corresponds to the level V1, the amount of the current I at the high temperature T1 is smaller than the low temperature T2. The temperature characteristic changes of the reference voltage VREF are reflected in the first and second internal voltages VINT1 and VINT2, thereby causing an operation error of the internal circuit. Therefore, the internal voltage generation circuit in accordance with an embodiment of the present invention increases a level of the reference voltage VREF by reducing the resistance value of the second resistor section 13 according to the first and second control signals CNT<1:2> to maintain a reference voltage substantially near the zero temperature coefficient point (ZTC).
  • In short, the internal voltage generation circuit in accordance with an embodiment of the present invention may control a level of the reference voltage VREF according to the first and second control signals CNT<1:2> and maintain and/or adjust the temperature characteristic of the reference voltage depending on the internal voltage change. Therefore, temperature characteristics of the first and second internal voltages VINT1 and VINT2 may be maintained to substantially prevent an error in the operations of the internal circuits.
  • FIG. 5 is a block diagram illustrating the configuration of an internal voltage generation circuit in accordance with another embodiment of the present invention.
  • Referring to FIG. 5, the internal voltage generation circuit in accordance with an embodiment of the present invention includes a reference voltage generation unit 4, a buffer unit 5, a pad 6, and an internal voltage trimming unit 7. The internal voltage generation circuit in accordance with an embodiment of the present invention may include the buffer unit 5, which is not included in the reference voltage generation unit depicted in FIG. 1. The buffer unit 5 may be configured to buffer a first reference voltage VREF1 generated by the reference voltage generation unit 4 and generate a second reference voltage VREF2. The pad 6 outputs the second reference voltage VREF2 buffered through the buffer unit 5. Therefore, monitoring accuracy further increases.
  • In accordance with embodiments of the present invention, a levels of the reference voltages are controlled to constantly maintain temperature characteristics of the reference voltages depending on the internal temperature change, which makes it possible to substantially prevent an error from occurring in the operations of the internal circuits receiving the internal voltage.
  • The embodiments of the present invention have been disclosed above for illustrative purposes. Those skilled in the art will readily appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.

Claims (14)

What is claimed is:
1. A reference voltage generation circuit configured to generate a reference voltage level that is compensated for based on an internal temperature change, where the reference voltage level is adjusted based on a resistance value controlled in response to a control signal.
2. The reference voltage generation circuit of claim 1, further comprising:
a current source configured to generate a current by compensating for the internal temperature change and output the current to an output node where the reference voltage is generated;
a first resistor unit coupled between the output node and a ground voltage; and
a second resistor unit coupled in parallel to the first resistor unit between the output node and the ground voltage and having the resistance value controlled in response to the control signal.
3. The reference voltage generation circuit of claim 2, wherein the first resistor unit comprises one or more diodes.
4. The reference voltage generation circuit of claim 2, wherein the second resistor unit comprises:
a resistor coupled between the output node and a ground voltage; and
a switch element coupled in parallel to the resistor between the output node and the ground voltage and turned on in response to the control signal.
5. An internal voltage generation circuit comprising:
a reference voltage generation unit configured to control the level of a reference voltage in response to a control signal;
a pad configured to monitor the reference voltage or apply a voltage to the reference voltage; and
an internal voltage trimming unit configured to receive the reference voltage and generate first and second internal voltages trimmed at different levels.
6. The internal voltage generation circuit of claim 5, wherein the reference voltage generation unit comprises:
a current source configured to generate a current that is compensated based on an internal temperature change, and output the generated current to an output node where a reference voltage is generated;
a first resistor section coupled between the output node and a ground voltage; and
a second resistor section coupled in parallel to the first resistor section between the output node and the ground voltage and having a resistance value controlled in response to the control signal.
7. The internal voltage generation circuit of claim 6, wherein the first resistor section comprises one or more diodes.
8. The internal voltage generation circuit of claim 6, wherein the second resistor section comprises:
a resistor coupled between the output node and a ground voltage; and
a switch element coupled in parallel to the resistor between the output node and the ground voltage and turned on in response to the control signal.
9. The internal voltage generation circuit of claim 5, wherein the internal voltage trimming unit comprises:
a driver configured to drive a first node in response to a pull-up signal;
a first resistor coupled between the first node and a second node from which the first internal voltage is outputted;
a second resistor coupled between the second node and a third node from which the second internal voltage is outputted; and
a comparator configured to compare the second internal voltage with the reference voltage and generate the pull-up signal.
10. An internal voltage generation circuit comprising:
a reference voltage generation unit configured to control a level of a first reference voltage in response to a control signal;
a buffer unit configured to buffer the first reference voltage and generate a second reference voltage;
a pad configured to monitor the second reference voltage or apply a voltage to the second reference voltage; and
an internal voltage trimming unit configured to receive the second reference voltage and generate first and second internal voltages trimmed at different levels.
11. The internal voltage generation circuit of claim 10, wherein the reference voltage generation unit comprises:
a current source configured to generate a current that is compensating for based on an internal temperature change and output the current to an output node from which the first reference voltage is generated;
a first resistor section coupled between the output node and a ground voltage; and
a second resistor section coupled in parallel to the first resistor section between the output node and the ground voltage and having a resistance value controlled in response to the control signal.
12. The internal voltage generation circuit of claim 11, wherein the first resistor section comprises one or more diodes.
13. The internal voltage generation circuit of claim 11, wherein the second resistor section comprises:
a resistor coupled between the output node and a ground voltage; and
a switch element coupled in parallel to the resistor between the output node and the ground voltage and turned on in response to the control signal.
14. The internal voltage generation circuit of claim 10, wherein the internal voltage trimming unit comprises:
a driver configured to drive a first node in response to a pull-up signal;
a first resistor coupled between the first node and a second node from which the first internal voltage is outputted;
a second resistor coupled between the second node and a third node from which the second internal voltage is outputted; and
a comparator configured to compare the second internal voltage with the reference voltage and generate the pull-up signal.
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US20150362379A1 (en) * 2014-06-17 2015-12-17 SK Hynix Inc. Temperature voltage generator
US9601209B2 (en) 2014-05-21 2017-03-21 Samsung Electronics Co., Ltd. Voltage generator and semiconductor memory device
US20190348082A1 (en) * 2018-05-10 2019-11-14 SK Hynix Inc. Reference voltage generating circuit, buffer, semiconductor apparatus, and semiconductor system using the reference voltage generating circuit
US20240053207A1 (en) * 2020-06-10 2024-02-15 SK Hynix Inc. Temperature sensor and method for controlling the temperature sensor
US12394470B2 (en) 2022-10-06 2025-08-19 Samsung Electronics Co., Ltd. Semiconductor chip capable of calibrating bias voltage supplied to write clock buffer regardless of process variation and temperature variation, and devices including the same

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US9601209B2 (en) 2014-05-21 2017-03-21 Samsung Electronics Co., Ltd. Voltage generator and semiconductor memory device
US20150362379A1 (en) * 2014-06-17 2015-12-17 SK Hynix Inc. Temperature voltage generator
US9791327B2 (en) * 2014-06-17 2017-10-17 SK Hynix Inc. Temperature voltage generator
US20190348082A1 (en) * 2018-05-10 2019-11-14 SK Hynix Inc. Reference voltage generating circuit, buffer, semiconductor apparatus, and semiconductor system using the reference voltage generating circuit
US10699754B2 (en) * 2018-05-10 2020-06-30 SK Hynix Inc. Reference voltage generating circuit, buffer, semiconductor apparatus, and semiconductor system using the reference voltage generating circuit
US11004483B2 (en) 2018-05-10 2021-05-11 SK Hynix Inc. Reference voltage generating circuit, buffer, semiconductor apparatus, and semiconductor system using the reference voltage generating circuit
US20240053207A1 (en) * 2020-06-10 2024-02-15 SK Hynix Inc. Temperature sensor and method for controlling the temperature sensor
US12078553B2 (en) * 2020-06-10 2024-09-03 SK Hynix Inc. Temperature sensor and method for controlling the temperature sensor
US12394470B2 (en) 2022-10-06 2025-08-19 Samsung Electronics Co., Ltd. Semiconductor chip capable of calibrating bias voltage supplied to write clock buffer regardless of process variation and temperature variation, and devices including the same

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