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US20130051170A1 - Semiconductor memory device - Google Patents

Semiconductor memory device Download PDF

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Publication number
US20130051170A1
US20130051170A1 US13/662,147 US201213662147A US2013051170A1 US 20130051170 A1 US20130051170 A1 US 20130051170A1 US 201213662147 A US201213662147 A US 201213662147A US 2013051170 A1 US2013051170 A1 US 2013051170A1
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Prior art keywords
conductivity type
transistor
signal
power supply
bit lines
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Abandoned
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US13/662,147
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English (en)
Inventor
Naoki Kuroda
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Panasonic Corp
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Panasonic Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out

Definitions

  • the present disclosure relates to semiconductor memory devices, and more particularly, to a semiconductor memory device in which the number of components is reduced while data destruction in a non-selected memory cell during data write operation is reduced.
  • a local SA circuit provided in the conventional hierarchical bit line architecture includes 22 components for each bit line when the local SA circuit is of single end type (see Japanese Patent Publication No. 2000-207886), and eight components for each bit line when the local SA circuit is of cross-coupled type (see K. Takeda, et al.).
  • the area overhead of the SRAM device is disadvantageously large.
  • the present disclosure describes implementations of a semiconductor memory device in which the number of components in the SA circuit while data destruction in the memory cell is reduced or prevented.
  • An example semiconductor memory device includes a first and a second signal line forming a pair of signal lines, a third and a fourth signal line forming another pair of signal lines, a memory cell connected to the first and second signal lines, and an SA circuit provided between the first and second signal lines and the third and fourth signal lines.
  • the SA circuit includes six transistors, i.e., a first transistor of a first conductivity type having a gate connected to a precharge signal, a source connected to a first power supply potential, and a drain connected to the first signal line, a second transistor of the first conductivity type having a gate connected to the precharge signal, a source connected to the first power supply potential, and a drain connected to the second signal line, a third transistor of the first conductivity type having a gate connected to the first signal line, a source connected to the first power supply potential, and a drain connected to the third signal line, a fourth transistor of the first conductivity type having a gate connected to the second signal line, a source connected to the first power supply potential, and a drain connected to the fourth signal line, a fifth transistor of a second conductivity type having a gate connected to the third signal line, a source connected to a second power supply potential, and a drain connected to the first signal line, and a sixth transistor of the second conductivity type having a gate connected to the fourth signal
  • Another example semiconductor memory device includes memory cells, bit lines each connected to corresponding ones of the memory cells, and sense amplifier circuits each connected to corresponding ones of the bit lines.
  • Each of the sense amplifier circuits has a single-end configuration and a function of writing data read from a corresponding one of the memory cells back to the corresponding bit lines, and achieves data write operation to a corresponding one of the memory cells by the function of writing data back to the corresponding bit lines.
  • the function of writing data stored by a non-selected memory cell during write operation back to the memory cell without the need of a fine timing control is provided, whereby a semiconductor memory device can be provided in which the number of components in the SA circuit is reduced while data destruction in the memory cell is reduced or prevented.
  • FIG. 1 is a block diagram showing a main configuration of a semiconductor memory device according to a first embodiment of the present disclosure.
  • FIG. 2 is a circuit diagram showing a detailed example configuration of a memory cell of FIG. 1 .
  • FIG. 3 is a circuit diagram showing a detailed example configuration of a local SA circuit of FIG. 1 .
  • FIG. 4 is a timing chart showing main operation of the semiconductor memory device of the first embodiment of the present disclosure.
  • FIG. 5 is a block diagram showing a main configuration of a semiconductor memory device according to a second embodiment of the present disclosure.
  • FIG. 6 is a circuit diagram showing a detailed example configuration of a memory cell of FIG. 5 .
  • FIG. 7 is a timing chart showing main operation of the semiconductor memory device of the second embodiment of the present disclosure.
  • FIG. 8 is a block diagram showing a main configuration of a semiconductor memory device according to a third embodiment of the present disclosure.
  • FIG. 9 is a circuit diagram showing a detailed example configuration of a local SA circuit of FIG. 8 .
  • FIG. 10 is a block diagram showing a main configuration of a semiconductor memory device according to a fourth embodiment of the present disclosure.
  • FIG. 11 is a circuit diagram showing a detailed example configuration of a local SA circuit of FIG. 10 .
  • FIG. 1 is a block diagram showing a main configuration of a semiconductor memory device according to a first embodiment of the present disclosure.
  • the semiconductor memory device of FIG. 1 includes memory cells (MCs) 1 , memory cell arrays 3 in which the memory cells 1 are arranged in a matrix, word lines WL ⁇ 0 >-WL ⁇ 3 > which are used to control input and output of data in the memory cells 1 , a row decoder 5 which selects and activates the word lines, local SA circuits 2 , local bit lines (pairs of signal lines) LBL ⁇ 0 >/NLBL ⁇ 0 >-LBL ⁇ 3 >/NLBL ⁇ 3 > which connect the memory cells 1 and the local SA circuits 2 , local SA control circuits 6 which control precharge signals PC ⁇ 0 >-PC ⁇ 1 > of the local SA circuits 2 , global bit lines (pairs of signal lines) GBL ⁇ 0 >/NGBL ⁇ 0 > and GBL ⁇ 1 >/NGBL ⁇ 1 > connected to the local SA circuits 2 , an interface (IF
  • FIG. 1 shows the semiconductor memory device having a hierarchical bit line architecture which includes the local bit lines LBL ⁇ 0 >/NLBL ⁇ 0 >-LBL ⁇ 3 >/NLBL ⁇ 3 > which are connected directly to the memory cells 1 arranged in specific groups and and have a short line length, and the global bit lines GBL ⁇ 0 >/NGBL ⁇ 0 > and GBL ⁇ 1 >/NGBL ⁇ 1 > which are provided on the memory cell arrays 3 and connected to all the local bit lines via the local SA circuits 2 and have a long line length.
  • FIG. 2 is a circuit diagram showing a detailed example configuration of the memory cell 1 of FIG. 1 .
  • the memory cell 1 includes a first cell transistor 21 a, a second cell transistor 21 b, a third cell transistor 22 a, a fourth cell transistor 22 b, a fifth cell transistor 23 a, and a sixth cell transistor 23 b.
  • the first cell transistor 21 a is a P-channel transistor having a source connected to a VDD potential, a drain connected to a first memory node, and a gate connected to a second memory node.
  • the second cell transistor 21 b is a P-channel transistor having a source connected to the VDD potential, a drain connected to the second memory node, and a gate connected to the first memory node.
  • the third cell transistor 22 a is an N-channel transistor having a source connected to a VSS potential, a drain connected to the first memory node, and a gate connected to the second memory node.
  • the fourth cell transistor 22 b is an N-channel transistor having a source connected to the VSS potential, a drain connected to the second memory node, and a gate connected to the first memory node.
  • the fifth cell transistor 23 a is an N-channel transistor having a source connected to the first memory node, a drain connected to the local bit line LBL, and a gate connected to the word line WL.
  • the sixth cell transistor 23 b is an N-channel transistor having a source connected to the second memory node, a drain connected to the local bit line NLBL, and a gate connected to the word line WL.
  • FIG. 3 is a circuit diagram showing a detailed example configuration of the local SA circuit 2 of FIG. 1 .
  • the local SA circuit 2 includes a first transistor 10 a, a second transistor 10 b, a third transistor 8 a, a fourth transistor 8 b, a fifth transistor 9 a, and a sixth transistor 9 b.
  • the first transistor 10 a is a P-channel transistor having a gate connected to the precharge signal PC, a source connected to the VDD potential, and a drain connected to the local bit line LBL.
  • the second transistor 10 b is a P-channel transistor having a gate connected to the precharge signal PC, a source connected to the VDD potential, and a drain connected to the local bit line NLBL.
  • the third transistor 8 a is a P-channel transistor having a gate connected to the local bit line LBL, a source connected to the VDD potential, and a drain connected to the global bit line GBL.
  • the fourth transistor 8 b is a P-channel transistor having a gate connected to the local bit line NLBL, a source connected to the VDD potential, and a drain connected to the global bit line NGBL.
  • the fifth transistor 9 a is an N-channel transistor having a gate connected to the global bit line GBL, a source connected to the VSS potential, and a drain connected to the local bit line LBL.
  • the sixth transistor 9 b is an N-channel transistor having a gate connected to the global bit line NGBL, a source connected to the VSS potential, and a drain connected to the local bit line NLBL.
  • the local SA circuit 2 of FIG. 3 is controlled based on the precharge signal PC, and includes the P-channel transistors 10 a and 10 b for precharging the local bit lines LBL and NLBL to a high level (a power supply potential or the VDD potential), the P-channel transistors 8 a and 8 b for transferring to the global bit lines GBL and NGBL data driven depending on the potential levels of the local bit lines LBL and NLBL, respectively, and the N-channel transistors 9 a and 9 b for transferring to the local bit lines LBL and NLBL data driven depending on the potential levels of the global bit lines GBL and NGBL, respectively.
  • Each of the pair of the P-channel transistor 8 a and the N-channel transistor 9 a and the pair of the P-channel transistor 8 b and the N-channel transistor 9 b has a feedback structure in which data is fed back, depending on the potential level.
  • FIG. 4 is a timing chart showing main operation of the semiconductor memory device of the first embodiment of the present disclosure. Write operation and read operation of the semiconductor memory device having the above configuration will be described with reference to the timing chart of FIG. 4 .
  • write operation is performed.
  • data DI 0 is input from the data input signal DI
  • the data DI 0 is transferred to the global bit lines GBL ⁇ 1 > and NGBL ⁇ 1 > selected by the IF circuit 7 .
  • precharge signal PC ⁇ 0 > goes high
  • word line WL ⁇ 0 > is activated to a high signal
  • the memory cells 1 connected to the word line WL ⁇ 0 > are connected to the respective corresponding local bit line pairs LBL ⁇ 0 >/NLBL ⁇ 0 > and LBL ⁇ 2 >/NLBL ⁇ 2 >.
  • the P-channel transistor 8 a writes high data to the global bit line GBL ⁇ 0 > (i.e., a so-called feedback function), thereby assisting in increasing the transfer rate of data to the local SA circuit 2 in addition to the normal operation. Because the global bit line NGBL ⁇ 1 > is low, the N-channel transistor 9 b in the local SA circuit 2 is not activated.
  • the global bit lines GBL ⁇ 0 > and NGBL ⁇ O> connected to the non-selected column are in a state (Hi-Z state) released from the precharged state and are on standby.
  • Hi-Z state a state released from the precharged state and are on standby.
  • the memory cell 1 and the local bit lines LBL ⁇ 0 > and NLBL ⁇ 0 > are connected together by the word line WL ⁇ 0 >, which state is a so-called half-selected state during write operation.
  • data stored by the memory cell 1 connected to the word line WL ⁇ 0 > is read out to the local bit lines LBL ⁇ 0 > and NLBL ⁇ 0 >.
  • the P-channel transistor 8 a of the local SA circuit 2 is activated to cause the global bit line GBL ⁇ 0 > to go high.
  • the N-channel transistor 9 a is activated to perform feedback operation to cause the local bit line LBL ⁇ 0 > to go low.
  • the P-channel transistor 8 b of the local SA circuit 2 is not activated, and therefore, the global bit line NGBL ⁇ 0 > is also maintained low, and the P-channel transistor 9 b is not activated, so that the local bit line NLBL ⁇ 0 > is maintained high.
  • the N-channel transistor 9 a is activated, so that by feedback operation, the local bit line LBL ⁇ 0 > is pulled down to go low.
  • data stored by the memory cell 1 causes the local bit line NLBL ⁇ 0 > to be maintained high, and therefore, the P-channel transistor 8 b of the local SA circuit 2 is not activated, and therefore, the global bit line NGBL ⁇ 0 > is also maintained low.
  • the N-channel transistor 9 b is not activated.
  • data read from the memory cell 1 is transferred to the global bit lines GBL ⁇ 0 > and NGBL ⁇ 0 >, and similarly, data is transferred to the global bit lines GBL ⁇ 1 > and NGBL ⁇ 1 >.
  • One of the two pieces of data is selected by the IF circuit 7 and is output as the output data DO 0 from the data output signal DO to circuitry external to the memory device (time C).
  • the static noise margin (SNM) of the non-selected memory cell 1 is significantly improved.
  • the N-channel transistors 9 a and 9 b in the local SA circuit 2 function as a write buffer circuit during write operation.
  • the interconnect load of the local bit line is considerably small, and only one stage of N-channel transistor is provided. Therefore, a sufficient level of write performance can be achieved, and a large driver size is not required, whereby the area can be effectively reduced.
  • the signal transferred to the global bit line selected during write operation may be a control signal for the N-channel transistors 9 a and 9 b for writing data to the memory cell 1 via the local bit line, and therefore, a high level of drive performance is not required.
  • the control signal transferred to the global bit line low (ground potential or VSS) precharge is used on the global bit line, and therefore, high data only needs to be driven.
  • the performance of the N-channel transistor included in the driver circuit can be further reduced, and therefore, it is expected that the area can be advantageously reduced.
  • the driver circuit can assist the global bit line in going high, whereby the speed of transmission of the control signal can be increased, and the area of the driver circuit can be reduced.
  • write operation of the SRAM memory cell typically tends to be most difficult under processing conditions that the threshold voltage of the P-channel transistor is low and the threshold voltage of the N-channel transistor is high.
  • the speed can be advantageously increased compared to when the bit line having a large load is driven by the N-channel transistor.
  • the write performance can be improved compared to the conventional art.
  • low data read to the local bit line can be transferred to the global bit line by the P-channel transistor without an unnecessary timing control. Therefore, in particular, this is considerably effective compared to the difficulty in the control of activation timing of a conventional cross-coupled SA circuit during high-speed operation, and high-speed operation can be achieved while the number of components can be reduced, and therefore, the area can be effectively reduced.
  • the local bit lines are pulled down by the feedback function of the N-channel transistors 9 a and 9 b, resulting in higher-speed read operation which may assist in read operation of low data to the local bit lines.
  • the SNM can be significantly improved by the restore function which can be achieved by the local SA circuit 2 in the non-selected memory cell.
  • the local SA circuit 2 of FIG. 3 can be implemented by a small number of components, and operation can be achieved without complicated activation timing (timing-free operation), whereby a reduction in area and an increase in speed can be simultaneously achieved.
  • the speed of the memory device can be effectively increased.
  • the local SA circuit 2 of FIG. 3 is used in a bit line configuration which is not of hierarchical type on the memory cell array 3 , the area can be effectively reduced and the control timing can be effectively facilitated.
  • the local SA circuit 2 may be provided between the separated memory cell arrays 3 .
  • the number of layout separation regions between the local SA circuit 2 and the memory cell array 3 can be halved, whereby the area can be effectively reduced.
  • precharge signal PC ⁇ 0 > is high in this embodiment, all of the precharge signals PC ⁇ 0 >-PC ⁇ 1 > may be simultaneously high in order to reduce or avoid an increase in a through current during write operation.
  • SRAM memory cell is illustrated in this embodiment, the present disclosure is, of course, applicable to any memory devices that require similar memory operation.
  • FIG. 5 is a block diagram showing a main configuration of a semiconductor memory device according to a second embodiment of the present disclosure.
  • FIG. 6 is a circuit diagram showing a detailed example configuration of a memory cell 11 of FIG. 5 .
  • the second embodiment is clearly different from the first embodiment in that the memory cell 11 of the second embodiment includes word lines WLA and WLB shown in FIG. 6 .
  • the memory cell 11 includes a first cell transistor 21 a, a second cell transistor 21 b, a third cell transistor 22 a, a fourth cell transistor 22 b, a fifth cell transistor 23 a, and a sixth cell transistor 23 b.
  • the first cell transistor 21 a is a P-channel transistor having a source connected to the VDD potential, a drain connected to the first memory node, and a gate connected to the second memory node.
  • the second cell transistor 21 b is a P-channel transistor having a source connected to the VDD potential, a drain connected to the second memory node, and a gate connected to the first memory node.
  • the third cell transistor 22 a is an N-channel transistor having a source connected to the VSS potential, a drain connected to the first memory node, and a gate connected to the second memory node.
  • the fourth cell transistor 22 b is an N-channel transistor having a source connected to the VSS potential, a drain connected to the second memory node, and a gate connected to the first memory node.
  • the fifth cell transistor 23 a is an N-channel transistor having a source connected to the first memory node, a drain connected to the local bit line LBL, and a gate connected to the first word line WLA.
  • the sixth cell transistor 23 b is an N-channel transistor having a source connected to the second memory node, a drain connected to the local bit line NLBL, and a gate connected to the second word line WLB different from the first word line WLA.
  • FIG. 7 is a timing chart showing main operation of the semiconductor memory device of the second embodiment of the present disclosure. Read operation of the semiconductor memory device having the above configuration will be described with reference to the timing chart of FIG. 7 .
  • a multiport memory device can be easily obtained.
  • a multiport memory device can be implemented using the memory cell 11 of FIG. 6 including six transistors. Therefore, the area can be significantly reduced compared to a conventional multiport memory device including eight transistors.
  • FIG. 8 is a block diagram showing a main configuration of a semiconductor memory device according to a third embodiment of the present disclosure.
  • FIG. 9 is a circuit diagram showing a detailed example configuration of a local SA circuit 13 A of FIG. 8 .
  • the local SA circuit 13 A of FIG. 9 and a local SA control circuit 12 are blocks clearly different from those of the first embodiment of FIG. 1 .
  • the local SA circuit 13 A of FIG. 9 is the above local SA circuit 2 in which an additional N-channel transistor 14 is provided at the sources of the N-channel transistors 9 a and 9 b, and is controlled based on a control signal NSE generated by the local SA control circuit 12 .
  • the control signal NSE ⁇ 0 > is a column selection signal, and may have the same logical value as that of the precharge signal PC ⁇ 0 >, and may go high at the same timing as or slightly later than the precharge signal PC ⁇ 0 >, and go low at the same timing as that of the precharge signal PC ⁇ 0 >.
  • the other control signal NSE ⁇ 1 > is maintained low.
  • the control signal NSE ⁇ 1 > other than the control signal NSE ⁇ 0 > connected to the local SA circuit 13 A connected to the selected memory cell 1 is maintained low.
  • precharge signal PC ⁇ 0 > is high in this embodiment, all of the precharge signals PC ⁇ 0 >-PC ⁇ 1 > may be simultaneously high in order to reduce or avoid an increase in a through current during write operation.
  • the control signal NSE may, of course, be generated by the logical product of the column selection signal and the timing control signal required for memory operation.
  • FIG. 10 is a block diagram showing a main configuration of a semiconductor memory device according to a fourth embodiment of the present disclosure.
  • FIG. 11 is a circuit diagram showing a detailed example configuration of a local SA circuit 13 B of FIG. 10 .
  • the local SA circuit 13 B of FIG. 11 and a local SA control circuit 12 are blocks clearly different from those of the first embodiment of FIG. 1 .
  • the local SA circuit 13 B of FIG. 11 is the above local SA circuit 2 in which a control signal NSE is connected to the sources of the N-channel transistors 9 a and 9 b.
  • the control signal NSE ⁇ 0 > is, for example, a logical signal derived from a column selection signal, and may have a logical value opposite to that of the precharge signal PC ⁇ 0 >, and may go low at the same timing as or slightly later than the precharge signal PC ⁇ 0 >, and go high at the same timing as that of the precharge signal PC ⁇ 0 >.
  • the other control signal NSE ⁇ 1 > is maintained high.
  • the control signal NSE ⁇ 1 > other than the control signal NSE ⁇ 0 > connected to the local SA circuit 13 B connected to the selected memory cell 1 is maintained high.
  • the N-channel transistor 14 of the local SA circuit 13 A of the third embodiment can be removed, whereby the area reduction effect of the first embodiment and the low power consumption effect of the third embodiment can be simultaneously achieved.
  • the precharge signal PC ⁇ 0 > is high in this embodiment, all of the precharge signals PC ⁇ 0 >-PC ⁇ 1 > may be simultaneously high in order to reduce or avoid an increase in a through current during write operation.
  • the first-fourth embodiments have been described.
  • the first-fourth embodiments may be implemented in combination in any manner.
  • the configuration of FIG. 3 , 9 , or 11 may be used in the global SA circuit.
  • the semiconductor memory device of the present disclosure has the advantage that the number of components in the SA circuit can be reduced while data destruction of the memory cell is reduced or prevented, and is useful, for example, for a system LSI circuit including a large number of various memory devices.

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130229887A1 (en) * 2010-12-16 2013-09-05 Panasonic Corporation Semiconductor memory device
US20140204656A1 (en) * 2013-01-22 2014-07-24 Stmicroelectronics International N.V. Low voltage dual supply memory cell with two word lines and activation circuitry
GB2512844A (en) * 2013-04-08 2014-10-15 Surecore Ltd Reduced power memory unit
US9761289B1 (en) 2016-06-13 2017-09-12 International Business Machines Corporation Managing semiconductor memory array leakage current
FR3075445A1 (fr) * 2017-12-19 2019-06-21 Commissariat A L'energie Atomique Et Aux Energies Alternatives Circuit memoire partitionne adapte a mettre en oeuvre des operations de calcul

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103617808A (zh) * 2013-12-06 2014-03-05 广东博观科技有限公司 一种sram的读取、缓存电路和方法
TWI552162B (zh) 2014-07-31 2016-10-01 Zhi-Cheng Xiao Low power memory
US20160189755A1 (en) 2015-08-30 2016-06-30 Chih-Cheng Hsiao Low power memory device
US10403338B2 (en) 2015-08-30 2019-09-03 Chih-Cheng Hsiao Low power memory device with column and row line switches for specific memory cells

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3248468B2 (ja) * 1997-10-30 2002-01-21 日本電気株式会社 半導体記憶装置
JP2000207886A (ja) * 1999-01-08 2000-07-28 Seiko Epson Corp 半導体記憶装置
US6587384B2 (en) * 2001-04-21 2003-07-01 Hewlett-Packard Development Company, L.P. Multi-function serial I/O circuit
JP3913709B2 (ja) * 2003-05-09 2007-05-09 株式会社東芝 半導体記憶装置
JP2007004888A (ja) 2005-06-23 2007-01-11 Toshiba Corp 半導体記憶装置及びその制御方法
WO2008032549A1 (fr) 2006-09-13 2008-03-20 Nec Corporation Dispositif de stockage semiconducteur
JP2008146734A (ja) * 2006-12-08 2008-06-26 Toshiba Corp 半導体記憶装置
JP2010113793A (ja) * 2008-10-10 2010-05-20 Renesas Electronics Corp 半導体記憶装置
WO2012081159A1 (ja) * 2010-12-16 2012-06-21 パナソニック株式会社 半導体記憶装置

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130229887A1 (en) * 2010-12-16 2013-09-05 Panasonic Corporation Semiconductor memory device
US8830774B2 (en) * 2010-12-16 2014-09-09 Panasonic Corporation Semiconductor memory device
US20140204656A1 (en) * 2013-01-22 2014-07-24 Stmicroelectronics International N.V. Low voltage dual supply memory cell with two word lines and activation circuitry
US9165642B2 (en) * 2013-01-22 2015-10-20 Stmicroelectronics International N.V. Low voltage dual supply memory cell with two word lines and activation circuitry
GB2512844A (en) * 2013-04-08 2014-10-15 Surecore Ltd Reduced power memory unit
US9406351B2 (en) 2013-04-08 2016-08-02 Surecore Limited Memory with local-/global bit line architecture and additional capacitance for global bit line discharge in reading
GB2512844B (en) * 2013-04-08 2017-06-21 Surecore Ltd Reduced Power Memory Unit
US9761289B1 (en) 2016-06-13 2017-09-12 International Business Machines Corporation Managing semiconductor memory array leakage current
US9792967B1 (en) * 2016-06-13 2017-10-17 International Business Machines Corporation Managing semiconductor memory array leakage current
FR3075445A1 (fr) * 2017-12-19 2019-06-21 Commissariat A L'energie Atomique Et Aux Energies Alternatives Circuit memoire partitionne adapte a mettre en oeuvre des operations de calcul
EP3503105A1 (fr) * 2017-12-19 2019-06-26 Commissariat à l'Energie Atomique et aux Energies Alternatives Circuit mémoire partitionné adapté à mettre en oeuvre des opérations de calcul
US10803927B2 (en) 2017-12-19 2020-10-13 Commissariat à l'énergie atomique et aux énergies alternatives Partitioned memory circuit capable of implementing calculation operations

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JP5798120B2 (ja) 2015-10-21
US20130229887A1 (en) 2013-09-05
WO2012081159A1 (ja) 2012-06-21
JPWO2012081159A1 (ja) 2014-05-22

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