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US20130026511A1 - Transfer-bonding method for the light emitting device and light emitting device array - Google Patents

Transfer-bonding method for the light emitting device and light emitting device array Download PDF

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Publication number
US20130026511A1
US20130026511A1 US13/557,231 US201213557231A US2013026511A1 US 20130026511 A1 US20130026511 A1 US 20130026511A1 US 201213557231 A US201213557231 A US 201213557231A US 2013026511 A1 US2013026511 A1 US 2013026511A1
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Prior art keywords
light emitting
substrate
device layers
layer
emitting devices
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US13/557,231
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English (en)
Inventor
Wen-Yung Yeh
Chia-Hsin Chao
Ming-Hsien Wu
Kuang-Yu Tai
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Industrial Technology Research Institute ITRI
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Industrial Technology Research Institute ITRI
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Priority claimed from TW101118745A external-priority patent/TWI521690B/zh
Application filed by Industrial Technology Research Institute ITRI filed Critical Industrial Technology Research Institute ITRI
Priority to US13/557,231 priority Critical patent/US20130026511A1/en
Assigned to INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE reassignment INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHAO, CHIA-HSIN, TAI, KUANG-YU, WU, MING-HSIEN, YEH, WEN-YUNG
Publication of US20130026511A1 publication Critical patent/US20130026511A1/en
Priority to US14/583,594 priority patent/US9306117B2/en
Priority to US14/970,548 priority patent/US9825013B2/en
Abandoned legal-status Critical Current

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    • H10W90/00—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/811—Bodies having quantum effect structures or superlattices, e.g. tunnel junctions
    • H10H20/812—Bodies having quantum effect structures or superlattices, e.g. tunnel junctions within the light-emitting regions, e.g. having quantum confinement structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/822—Materials of the light-emitting regions
    • H10H20/824—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP
    • H10H20/825—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP containing nitrogen, e.g. GaN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/83—Electrodes
    • H10H20/831—Electrodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/852—Encapsulations
    • H10H20/853—Encapsulations characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/855—Optical field-shaping means, e.g. lenses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/10—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00
    • H10H29/14—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00 comprising multiple light-emitting semiconductor components
    • H10H29/142—Two-dimensional arrangements, e.g. asymmetric LED layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/84—Coatings, e.g. passivation layers or antireflective coatings

Definitions

  • the technical field relates to a manufacturing method for light emitting devices array.
  • Inorganic light emitting diode display has features of self-luminous, high brightness and so on, and therefore has been widely applied in the fields of illumination, display and so forth monolithic micro-display has been constantly faced with a bottleneck of colorizing technology.
  • a conventional technology utilizing an epitaxial technique in a single light emitting diode chip to manufacture a plurality of light emitting layers capable of emitting different colored lights has already been provided, such that the single light emitting diode chip can provide different colored lights. Because lattice constants of the light emitting layers capable of emitting different colored lights are different, growth of the light emitting layers on a same substrate is difficult.
  • another conventional technology has provided a colorizing technique utilizing a light emitting diode chip in collocation with different color conversion materials, but this technology is still facing problems of low conversion efficiency of the color conversion materials, coating uniformity and so forth.
  • the transfer-bonding technique of the light emitting diode has a better chance to enhance brightness and display quality of a monolithic micro-display. Rapidly and efficiently transfer-bonding the light emitting diode to a circuit substrate of the monolithic micro-display is in fact one of the recently concerned issues of industry.
  • One of exemplary embodiments provides a transfer-bonding method for light emitting devices and a light emitting device array.
  • One of exemplary embodiments provides a transfer-bonding method for light emitting devices including: a plurality of light emitting devices is formed over a first substrate and is arranged in array, wherein each of the light emitting devices includes a device layer and a sacrificial pattern sandwiched between the device layer and the first substrate; a protective layer is formed over the first substrate to selectively cover parts of the light emitting devices, and other parts of the light emitting devices are uncovered by the protective layer; the device layers uncovered by protective layer are bonded with a second substrate; and the sacrificial patterns uncovered by the protective layer are removed, so that parts of the device layers are separated from the first substrate and are transfer-bonded to the second substrate.
  • One of exemplary embodiments provides a light emitting device array including a circuit substrate and a plurality of device layers capable of emitting different colored lights, wherein the circuit substrate has a plurality of bonding pads and a plurality of conductive bumps over the bonding pads, the device layers capable of emitting different colored lights are electrically connected with the circuit substrate through the conductive bumps and the bonding pads.
  • the device layers capable of emitting different colored lights have different thicknesses, and the conductive bumps bonded with the device layers capable of emitting different colored lights have different heights, such that top surfaces of the device layers capable of emitting different colored lights device layer are located on a same level of height.
  • One of exemplary embodiments provides a light emitting device array including a circuit substrate and a plurality of device layers capable of emitting different colored lights, wherein the circuit substrate has a plurality of bonding pads and a plurality of conductive bumps over the bonding pads, and the device layers capable of emitting different colored lights are electrically connected with the circuit substrate through the conductive bumps and the bonding pads.
  • the device layers capable of emitting different colored lights have different thicknesses, and the conductive bumps bonded with the device layers capable of emitting different colored lights have different heights, such that top surfaces of the device layers capable of emitting different colored lights are located on a different level of heights.
  • An embodiment is able to rapidly and efficiently transfer-bond the light emitting devices from a substrate to another substrate so as to facilitate an application of the light emitting devices in the field of micro-display.
  • FIG. 1 A to FIG. 1K are schematic flow chat diagrams illustrating a transfer-bonding method for light emitting devices according to a first embodiment.
  • FIG. 2 , FIG. 3 and FIG. 4 illustrate bonding sequences of the light emitting devices and a second substrate.
  • FIG. 5A to FIG. 5C illustrate a method for manufacturing sacrificial patterns.
  • FIG. 6A to FIG. 6C illustrate another method for manufacturing sacrificial patterns.
  • FIG. 7A to FIG. 7K are schematic flow chat diagrams illustrating a transfer-bonding method for light emitting devices according to a second embodiment.
  • FIG. 8A to FIG. 8K are schematic flow chat diagrams illustrating a transfer-bonding method for light emitting devices according to a third embodiment.
  • FIG. 1A to FIG. 1K are schematic flow chat diagrams illustrating a transfer-bonding method for light emitting devices according to a first embodiment.
  • a plurality of light emitting devices 100 is formed over a first substrate SUB 1 and are arranged in array, wherein each of the light emitting devices 100 includes a device layer 110 and a sacrificial pattern 120 sandwiched between the device layer 110 and the first substrate SUB 1 .
  • the device layers 110 located over the same first substrate SUB 1 are suitable for emitting same colored lights.
  • the device layers 110 formed over the first substrate SUB 1 are red light emitting diodes, green light emitting diodes or blue light emitting diodes.
  • every device layer 110 has already included an electrode (not shown).
  • a protective layer PV is formed over the first substrate SUB 1 to selectively cover parts of the light emitting devices 100 , while other parts of the light emitting devices 100 are uncovered by the protective layer PV.
  • the protective layer PV is, for example, a photoresist material or other dielectric material, such that the light emitting devices 100 covered by the protective layer PV, in a subsequent removal process of the sacrificial patterns 120 , is not separated from the first substrate SUB 1 .
  • a material of the protective layer PV may be a polyimide or other polymer material, and the material of the protective layer PV may also be a silicon oxide (SiOx), a silicon nitride (SiNx) or other inorganic dielectric material.
  • the device layers 110 uncovered by the protective layer PV are bonded with a second substrate SUB 2 , and the sacrificial patterns 120 (as shown in FIG. 1C ) uncovered by the protective layer PV are removed, so that parts of the device layers 110 are separated from the first substrate SUB 1 and are transfer-bonded to the second substrate SUB 2 (as shown in FIG. 1D ).
  • the second substrate SUB 2 is, for example, a circuit substrate (e.g., a complementary metal oxide semiconductor chip having a plurality of bonding pads PAD) in a monolithic micro-display, and the device layers 110 uncovered by the protective layer PV are bonded with the bonding pads PAD over the second substrate SUB 2 through the conductive bumps B.
  • the conductive bumps B are gold bumps or other alloy bumps, and the bonding (electrical connection) between the conductive bumps B and the bonding pads PAD over the second substrate SUB 2 are achieved through reflow or other soldering process.
  • the protective layer PV is able to effectively and directly control a distance between the first substrate SUB 1 and the second substrate SUB 2 , so as to avoid a phenomena of excessive press fit.
  • the protective layer PV provides a function of bonding stop and thus a process control is much easier.
  • the removal process of the sacrificial pattern is, for example, wet etch.
  • a choice of etchant is related to the material of the protective layer PV, an etching rate of the chosen etchant on the sacrificial pattern 120 has to be higher than an etching rate on the protective layer PV, so as to ensure the device layers 110 and the sacrificial patterns 120 covered by the protective layer PV are not to be damaged by the etchant.
  • FIG. 1A to FIG. 1D have briefly illustrated a process of transfer-bonding the light emitting devices 100 from the first substrate SUB 1 to the second substrate SUB 2 .
  • the present embodiment is able to selectively perform the manufacturing process steps illustrated in FIG. 1E to FIG. 1K .
  • a plurality of light emitting devices arranged in array 100 ′ are formed over another first substrate SUB 1 ′, wherein each of the light emitting device 100 ′ includes a device layer 110 ′ and a sacrificial pattern 120 ′ sandwiched between the device layer 110 ′ and the first substrate SUB 1 ′.
  • device layers 110 ′ located over the first substrate SUB 1 ′ are suitable for emitting same colored lights.
  • the device layers 110 ′ over the first substrate SUB 1 ′ all are red light emitting diodes, green light emitting diodes or blue light emitting diodes.
  • the device layer 110 ′ and the device layers 110 are suitable for respectively emitting different colors of light.
  • a protective layer PV′ is formed over the first substrate SUB 1 ′ to selectively cover parts of the light emitting devices 100 ′, while other parts of the light emitting devices 100 ′ are uncovered by the protective layer PV′.
  • the protective layer PV′ in FIG. 1E has the same function as the protective layer PV in FIG. 1B , and thus is not repeated herein.
  • the device layers 110 ′ uncovered the by protective layer PV′ are bonded with a second substrate SUB 2 , and the sacrificial patterns 120 ′ (as shown in FIG. 1 F) uncovered by the protective layer PV′ are removed, so that parts of the device layers 110 ′ are separated from the first substrate SUB 1 ′ and are transfer-bonded to the second substrate SUB 2 (as shown in FIG. 1G ).
  • the device layers 110 ′ uncovered by the protective layer PV′ is, for example, bonded with a plurality of bonding pads PAD over the second substrate SUB 2 through a plurality of conductive bumps B′.
  • the conductive bumps B′ are gold bumps or other alloy bumps, and the bonding (electrical connection) between the conductive bumps B′ and the bonding pads PAD over the second substrate SUB 2 are achieved through reflow or other soldering process.
  • a plurality of light emitting devices arranged in array 100 ′′ is formed over another first substrate SUB 1 ′′, wherein each of the light emitting devices 100 ′′ includes a device layer 110 ′′ and a sacrificial pattern 120 ′′ sandwichted between the device layer 110 ′′ and the first substrate SUB 1 ′′.
  • the device layers 110 ′′ located over the same first substrate SUB 1 ′′ are suitable for emitting same colored lights.
  • the device layer 110 ′′ over the first substrate SUB 1 ′′ all are red light emitting diodes, green light emitting diodes or blue light emitting diodes.
  • the device layers 110 ′′, the device layers 110 ′ and the device layers 110 are suitable for respectively emitting different colors of light.
  • a protective layer PV′′ is formed on the first substrate SUB 1 ′′ to selectively cover parts of the light emitting devices 100 ′′, while other parts of the light emitting devices 100 ′′ are uncovered by the protective layer PV′′.
  • the protective layer PV′′ in FIG. 1E is has the same function as the protective layer PV in FIG. 1B , and thus is not repeated herein.
  • the device layers 110 ′′ uncovered by the protective layer PV′′ are bonded with a second substrate SUB 2 , and the sacrificial patterns 120 ′′ uncovered by the protective layer PV′′ are removed, so that parts of the device layers 110 ′′ are separated from the first substrate SUB 1 ′′ and are transfer-bonded to the second substrate SUB 2 (as shown in FIG. 1G ).
  • the device layer 110 ′′ uncovered by the protective layer PV′′ are, for example, bonded with a plurality of bonding pads PAD over the second substrate SUB 2 through a plurality of conductive bumps B′′.
  • the conductive bumps B′′ are gold bumps or other alloy bumps, and the bonding between the conductive bumps B′′ and the bonding pads PAD over the second substrate SUB 2 is achieved through reflow or other soldering process.
  • the device layers 110 , the device layers 110 ′ and the device layers 110 ′′ are transfer-bonded to the second substrate SUB 2 .
  • a total thickness of the device layers 110 and the conductive bumps B is smaller than a total thickness of the device layers 110 ′ and the conductive bumps B′, and the total thickness of the device layers 110 ′ and the conductive bumps B′ is smaller than a total thickness of the device layers 110 ′′ and the conductive bumps B′′.
  • the device layers 110 ′′ during the process of transfer-bonding to the second substrate SU 2 B are not to be interfered by the device layers 110 .
  • the device layers 110 ′′′ during the transfer-bonding process to the second substrate SU 2 B are not to be interfered by the device layers 110 ′.
  • the present embodiment in order to prevent abnormal short-circuit between the device layers 110 , 110 ′, 110 ′′, the present embodiment firstly form an insulating layer IN over the second substrate SUB 2 to fill in between the device layers 110 , 110 ′, 110 ′′, and then a common electrode COM is formed on the device layers 110 , 110 ′, 110 ′′ and the insulating layer IN.
  • the present embodiment is able to form a planarized layer PLN on the common electrode COM, and after the manufacturing of the planarized layer PLN is completed, the present embodiment is able to selectively form a black matrix BM and/or a micro-lens array MLA on the planarized layer PLN.
  • the black matrix BM has a plurality of openings AP, and each of the openings AP is respectively located above at least one of the device layers 110 , 110 ′, 110 ′′.
  • the micro-lens array MLA includes a plurality of micro-lenses ML arranged in array, and each of the micro-lenses ML is respectively located above at least one of the device layers 110 , 110 ′, 110 ′′.
  • Each of the micro-lenses ML is respectively located the openings AP therein, and is corresponded to at least one of the device layers 110 , 110 ′, 110 ′′.
  • the present embodiment adopts a coordination of the sacrificial patterns 120 , 120 ′, 120 ′′, the protective layers PV, PV′, PV′′ and the conductive bumps B, B′, B′′, the present embodiment is able to very efficiently transfer-bond the different device layers 110 , 110 ′, 110 ′′ to the second substrate SUB 2 .
  • the present embodiment provides the bonding sequences illustrated in FIG. 2 , FIG. 3 and FIG. 4 .
  • the bonding sequences illustrated in FIG. 2 , FIG. 3 and FIG. 4 all of the light emitting devices may be smoothly transfer-bonded to the second substrate SUB 2 without a problem of still remaining parts of the light emitting device over the first substrate SUB 1 (or the first substrate SUB 1 ′, SUB 1 ′′).
  • the red light emitting devices 110 R, the green light emitting devices 110 G and the blue light emitting devices 110 B may be rapidly and efficiently transfer-bonded from the first substrates SUB 1 to the second substrates SUB 2 without the problem of still remaining parts of the light emitting device over the first substrate SUB 1 .
  • FIG. 5A to FIG. 5C illustrate a method for manufacturing sacrificial patterns.
  • a sacrificial layer 120 a and a semiconductor epitaxial layer 110 a are formed on the first substrate SUB 1 , wherein the first substrate SUB 1 is, for example, a sapphire substrate, and the sacrificial layer 120 a is, for example, a zinc oxide (ZnO) epitaxial layer, a AlGaN epitaxial layer, a AlInN epitaxial layer, or so forth formed by an epitaxial process.
  • ZnO zinc oxide
  • the semiconductor epitaxial layer 110 a and the sacrificial layer 120 a are patterned in order to form a plurality of device layers 110 and a plurality of sacrificial patterns 120 sandwiched between the device layers 110 and the first substrate SUB 1 .
  • a process of patterning the semiconductor epitaxial layer 110 a and the sacrificial layer 120 a is, for example, a photolithography and etching process.
  • the sacrificial patterns 120 uncovered by the protective layer PV may be removed by the etchant, such that the device layers 110 uncovered by the protective layer PV are separated from the first substrate SUB 1 .
  • an etchant to be used includes a phosphoric acid (H 3 PO 4 ), a hydrochloric acid (HCl) or other acidic solution.
  • an etchant to be used includes a potassium hydroxide (KOH), a nitric acid (HNO 3 ) or other solution.
  • FIG. 6A to FIG. 6C illustrate another method for manufacturing sacrificial patterns.
  • a patterned sacrificial layer 120 b is firstly formed on the first substrate SUB 1 , and then a semiconductor epitaxial layer 110 a is formed on the patterned sacrificial layer 120 b and the first substrate SUB 1 , wherein the first substrate SUB 1 is, for example, a sapphire substrate, and the patterned sacrificial layer 120 b is, for example, a zinc oxide (ZnO) epitaxial layer, a AlGaN epitaxial layer, a AlInN epitaxial layer, or so forth formed through the epitaxial process.
  • ZnO zinc oxide
  • the semiconductor epitaxial layer 110 a is patterned in order to form a plurality of device layers 110 and a plurality of sacrificial patterns or sacrificial islands 120 b embedded between the device layers 110 and the first substrate SUB 1 .
  • the process of patterning the semiconductor epitaxial layer 110 a is, for example, the photolithography and etching process.
  • the sacrificial patterns 120 b uncovered by the protective layer PV may be removed by the etchant, so that the device layers 110 uncovered by the protective layer PV can be easily separated from the first substrate SUB 1 .
  • an etchant to be used includes a phosphoric acid (H 3 PO 4 ), a hydrochloric acid (HCl) or other acidic solution.
  • an etchant to be used includes a potassium hydroxide (KOH), a nitric acid (HNO 3 ) or other solution.
  • FIG. 7A to FIG. 7K are schematic flow chat diagrams illustrating a transfer-bonding method for light emitting devices according to a second embodiment.
  • a first type doped semiconductor layer 210 a a light emitting layer 210 b and a second type doped semiconductor layer 210 c are formed on a growth substrate SUB.
  • the first type doped semiconductor layer 210 a is, for example, a N-type doped GaN epitaxial layer formed through the epitaxial process
  • the light emitting layer 210 b is, for example, a single or multiple quantum well light emitting layer formed through the epitaxial process
  • the second type doped semiconductor layer 210 c is, for example, a P-type doped GaN epitaxial layer formed through the epitaxial process.
  • a sacrificial layer 120 a is formed on a first substrate SUB 1 , and the second type doped semiconductor layer 210 c is temporarily bonded with the sacrificial layer 120 a.
  • the first type doped semiconductor layer 210 a and the growth substrate SUB are separated.
  • a process of separating the first type doped semiconductor layer 210 a and the growth substrate SUB includes a laser lift-off technique.
  • one of ordinary skill in the art may selectively perform a thinning process of first type doped semiconductor layer 210 a (e.g., grinding or back etching), or to manufacture the photonic crystal on the first type doped semiconductor layer 210 a.
  • the first type semiconductor layer 210 a , the light emitting layer 210 b , the second type semiconductor layer 210 c , and the sacrificial layer 120 a are patterned in order to form a plurality of first type semiconductor patterns 210 a′ , a plurality of light-emitting patterns 210 b′ , a plurality of second type semiconductor patterns 210 c′ and the sacrificial patterns 120 .
  • a plurality of electrodes 210 d are formed over the first type semiconductor patterns 210 a′ , wherein the first type semiconductor patterns 210 a′ , the light-emitting patterns 210 b′ , the second type semiconductor patterns 210 c′ , and the electrodes 210 d located on a same sacrificial pattern 120 constitute a device layer 210 .
  • a protective layer PV is formed over the first substrate SUB 1 to selectively cover parts of the device layers 210 and the sacrificial patterns 120 , wherein parts of the device layers 210 and the sacrificial patterns 120 are uncovered by the protective layer PV.
  • the protective layer PV is, for example, a photoresist material or other dielectric material, so as to ensure the device layers 210 covered by the protective layer PV are not to be separated from the first substrate SUB 1 during a subsequent removal process of the sacrificial patterns 120 .
  • a material of the protective layer PV may be a polyimide or other polymer material, and the material of the protective layer PV may also be a silicon oxide (SiOx), a silicon nitride (SiNx) or other inorganic dielectric material.
  • a second substrate SUB 2 is provided, and the second substrate SUB 2 is, for example, a circuit substrate (e.g., a complementary metal oxide semiconductor chip having a plurality of bonding pads PAD) in a monolithic micro-display.
  • the device layers 210 uncovered by the protective layer PV are bonded with the second substrate SUB 2 , and the sacrificial patterns 120 uncovered by the protective layer PV are removed, so that parts of the device layers 110 are separated from the first substrate SUB 1 and are transfer-bonded to the second substrate SUB 2 .
  • the device layer 210 uncovered by the protective layer PV are, for example, bonded the bonding pads PAD over the second substrate SUB 2 through the conductive bumps B.
  • the conductive bumps B are gold bumps or other alloy bumps, and the bonding (electrical connection) between the conductive bumps B and the bonding pads PAD over the second substrate SUB 2 are achieved through reflow or other soldering process.
  • the protective layer PV is able to control a distance between the first substrate SUB 1 and the second substrate SUB 2 , so as to avoid a phenomenon of excessive press fit.
  • the protective layer PV provides a function of bonding stop and thus a process control is easier.
  • the device layers 210 are transfer-bonded to the second substrate SUB 2 , one of ordinary skill in the art may selectively repeat the aforementioned steps illustrated in FIG. 7A to FIG. 7G for at least once, so as to transfer-bond the device layers 210 ′ and the device layers 210 ′′ to the second substrate SUB 2 . Since the device layers 210 , 210 ′, 210 ′′ can emit different colored lights (e.g., a combination of red light, blue light, green light), the device layers 210 , 210 ′, 210 ′′ over the second substrate SUB 2 can provide a function of full-color display.
  • the device layers 210 , 210 ′, 210 ′′ over the second substrate SUB 2 can provide a function of full-color display.
  • the device layers 210 , 210 ′, 210 ′′ capable of emitting different colored lights have different thicknesses, and the conductive bumps B, B′, B′′ bonded with the device layers 210 , 210 ′, 210 ′′ also have different heights, top surfaces of the device layers 210 , 210 ′, 210 ′′ can be located on a same level of height.
  • the present embodiment does not limit the top surfaces of the device layers 210 , 210 ′, 210 ′′ must be located on a same level of height, such that through adjusting the heights of the conductive bumps B, B′, B′′, the top surfaces of the device layers 210 , 210 ′, 210 ′′ may be respectively located on different level of heights.
  • a planar insulating layer PLN′ (as shown in FIG. 7I ) are formed in between the device layers 210 , 210 ′, 210 ′′ over the second substrate SUB 2 , and then a common electrode COM is formed on the device layers 210 , 210 ′, 210 ′′ and the planar insulating layer PLN′.
  • a black matrix BM is further formed on the common electrode COM, wherein the black matrix BM has a plurality of openings AP, and each of the openings AP is respectively located above one of the device layers 210 , 210 ′, 210 ′′.
  • the black matrix BM may selectively be a good conductive shading material. Since the black matrix BM is disposed on the common electrode COM, the black matrix BM is able to further reduce a resistance of the common electrode COM in order to further enhance light emitting efficiencies of the device layers 210 , 210 ′, 210 ′′.
  • the present embodiment is able to selectively form a micro-lens array MLA above the device layers 210 , 210 ′, 210 ′′, wherein the micro-lens array MLA includes a plurality of micro-lenses ML arranged in array, and each of the micro-lenses ML is respectively located above at least one of the device layers 210 , 210 ′, 210 ′′.
  • FIG. 8A to FIG. 8K are schematic flow chat diagrams illustrating a transfer-bonding method for light emitting devices according to a third embodiment.
  • the transfer-bonding method for light emitting devices of the present embodiment is similar to the transfer-bonding method for light emitting devices of the second embodiment, except for main differences illustrated in FIG. 8B to FIG. 8H . , the following is to provide detail descriptions in coordination with FIG. 8A to FIG. 8K .
  • a first type doped semiconductor layer 310 a , a light emitting layer 310 b and a second type doped semiconductor layer 310 c are formed on a growth substrate SUB.
  • the first type doped semiconductor layer 310 a is, for example, a N-type doped GaN epitaxial layer formed by an epitaxial process
  • the light emitting layer 310 b is, for example, a single or multiple quantum well light emitting layers formed through the epitaxial process
  • the second type doped semiconductor layer 310 c is, for example, a P-type doped GaN epitaxial layer formed through the epitaxial process.
  • One of ordinary skill in the art would be able to manufacture a photonic crystal based on actual design requirements, and no detail descriptions are elaborated in the present embodiment.
  • a plurality of electrodes 310 d′ are formed over the second type doped semiconductor layer 310 c , wherein the electrodes 310 d′ and the second type doped semiconductor layer 310 c have a ohmic contact in between.
  • a sacrificial layer 120 a is formed on the first substrate SUB 1 , so that the second type doped semiconductor layer 310 c is temporarily bonded with the sacrificial layer 120 a.
  • the first type doped semiconductor layer 310 a are separated from the growth substrate SUB.
  • a process of separating the first type doped semiconductor layer 310 a and the growth substrate SUB includes a laser lift-off technique.
  • one of ordinary skill in the art may selectively perform a thinning process of first type doped semiconductor layer 310 a (e.g., grinding or back etching), or to manufacture the photonic crystal on the first type doped semiconductor layer 310 a.
  • the first type semiconductor layer 310 a , the light emitting layer 310 b , the second type semiconductor layer 310 c , and the sacrificial layer 120 a are patterned, in order to form a plurality of first type semiconductor patterns 310 a′ , a plurality of light-emitting patterns 310 b ′, a plurality of second type semiconductor patterns 310 c′ and the sacrificial patterns 120 .
  • the first type semiconductor patterns 310 a′ , the light-emitting patterns 310 b′ , the second type semiconductor patterns 310 c′ , and the electrodes 310 d located on a same sacrificial pattern 120 constitute a device layer 310 .
  • a protective layer PV is formed over the first substrate SUB 1 to selectively cover parts of the device layers 310 and the sacrificial patterns 120 , wherein parts of the device layers 310 and the sacrificial patterns 120 are uncovered by the protective layer PV.
  • the protective layer PV is, for example, a photoresist material or other dielectric material, so as to ensure the device layers 310 covered by the protective layer PV are not to be separated from the first substrate SUB 1 during a subsequent removal process of the sacrificial patterns 120 .
  • a material of the protective layer PV may be a polyimide or other polymer material, and the material of the protective layer PV may also be a silicon oxide (SiOx), a silicon nitride (SiNx) or other inorganic dielectric material.
  • a second substrate SUB 2 is provided, wherein the second substrate SUB 2 is, for example, a stamp mold, and the stamp mold has a plurality of protrusions P.
  • the protrusions P over the second substrate SUB 2 are bonded with the device layers 310 uncovered by the protective layer PV.
  • the sacrificial patterns 120 uncovered by the protective layer PV are removed, so as to transfer-bond parts of the device layers 310 to the stamp mold (SUB 2 ).
  • the device layers 310 transfer-bonded to the stamp mold (SUB 2 ) are bonded with a circuit substrate SUB 3 to further transfer-bond the device layers 310 to the circuit substrate SUB 3 , wherein the circuit substrate SUB 3 is, for example, a circuit substrate (e.g., a complementary metal oxide semiconductor chip having a plurality of bonding pads PAD) in a monolithic micro-display.
  • the device layers 310 are, for example, bonded the bonding pads PAD over the second substrate SUB 2 through the conductive bumps B.
  • the conductive bumps B are gold bumps or other alloy bumps, and the bonding (electrical connection) between the conductive bumps B and the bonding pads PAD over the second substrate SUB 2 are achieved through reflow or other soldering process.
  • FIG. 8I after firstly transfer-bonded the device layers 310 to the second substrate SUB 2 and then to the circuit substrate SUB 3 , one of ordinary skill in the art may selectively repeat the aforementioned steps illustrated in FIG. 8A to FIG. 8H for at least once, so as to transfer-bond the device layers 310 ′ and the device layers 310 ′′ to the circuit substrate SUB 3 .
  • the device layers 310 , 310 ′, 310 ′′ capable of emitting different colored lights have different thicknesses, and the conductive bumps B, B′, B′′ bonded with the device layers 310 , 310 ′, 310 ′′ also have different heights, top surfaces of the device layers 310 , 310 ′, 310 ′′ can be located on a same level of height.
  • the present embodiment does not limit the top surfaces of the device layers 310 , 310 ′, 310 ′′ located on a same level of height, such that through adjusting the heights of the conductive bumps B, B′, B′′, the top surfaces of the device layers 310 , 310 ′, 310 ′′ may be respectively located on different level of heights.
  • the light emitting devices may be rapidly and efficiently transfer-bonded from a substrate to another substrate, so as to facilitate an application of the light emitting devices in the field of micro-display.

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